*
* Support functions for the OMAP internal DMA channels.
*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Converted DMA library into DMA platform driver.
+ * - G, Manjunath Kondaiah <manjugk@ti.com>
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
#undef DEBUG
-static u16 reg_map_omap1[] = {
- [GCR] = 0x400,
- [GSCR] = 0x404,
- [GRST1] = 0x408,
- [HW_ID] = 0x442,
- [PCH2_ID] = 0x444,
- [PCH0_ID] = 0x446,
- [PCH1_ID] = 0x448,
- [PCHG_ID] = 0x44a,
- [PCHD_ID] = 0x44c,
- [CAPS_0] = 0x44e,
- [CAPS_1] = 0x452,
- [CAPS_2] = 0x456,
- [CAPS_3] = 0x458,
- [CAPS_4] = 0x45a,
- [PCH2_SR] = 0x460,
- [PCH0_SR] = 0x480,
- [PCH1_SR] = 0x482,
- [PCHD_SR] = 0x4c0,
-
- /* Common Registers */
- [CSDP] = 0x00,
- [CCR] = 0x02,
- [CICR] = 0x04,
- [CSR] = 0x06,
- [CEN] = 0x10,
- [CFN] = 0x12,
- [CSFI] = 0x14,
- [CSEI] = 0x16,
- [CPC] = 0x18, /* 15xx only */
- [CSAC] = 0x18,
- [CDAC] = 0x1a,
- [CDEI] = 0x1c,
- [CDFI] = 0x1e,
- [CLNK_CTRL] = 0x28,
-
- /* Channel specific register offsets */
- [CSSA] = 0x08,
- [CDSA] = 0x0c,
- [COLOR] = 0x20,
- [CCR2] = 0x24,
- [LCH_CTRL] = 0x2a,
-};
-
-static u16 reg_map_omap2[] = {
- [REVISION] = 0x00,
- [GCR] = 0x78,
- [IRQSTATUS_L0] = 0x08,
- [IRQSTATUS_L1] = 0x0c,
- [IRQSTATUS_L2] = 0x10,
- [IRQSTATUS_L3] = 0x14,
- [IRQENABLE_L0] = 0x18,
- [IRQENABLE_L1] = 0x1c,
- [IRQENABLE_L2] = 0x20,
- [IRQENABLE_L3] = 0x24,
- [SYSSTATUS] = 0x28,
- [OCP_SYSCONFIG] = 0x2c,
- [CAPS_0] = 0x64,
- [CAPS_2] = 0x6c,
- [CAPS_3] = 0x70,
- [CAPS_4] = 0x74,
-
- /* Common register offsets */
- [CCR] = 0x80,
- [CLNK_CTRL] = 0x84,
- [CICR] = 0x88,
- [CSR] = 0x8c,
- [CSDP] = 0x90,
- [CEN] = 0x94,
- [CFN] = 0x98,
- [CSEI] = 0xa4,
- [CSFI] = 0xa8,
- [CDEI] = 0xac,
- [CDFI] = 0xb0,
- [CSAC] = 0xb4,
- [CDAC] = 0xb8,
-
- /* Channel specific register offsets */
- [CSSA] = 0x9c,
- [CDSA] = 0xa0,
- [CCEN] = 0xbc,
- [CCFN] = 0xc0,
- [COLOR] = 0xc4,
-
- /* OMAP4 specific registers */
- [CDP] = 0xd0,
- [CNDP] = 0xd4,
- [CCDN] = 0xd8,
-};
-
#ifndef CONFIG_ARCH_OMAP1
enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
+static struct omap_system_dma_plat_info *p;
+static struct omap_dma_dev_attr *d;
+
static int enable_1510_mode;
static u32 errata;
u32 dma_gcr;
} omap_dma_global_context;
-struct omap_dma_lch {
- int next_lch;
- int dev_id;
- u16 saved_csr;
- u16 enabled_irqs;
- const char *dev_name;
- void (*callback)(int lch, u16 ch_status, void *data);
- void *data;
-
-#ifndef CONFIG_ARCH_OMAP1
- /* required for Dynamic chaining */
- int prev_linked_ch;
- int next_linked_ch;
- int state;
- int chain_id;
-
- int status;
-#endif
- long flags;
-};
-
struct dma_link_info {
int *linked_dmach_q;
int no_of_lchs_linked;
static spinlock_t dma_chan_lock;
static struct omap_dma_lch *dma_chan;
-static void __iomem *omap_dma_base;
-static u16 *reg_map;
-static u8 dma_stride;
-static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
-
-static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
- INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
- INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
- INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
- INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
- INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
-};
static inline void disable_lnk(int lch);
static void omap_disable_channel_irq(int lch);
#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
__func__);
-static inline void dma_write(u32 val, int reg, int lch)
-{
- u8 stride;
- u32 offset;
-
- stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
- offset = reg_map[reg] + (stride * lch);
-
- if (dma_stride == 0x40) {
- __raw_writew(val, omap_dma_base + offset);
- if ((reg > CLNK_CTRL && reg < CCEN) ||
- (reg > PCHD_ID && reg < CAPS_2)) {
- u32 offset2 = reg_map[reg] + 2 + (stride * lch);
- __raw_writew(val >> 16, omap_dma_base + offset2);
- }
- } else {
- __raw_writel(val, omap_dma_base + offset);
- }
-}
-
-static inline u32 dma_read(int reg, int lch)
-{
- u8 stride;
- u32 offset, val;
-
- stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
- offset = reg_map[reg] + (stride * lch);
-
- if (dma_stride == 0x40) {
- val = __raw_readw(omap_dma_base + offset);
- if ((reg > CLNK_CTRL && reg < CCEN) ||
- (reg > PCHD_ID && reg < CAPS_2)) {
- u16 upper;
- u32 offset2 = reg_map[reg] + 2 + (stride * lch);
- upper = __raw_readw(omap_dma_base + offset2);
- val |= (upper << 16);
- }
- } else {
- val = __raw_readl(omap_dma_base + offset);
- }
- return val;
-}
-
#ifdef CONFIG_ARCH_OMAP15XX
/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
-static int omap_dma_in_1510_mode(void)
+int omap_dma_in_1510_mode(void)
{
return enable_1510_mode;
}
#define set_gdma_dev(req, dev) do {} while (0)
#endif
-/* Omap1 only */
-static void clear_lch_regs(int lch)
-{
- int i = dma_common_ch_start;
-
- for (; i <= dma_common_ch_end; i += 1)
- dma_write(0, i, lch);
-}
-
void omap_set_dma_priority(int lch, int dst_port, int priority)
{
unsigned long reg;
if (cpu_class_is_omap2()) {
u32 ccr;
- ccr = dma_read(CCR, lch);
+ ccr = p->dma_read(CCR, lch);
if (priority)
ccr |= (1 << 6);
else
ccr &= ~(1 << 6);
- dma_write(ccr, CCR, lch);
+ p->dma_write(ccr, CCR, lch);
}
}
EXPORT_SYMBOL(omap_set_dma_priority);
{
u32 l;
- l = dma_read(CSDP, lch);
+ l = p->dma_read(CSDP, lch);
l &= ~0x03;
l |= data_type;
- dma_write(l, CSDP, lch);
+ p->dma_write(l, CSDP, lch);
if (cpu_class_is_omap1()) {
u16 ccr;
- ccr = dma_read(CCR, lch);
+ ccr = p->dma_read(CCR, lch);
ccr &= ~(1 << 5);
if (sync_mode == OMAP_DMA_SYNC_FRAME)
ccr |= 1 << 5;
- dma_write(ccr, CCR, lch);
+ p->dma_write(ccr, CCR, lch);
- ccr = dma_read(CCR2, lch);
+ ccr = p->dma_read(CCR2, lch);
ccr &= ~(1 << 2);
if (sync_mode == OMAP_DMA_SYNC_BLOCK)
ccr |= 1 << 2;
- dma_write(ccr, CCR2, lch);
+ p->dma_write(ccr, CCR2, lch);
}
if (cpu_class_is_omap2() && dma_trigger) {
u32 val;
- val = dma_read(CCR, lch);
+ val = p->dma_read(CCR, lch);
/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
val &= ~((1 << 23) | (3 << 19) | 0x1f);
} else {
val &= ~(1 << 24); /* dest synch */
}
- dma_write(val, CCR, lch);
+ p->dma_write(val, CCR, lch);
}
- dma_write(elem_count, CEN, lch);
- dma_write(frame_count, CFN, lch);
+ p->dma_write(elem_count, CEN, lch);
+ p->dma_write(frame_count, CFN, lch);
}
EXPORT_SYMBOL(omap_set_dma_transfer_params);
if (cpu_class_is_omap1()) {
u16 w;
- w = dma_read(CCR2, lch);
+ w = p->dma_read(CCR2, lch);
w &= ~0x03;
switch (mode) {
default:
BUG();
}
- dma_write(w, CCR2, lch);
+ p->dma_write(w, CCR2, lch);
- w = dma_read(LCH_CTRL, lch);
+ w = p->dma_read(LCH_CTRL, lch);
w &= ~0x0f;
/* Default is channel type 2D */
if (mode) {
- dma_write(color, COLOR, lch);
+ p->dma_write(color, COLOR, lch);
w |= 1; /* Channel type G */
}
- dma_write(w, LCH_CTRL, lch);
+ p->dma_write(w, LCH_CTRL, lch);
}
if (cpu_class_is_omap2()) {
u32 val;
- val = dma_read(CCR, lch);
+ val = p->dma_read(CCR, lch);
val &= ~((1 << 17) | (1 << 16));
switch (mode) {
default:
BUG();
}
- dma_write(val, CCR, lch);
+ p->dma_write(val, CCR, lch);
color &= 0xffffff;
- dma_write(color, COLOR, lch);
+ p->dma_write(color, COLOR, lch);
}
}
EXPORT_SYMBOL(omap_set_dma_color_mode);
if (cpu_class_is_omap2()) {
u32 csdp;
- csdp = dma_read(CSDP, lch);
+ csdp = p->dma_read(CSDP, lch);
csdp &= ~(0x3 << 16);
csdp |= (mode << 16);
- dma_write(csdp, CSDP, lch);
+ p->dma_write(csdp, CSDP, lch);
}
}
EXPORT_SYMBOL(omap_set_dma_write_mode);
if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
u32 l;
- l = dma_read(LCH_CTRL, lch);
+ l = p->dma_read(LCH_CTRL, lch);
l &= ~0x7;
l |= mode;
- dma_write(l, LCH_CTRL, lch);
+ p->dma_write(l, LCH_CTRL, lch);
}
}
EXPORT_SYMBOL(omap_set_dma_channel_mode);
if (cpu_class_is_omap1()) {
u16 w;
- w = dma_read(CSDP, lch);
+ w = p->dma_read(CSDP, lch);
w &= ~(0x1f << 2);
w |= src_port << 2;
- dma_write(w, CSDP, lch);
+ p->dma_write(w, CSDP, lch);
}
- l = dma_read(CCR, lch);
+ l = p->dma_read(CCR, lch);
l &= ~(0x03 << 12);
l |= src_amode << 12;
- dma_write(l, CCR, lch);
+ p->dma_write(l, CCR, lch);
- dma_write(src_start, CSSA, lch);
+ p->dma_write(src_start, CSSA, lch);
- dma_write(src_ei, CSEI, lch);
- dma_write(src_fi, CSFI, lch);
+ p->dma_write(src_ei, CSEI, lch);
+ p->dma_write(src_fi, CSFI, lch);
}
EXPORT_SYMBOL(omap_set_dma_src_params);
if (cpu_class_is_omap2())
return;
- dma_write(eidx, CSEI, lch);
- dma_write(fidx, CSFI, lch);
+ p->dma_write(eidx, CSEI, lch);
+ p->dma_write(fidx, CSFI, lch);
}
EXPORT_SYMBOL(omap_set_dma_src_index);
{
u32 l;
- l = dma_read(CSDP, lch);
+ l = p->dma_read(CSDP, lch);
l &= ~(1 << 6);
if (enable)
l |= (1 << 6);
- dma_write(l, CSDP, lch);
+ p->dma_write(l, CSDP, lch);
}
EXPORT_SYMBOL(omap_set_dma_src_data_pack);
unsigned int burst = 0;
u32 l;
- l = dma_read(CSDP, lch);
+ l = p->dma_read(CSDP, lch);
l &= ~(0x03 << 7);
switch (burst_mode) {
}
l |= (burst << 7);
- dma_write(l, CSDP, lch);
+ p->dma_write(l, CSDP, lch);
}
EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
u32 l;
if (cpu_class_is_omap1()) {
- l = dma_read(CSDP, lch);
+ l = p->dma_read(CSDP, lch);
l &= ~(0x1f << 9);
l |= dest_port << 9;
- dma_write(l, CSDP, lch);
+ p->dma_write(l, CSDP, lch);
}
- l = dma_read(CCR, lch);
+ l = p->dma_read(CCR, lch);
l &= ~(0x03 << 14);
l |= dest_amode << 14;
- dma_write(l, CCR, lch);
+ p->dma_write(l, CCR, lch);
- dma_write(dest_start, CDSA, lch);
+ p->dma_write(dest_start, CDSA, lch);
- dma_write(dst_ei, CDEI, lch);
- dma_write(dst_fi, CDFI, lch);
+ p->dma_write(dst_ei, CDEI, lch);
+ p->dma_write(dst_fi, CDFI, lch);
}
EXPORT_SYMBOL(omap_set_dma_dest_params);
if (cpu_class_is_omap2())
return;
- dma_write(eidx, CDEI, lch);
- dma_write(fidx, CDFI, lch);
+ p->dma_write(eidx, CDEI, lch);
+ p->dma_write(fidx, CDFI, lch);
}
EXPORT_SYMBOL(omap_set_dma_dest_index);
{
u32 l;
- l = dma_read(CSDP, lch);
+ l = p->dma_read(CSDP, lch);
l &= ~(1 << 13);
if (enable)
l |= 1 << 13;
- dma_write(l, CSDP, lch);
+ p->dma_write(l, CSDP, lch);
}
EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
unsigned int burst = 0;
u32 l;
- l = dma_read(CSDP, lch);
+ l = p->dma_read(CSDP, lch);
l &= ~(0x03 << 14);
switch (burst_mode) {
return;
}
l |= (burst << 14);
- dma_write(l, CSDP, lch);
+ p->dma_write(l, CSDP, lch);
}
EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
/* Clear CSR */
if (cpu_class_is_omap1())
- status = dma_read(CSR, lch);
+ status = p->dma_read(CSR, lch);
else if (cpu_class_is_omap2())
- dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
+ p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
/* Enable some nice interrupts. */
- dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
+ p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
}
static void omap_disable_channel_irq(int lch)
{
if (cpu_class_is_omap2())
- dma_write(0, CICR, lch);
+ p->dma_write(0, CICR, lch);
}
void omap_enable_dma_irq(int lch, u16 bits)
{
u32 l;
- l = dma_read(CLNK_CTRL, lch);
+ l = p->dma_read(CLNK_CTRL, lch);
if (cpu_class_is_omap1())
l &= ~(1 << 14);
l = dma_chan[lch].next_linked_ch | (1 << 15);
#endif
- dma_write(l, CLNK_CTRL, lch);
+ p->dma_write(l, CLNK_CTRL, lch);
}
static inline void disable_lnk(int lch)
{
u32 l;
- l = dma_read(CLNK_CTRL, lch);
+ l = p->dma_read(CLNK_CTRL, lch);
/* Disable interrupts */
if (cpu_class_is_omap1()) {
- dma_write(0, CICR, lch);
+ p->dma_write(0, CICR, lch);
/* Set the STOP_LNK bit */
l |= 1 << 14;
}
l &= ~(1 << 15);
}
- dma_write(l, CLNK_CTRL, lch);
+ p->dma_write(l, CLNK_CTRL, lch);
dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
}
return;
spin_lock_irqsave(&dma_chan_lock, flags);
- val = dma_read(IRQENABLE_L0, lch);
+ val = p->dma_read(IRQENABLE_L0, lch);
val |= 1 << lch;
- dma_write(val, IRQENABLE_L0, lch);
+ p->dma_write(val, IRQENABLE_L0, lch);
spin_unlock_irqrestore(&dma_chan_lock, flags);
}
return;
spin_lock_irqsave(&dma_chan_lock, flags);
- val = dma_read(IRQENABLE_L0, lch);
+ val = p->dma_read(IRQENABLE_L0, lch);
val &= ~(1 << lch);
- dma_write(val, IRQENABLE_L0, lch);
+ p->dma_write(val, IRQENABLE_L0, lch);
spin_unlock_irqrestore(&dma_chan_lock, flags);
}
chan = dma_chan + free_ch;
chan->dev_id = dev_id;
- if (cpu_class_is_omap1())
- clear_lch_regs(free_ch);
+ if (p->clear_lch_regs)
+ p->clear_lch_regs(free_ch);
if (cpu_class_is_omap2())
omap_clear_dma(free_ch);
* Disable the 1510 compatibility mode and set the sync device
* id.
*/
- dma_write(dev_id | (1 << 10), CCR, free_ch);
+ p->dma_write(dev_id | (1 << 10), CCR, free_ch);
} else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
- dma_write(dev_id, CCR, free_ch);
+ p->dma_write(dev_id, CCR, free_ch);
}
if (cpu_class_is_omap2()) {
omap2_enable_irq_lch(free_ch);
omap_enable_channel_irq(free_ch);
/* Clear the CSR register and IRQ status register */
- dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
- dma_write(1 << free_ch, IRQSTATUS_L0, 0);
+ p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
+ p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
}
*dma_ch_out = free_ch;
if (cpu_class_is_omap1()) {
/* Disable all DMA interrupts for the channel. */
- dma_write(0, CICR, lch);
+ p->dma_write(0, CICR, lch);
/* Make sure the DMA transfer is stopped. */
- dma_write(0, CCR, lch);
+ p->dma_write(0, CCR, lch);
}
if (cpu_class_is_omap2()) {
omap2_disable_irq_lch(lch);
/* Clear the CSR register and IRQ status register */
- dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
- dma_write(1 << lch, IRQSTATUS_L0, lch);
+ p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
+ p->dma_write(1 << lch, IRQSTATUS_L0, lch);
/* Disable all DMA interrupts for the channel. */
- dma_write(0, CICR, lch);
+ p->dma_write(0, CICR, lch);
/* Make sure the DMA transfer is stopped. */
- dma_write(0, CCR, lch);
+ p->dma_write(0, CCR, lch);
omap_clear_dma(lch);
}
reg |= (0x3 & tparams) << 12;
reg |= (arb_rate & 0xff) << 16;
- dma_write(reg, GCR, 0);
+ p->dma_write(reg, GCR, 0);
}
EXPORT_SYMBOL(omap_dma_set_global_params);
printk(KERN_ERR "Invalid channel id\n");
return -EINVAL;
}
- l = dma_read(CCR, lch);
+ l = p->dma_read(CCR, lch);
l &= ~((1 << 6) | (1 << 26));
if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
else
l |= ((read_prio & 0x1) << 6);
- dma_write(l, CCR, lch);
+ p->dma_write(l, CCR, lch);
return 0;
}
unsigned long flags;
local_irq_save(flags);
-
- if (cpu_class_is_omap1()) {
- u32 l;
-
- l = dma_read(CCR, lch);
- l &= ~OMAP_DMA_CCR_EN;
- dma_write(l, CCR, lch);
-
- /* Clear pending interrupts */
- l = dma_read(CSR, lch);
- }
-
- if (cpu_class_is_omap2()) {
- int i = dma_common_ch_start;
- for (; i <= dma_common_ch_end; i += 1)
- dma_write(0, i, lch);
- }
-
+ p->clear_dma(lch);
local_irq_restore(flags);
}
EXPORT_SYMBOL(omap_clear_dma);
* before starting dma transfer.
*/
if (cpu_is_omap15xx())
- dma_write(0, CPC, lch);
+ p->dma_write(0, CPC, lch);
else
- dma_write(0, CDAC, lch);
+ p->dma_write(0, CDAC, lch);
if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
int next_lch, cur_lch;
- char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
+ char dma_chan_link_map[dma_lch_count];
dma_chan_link_map[lch] = 1;
/* Set the link register of the first channel */
cur_lch = next_lch;
} while (next_lch != -1);
} else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
- dma_write(lch, CLNK_CTRL, lch);
+ p->dma_write(lch, CLNK_CTRL, lch);
omap_enable_channel_irq(lch);
- l = dma_read(CCR, lch);
+ l = p->dma_read(CCR, lch);
if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
l |= OMAP_DMA_CCR_EN;
- dma_write(l, CCR, lch);
+ p->dma_write(l, CCR, lch);
dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
}
/* Disable all interrupts on the channel */
if (cpu_class_is_omap1())
- dma_write(0, CICR, lch);
+ p->dma_write(0, CICR, lch);
- l = dma_read(CCR, lch);
+ l = p->dma_read(CCR, lch);
if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
(l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
int i = 0;
u32 sys_cf;
/* Configure No-Standby */
- l = dma_read(OCP_SYSCONFIG, lch);
+ l = p->dma_read(OCP_SYSCONFIG, lch);
sys_cf = l;
l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
- dma_write(l , OCP_SYSCONFIG, 0);
+ p->dma_write(l , OCP_SYSCONFIG, 0);
- l = dma_read(CCR, lch);
+ l = p->dma_read(CCR, lch);
l &= ~OMAP_DMA_CCR_EN;
- dma_write(l, CCR, lch);
+ p->dma_write(l, CCR, lch);
/* Wait for sDMA FIFO drain */
- l = dma_read(CCR, lch);
+ l = p->dma_read(CCR, lch);
while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
OMAP_DMA_CCR_WR_ACTIVE))) {
udelay(5);
i++;
- l = dma_read(CCR, lch);
+ l = p->dma_read(CCR, lch);
}
if (i >= 100)
printk(KERN_ERR "DMA drain did not complete on "
"lch %d\n", lch);
/* Restore OCP_SYSCONFIG */
- dma_write(sys_cf, OCP_SYSCONFIG, lch);
+ p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
} else {
l &= ~OMAP_DMA_CCR_EN;
- dma_write(l, CCR, lch);
+ p->dma_write(l, CCR, lch);
}
if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
int next_lch, cur_lch = lch;
- char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
+ char dma_chan_link_map[dma_lch_count];
memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
do {
dma_addr_t offset = 0;
if (cpu_is_omap15xx())
- offset = dma_read(CPC, lch);
+ offset = p->dma_read(CPC, lch);
else
- offset = dma_read(CSAC, lch);
+ offset = p->dma_read(CSAC, lch);
if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
- offset = dma_read(CSAC, lch);
+ offset = p->dma_read(CSAC, lch);
if (cpu_class_is_omap1())
- offset |= (dma_read(CSSA, lch) & 0xFFFF0000);
+ offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
return offset;
}
dma_addr_t offset = 0;
if (cpu_is_omap15xx())
- offset = dma_read(CPC, lch);
+ offset = p->dma_read(CPC, lch);
else
- offset = dma_read(CDAC, lch);
+ offset = p->dma_read(CDAC, lch);
/*
* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
* read before the DMA controller finished disabling the channel.
*/
if (!cpu_is_omap15xx() && offset == 0)
- offset = dma_read(CDAC, lch);
+ offset = p->dma_read(CDAC, lch);
if (cpu_class_is_omap1())
- offset |= (dma_read(CDSA, lch) & 0xFFFF0000);
+ offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
return offset;
}
int omap_get_dma_active_status(int lch)
{
- return (dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
+ return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
}
EXPORT_SYMBOL(omap_get_dma_active_status);
return 1;
for (lch = 0; lch < dma_chan_count; lch++)
- if (dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
+ if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
return 1;
return 0;
{
if (omap_dma_in_1510_mode()) {
if (lch_head == lch_queue) {
- dma_write(dma_read(CCR, lch_head) | (3 << 8),
+ p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
CCR, lch_head);
return;
}
{
if (omap_dma_in_1510_mode()) {
if (lch_head == lch_queue) {
- dma_write(dma_read(CCR, lch_head) & ~(3 << 8),
+ p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
CCR, lch_head);
return;
}
}
EXPORT_SYMBOL(omap_dma_unlink_lch);
-/*----------------------------------------------------------------------------*/
-
#ifndef CONFIG_ARCH_OMAP1
/* Create chain of DMA channesls */
static void create_dma_lch_chain(int lch_head, int lch_queue)
lch_queue;
}
- l = dma_read(CLNK_CTRL, lch_head);
+ l = p->dma_read(CLNK_CTRL, lch_head);
l &= ~(0x1f);
l |= lch_queue;
- dma_write(l, CLNK_CTRL, lch_head);
+ p->dma_write(l, CLNK_CTRL, lch_head);
- l = dma_read(CLNK_CTRL, lch_queue);
+ l = p->dma_read(CLNK_CTRL, lch_queue);
l &= ~(0x1f);
l |= (dma_chan[lch_queue].next_linked_ch);
- dma_write(l, CLNK_CTRL, lch_queue);
+ p->dma_write(l, CLNK_CTRL, lch_queue);
}
/**
/* Set the params to the free channel */
if (src_start != 0)
- dma_write(src_start, CSSA, lch);
+ p->dma_write(src_start, CSSA, lch);
if (dest_start != 0)
- dma_write(dest_start, CDSA, lch);
+ p->dma_write(dest_start, CDSA, lch);
/* Write the buffer size */
- dma_write(elem_count, CEN, lch);
- dma_write(frame_count, CFN, lch);
+ p->dma_write(elem_count, CEN, lch);
+ p->dma_write(frame_count, CFN, lch);
/*
* If the chain is dynamically linked,
enable_lnk(dma_chan[lch].prev_linked_ch);
dma_chan[lch].state = DMA_CH_QUEUED;
start_dma = 0;
- if (0 == ((1 << 7) & dma_read(
+ if (0 == ((1 << 7) & p->dma_read(
CCR, dma_chan[lch].prev_linked_ch))) {
disable_lnk(dma_chan[lch].
prev_linked_ch);
}
omap_enable_channel_irq(lch);
- l = dma_read(CCR, lch);
+ l = p->dma_read(CCR, lch);
if ((0 == (l & (1 << 24))))
l &= ~(1 << 25);
l |= (1 << 7);
dma_chan[lch].state = DMA_CH_STARTED;
pr_debug("starting %d\n", lch);
- dma_write(l, CCR, lch);
+ p->dma_write(l, CCR, lch);
} else
start_dma = 0;
} else {
if (0 == (l & (1 << 7)))
- dma_write(l, CCR, lch);
+ p->dma_write(l, CCR, lch);
}
dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
}
omap_enable_channel_irq(channels[0]);
}
- l = dma_read(CCR, channels[0]);
+ l = p->dma_read(CCR, channels[0]);
l |= (1 << 7);
dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
dma_chan[channels[0]].state = DMA_CH_STARTED;
l &= ~(1 << 25);
else
l |= (1 << 25);
- dma_write(l, CCR, channels[0]);
+ p->dma_write(l, CCR, channels[0]);
dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
channels = dma_linked_lch[chain_id].linked_dmach_q;
if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
- sys_cf = dma_read(OCP_SYSCONFIG, 0);
+ sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
l = sys_cf;
/* Middle mode reg set no Standby */
l &= ~((1 << 12)|(1 << 13));
- dma_write(l, OCP_SYSCONFIG, 0);
+ p->dma_write(l, OCP_SYSCONFIG, 0);
}
for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
/* Stop the Channel transmission */
- l = dma_read(CCR, channels[i]);
+ l = p->dma_read(CCR, channels[i]);
l &= ~(1 << 7);
- dma_write(l, CCR, channels[i]);
+ p->dma_write(l, CCR, channels[i]);
/* Disable the link in all the channels */
disable_lnk(channels[i]);
OMAP_DMA_CHAIN_QINIT(chain_id);
if (IS_DMA_ERRATA(DMA_ERRATA_i88))
- dma_write(sys_cf, OCP_SYSCONFIG, 0);
+ p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
return 0;
}
/* Get the current channel */
lch = channels[dma_linked_lch[chain_id].q_head];
- *ei = dma_read(CCEN, lch);
- *fi = dma_read(CCFN, lch);
+ *ei = p->dma_read(CCEN, lch);
+ *fi = p->dma_read(CCFN, lch);
return 0;
}
/* Get the current channel */
lch = channels[dma_linked_lch[chain_id].q_head];
- return dma_read(CDAC, lch);
+ return p->dma_read(CDAC, lch);
}
EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
/* Get the current channel */
lch = channels[dma_linked_lch[chain_id].q_head];
- return dma_read(CSAC, lch);
+ return p->dma_read(CSAC, lch);
}
EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
#endif /* ifndef CONFIG_ARCH_OMAP1 */
csr = dma_chan[ch].saved_csr;
dma_chan[ch].saved_csr = 0;
} else
- csr = dma_read(CSR, ch);
+ csr = p->dma_read(CSR, ch);
if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
dma_chan[ch + 6].saved_csr = csr >> 7;
csr &= 0x7f;
static int omap2_dma_handle_ch(int ch)
{
- u32 status = dma_read(CSR, ch);
+ u32 status = p->dma_read(CSR, ch);
if (!status) {
if (printk_ratelimit())
printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
ch);
- dma_write(1 << ch, IRQSTATUS_L0, ch);
+ p->dma_write(1 << ch, IRQSTATUS_L0, ch);
return 0;
}
if (unlikely(dma_chan[ch].dev_id == -1)) {
if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
u32 ccr;
- ccr = dma_read(CCR, ch);
+ ccr = p->dma_read(CCR, ch);
ccr &= ~OMAP_DMA_CCR_EN;
- dma_write(ccr, CCR, ch);
+ p->dma_write(ccr, CCR, ch);
dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
}
}
printk(KERN_INFO "DMA misaligned error with device %d\n",
dma_chan[ch].dev_id);
- dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, ch);
- dma_write(1 << ch, IRQSTATUS_L0, ch);
+ p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, ch);
+ p->dma_write(1 << ch, IRQSTATUS_L0, ch);
/* read back the register to flush the write */
- dma_read(IRQSTATUS_L0, ch);
+ p->dma_read(IRQSTATUS_L0, ch);
/* If the ch is not chained then chain_id will be -1 */
if (dma_chan[ch].chain_id != -1) {
int chain_id = dma_chan[ch].chain_id;
dma_chan[ch].state = DMA_CH_NOTSTARTED;
- if (dma_read(CLNK_CTRL, ch) & (1 << 15))
+ if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
dma_chan[dma_chan[ch].next_linked_ch].state =
DMA_CH_STARTED;
if (dma_linked_lch[chain_id].chain_mode ==
if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
OMAP_DMA_CHAIN_INCQHEAD(chain_id);
- status = dma_read(CSR, ch);
+ status = p->dma_read(CSR, ch);
}
- dma_write(status, CSR, ch);
+ p->dma_write(status, CSR, ch);
if (likely(dma_chan[ch].callback != NULL))
dma_chan[ch].callback(ch, status, dma_chan[ch].data);
u32 val, enable_reg;
int i;
- val = dma_read(IRQSTATUS_L0, 0);
+ val = p->dma_read(IRQSTATUS_L0, 0);
if (val == 0) {
if (printk_ratelimit())
printk(KERN_WARNING "Spurious DMA IRQ\n");
return IRQ_HANDLED;
}
- enable_reg = dma_read(IRQENABLE_L0, 0);
+ enable_reg = p->dma_read(IRQENABLE_L0, 0);
val &= enable_reg; /* Dispatch only relevant interrupts */
for (i = 0; i < dma_lch_count && val != 0; i++) {
if (val & 1)
void omap_dma_global_context_save(void)
{
omap_dma_global_context.dma_irqenable_l0 =
- dma_read(IRQENABLE_L0, 0);
+ p->dma_read(IRQENABLE_L0, 0);
omap_dma_global_context.dma_ocp_sysconfig =
- dma_read(OCP_SYSCONFIG, 0);
- omap_dma_global_context.dma_gcr = dma_read(GCR, 0);
+ p->dma_read(OCP_SYSCONFIG, 0);
+ omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
}
void omap_dma_global_context_restore(void)
{
int ch;
- dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
- dma_write(omap_dma_global_context.dma_ocp_sysconfig,
+ p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
+ p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
OCP_SYSCONFIG, 0);
- dma_write(omap_dma_global_context.dma_irqenable_l0,
+ p->dma_write(omap_dma_global_context.dma_irqenable_l0,
IRQENABLE_L0, 0);
if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
- dma_write(0x3 , IRQSTATUS_L0, 0);
+ p->dma_write(0x3 , IRQSTATUS_L0, 0);
for (ch = 0; ch < dma_chan_count; ch++)
if (dma_chan[ch].dev_id != -1)
omap_clear_dma(ch);
}
-static void configure_dma_errata(void)
+static int __devinit omap_system_dma_probe(struct platform_device *pdev)
{
-
- /*
- * Errata applicable for OMAP2430ES1.0 and all omap2420
- *
- * I.
- * Erratum ID: Not Available
- * Inter Frame DMA buffering issue DMA will wrongly
- * buffer elements if packing and bursting is enabled. This might
- * result in data gets stalled in FIFO at the end of the block.
- * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
- * guarantee no data will stay in the DMA FIFO in case inter frame
- * buffering occurs
- *
- * II.
- * Erratum ID: Not Available
- * DMA may hang when several channels are used in parallel
- * In the following configuration, DMA channel hanging can occur:
- * a. Channel i, hardware synchronized, is enabled
- * b. Another channel (Channel x), software synchronized, is enabled.
- * c. Channel i is disabled before end of transfer
- * d. Channel i is reenabled.
- * e. Steps 1 to 4 are repeated a certain number of times.
- * f. A third channel (Channel y), software synchronized, is enabled.
- * Channel x and Channel y may hang immediately after step 'f'.
- * Workaround:
- * For any channel used - make sure NextLCH_ID is set to the value j.
- */
- if (cpu_is_omap2420() || (cpu_is_omap2430() &&
- (omap_type() == OMAP2430_REV_ES1_0))) {
- SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
- SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
- }
-
- /*
- * Erratum ID: i378: OMAP2plus: sDMA Channel is not disabled
- * after a transaction error.
- * Workaround: SW should explicitely disable the channel.
- */
- if (cpu_class_is_omap2())
- SET_DMA_ERRATA(DMA_ERRATA_i378);
-
- /*
- * Erratum ID: i541: sDMA FIFO draining does not finish
- * If sDMA channel is disabled on the fly, sDMA enters standby even
- * through FIFO Drain is still in progress
- * Workaround: Put sDMA in NoStandby more before a logical channel is
- * disabled, then put it back to SmartStandby right after the channel
- * finishes FIFO draining.
- */
- if (cpu_is_omap34xx())
- SET_DMA_ERRATA(DMA_ERRATA_i541);
-
- /*
- * Erratum ID: i88 : Special programming model needed to disable DMA
- * before end of block.
- * Workaround: software must ensure that the DMA is configured in No
- * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
- */
- if (cpu_is_omap34xx() && (omap_type() == OMAP3430_REV_ES1_0))
- SET_DMA_ERRATA(DMA_ERRATA_i88);
-
- /*
- * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
- * read before the DMA controller finished disabling the channel.
- */
- if (!cpu_is_omap15xx())
- SET_DMA_ERRATA(DMA_ERRATA_3_3);
-
- /*
- * Erratum ID: Not Available
- * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
- * after secure sram context save and restore.
- * Work around: Hence we need to manually clear those IRQs to avoid
- * spurious interrupts. This affects only secure devices.
- */
- if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
- SET_DMA_ERRATA(DMA_ROMCODE_BUG);
-}
-
-/*----------------------------------------------------------------------------*/
-
-static int __init omap_init_dma(void)
-{
- unsigned long base;
- int ch, r;
-
- if (cpu_class_is_omap1()) {
- base = OMAP1_DMA_BASE;
- dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
- } else if (cpu_is_omap24xx()) {
- base = OMAP24XX_DMA4_BASE;
- dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
- } else if (cpu_is_omap34xx()) {
- base = OMAP34XX_DMA4_BASE;
- dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
- } else if (cpu_is_omap44xx()) {
- base = OMAP44XX_DMA4_BASE;
- dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
- } else {
- pr_err("DMA init failed for unsupported omap\n");
- return -ENODEV;
+ int ch, ret = 0;
+ int dma_irq;
+ char irq_name[4];
+ int irq_rel;
+
+ p = pdev->dev.platform_data;
+ if (!p) {
+ dev_err(&pdev->dev, "%s: System DMA initialized without"
+ "platform data\n", __func__);
+ return -EINVAL;
}
- omap_dma_base = ioremap(base, SZ_4K);
- BUG_ON(!omap_dma_base);
-
- if (cpu_class_is_omap1()) {
- dma_stride = 0x40;
- reg_map = reg_map_omap1;
- dma_common_ch_start = CPC;
- dma_common_ch_end = COLOR;
- } else {
- dma_stride = 0x60;
- reg_map = reg_map_omap2;
- dma_common_ch_start = CSDP;
- if (cpu_is_omap3630() || cpu_is_omap4430())
- dma_common_ch_end = CCDN;
- else
- dma_common_ch_end = CCFN;
- }
+ d = p->dma_attr;
+ errata = p->errata;
- if (cpu_class_is_omap2() && omap_dma_reserve_channels
+ if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
&& (omap_dma_reserve_channels <= dma_lch_count))
- dma_lch_count = omap_dma_reserve_channels;
+ d->lch_count = omap_dma_reserve_channels;
- dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
- GFP_KERNEL);
- if (!dma_chan) {
- r = -ENOMEM;
- goto out_unmap;
- }
+ dma_lch_count = d->lch_count;
+ dma_chan_count = dma_lch_count;
+ dma_chan = d->chan;
+ enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
if (cpu_class_is_omap2()) {
dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
dma_lch_count, GFP_KERNEL);
if (!dma_linked_lch) {
- r = -ENOMEM;
- goto out_free;
+ ret = -ENOMEM;
+ goto exit_dma_lch_fail;
}
}
- if (cpu_is_omap15xx()) {
- printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
- dma_chan_count = 9;
- enable_1510_mode = 1;
- } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
- printk(KERN_INFO "OMAP DMA hardware version %d\n",
- dma_read(HW_ID, 0));
- printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
- dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
- dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
- dma_read(CAPS_4, 0));
- if (!enable_1510_mode) {
- u16 w;
-
- /* Disable OMAP 3.0/3.1 compatibility mode. */
- w = dma_read(GSCR, 0);
- w |= 1 << 3;
- dma_write(w, GSCR, 0);
- dma_chan_count = 16;
- } else
- dma_chan_count = 9;
- } else if (cpu_class_is_omap2()) {
- u8 revision = dma_read(REVISION, 0) & 0xff;
- printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
- revision >> 4, revision & 0xf);
- dma_chan_count = dma_lch_count;
- } else {
- dma_chan_count = 0;
- return 0;
- }
-
spin_lock_init(&dma_chan_lock);
-
for (ch = 0; ch < dma_chan_count; ch++) {
omap_clear_dma(ch);
if (cpu_class_is_omap2())
* request_irq() doesn't like dev_id (ie. ch) being
* zero, so we have to kludge around this.
*/
- r = request_irq(omap1_dma_irq[ch],
+ sprintf(&irq_name[0], "%d", ch);
+ dma_irq = platform_get_irq_byname(pdev, irq_name);
+
+ if (dma_irq < 0) {
+ ret = dma_irq;
+ goto exit_dma_irq_fail;
+ }
+
+ /* INT_DMA_LCD is handled in lcd_dma.c */
+ if (dma_irq == INT_DMA_LCD)
+ continue;
+
+ ret = request_irq(dma_irq,
omap1_dma_irq_handler, 0, "DMA",
(void *) (ch + 1));
- if (r != 0) {
- int i;
-
- printk(KERN_ERR "unable to request IRQ %d "
- "for DMA (error %d)\n",
- omap1_dma_irq[ch], r);
- for (i = 0; i < ch; i++)
- free_irq(omap1_dma_irq[i],
- (void *) (i + 1));
- goto out_free;
- }
+ if (ret != 0)
+ goto exit_dma_irq_fail;
}
}
DMA_DEFAULT_FIFO_DEPTH, 0);
if (cpu_class_is_omap2()) {
- int irq;
- if (cpu_is_omap44xx())
- irq = OMAP44XX_IRQ_SDMA_0;
- else
- irq = INT_24XX_SDMA_IRQ0;
- setup_irq(irq, &omap24xx_dma_irq);
- }
-
- if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
- /* Enable smartidle idlemodes and autoidle */
- u32 v = dma_read(OCP_SYSCONFIG, 0);
- v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
- DMA_SYSCONFIG_SIDLEMODE_MASK |
- DMA_SYSCONFIG_AUTOIDLE);
- v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
- DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
- DMA_SYSCONFIG_AUTOIDLE);
- dma_write(v , OCP_SYSCONFIG, 0);
- /* reserve dma channels 0 and 1 in high security devices */
- if (cpu_is_omap34xx() &&
- (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
- printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
- "HS ROM code\n");
- dma_chan[0].dev_id = 0;
- dma_chan[1].dev_id = 1;
+ strcpy(irq_name, "0");
+ dma_irq = platform_get_irq_byname(pdev, irq_name);
+ if (dma_irq < 0) {
+ dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
+ goto exit_dma_lch_fail;
+ }
+ ret = setup_irq(dma_irq, &omap24xx_dma_irq);
+ if (ret) {
+ dev_err(&pdev->dev, "set_up failed for IRQ %d"
+ "for DMA (error %d)\n", dma_irq, ret);
+ goto exit_dma_lch_fail;
}
}
- configure_dma_errata();
+ /* reserve dma channels 0 and 1 in high security devices */
+ if (cpu_is_omap34xx() &&
+ (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
+ printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
+ "HS ROM code\n");
+ dma_chan[0].dev_id = 0;
+ dma_chan[1].dev_id = 1;
+ }
+ p->show_dma_caps();
return 0;
-out_free:
+exit_dma_irq_fail:
+ dev_err(&pdev->dev, "unable to request IRQ %d"
+ "for DMA (error %d)\n", dma_irq, ret);
+ for (irq_rel = 0; irq_rel < ch; irq_rel++) {
+ dma_irq = platform_get_irq(pdev, irq_rel);
+ free_irq(dma_irq, (void *)(irq_rel + 1));
+ }
+
+exit_dma_lch_fail:
+ kfree(p);
+ kfree(d);
kfree(dma_chan);
+ return ret;
+}
-out_unmap:
- iounmap(omap_dma_base);
+static int __devexit omap_system_dma_remove(struct platform_device *pdev)
+{
+ int dma_irq;
- return r;
+ if (cpu_class_is_omap2()) {
+ char irq_name[4];
+ strcpy(irq_name, "0");
+ dma_irq = platform_get_irq_byname(pdev, irq_name);
+ remove_irq(dma_irq, &omap24xx_dma_irq);
+ } else {
+ int irq_rel = 0;
+ for ( ; irq_rel < dma_chan_count; irq_rel++) {
+ dma_irq = platform_get_irq(pdev, irq_rel);
+ free_irq(dma_irq, (void *)(irq_rel + 1));
+ }
+ }
+ kfree(p);
+ kfree(d);
+ kfree(dma_chan);
+ return 0;
+}
+
+static struct platform_driver omap_system_dma_driver = {
+ .probe = omap_system_dma_probe,
+ .remove = omap_system_dma_remove,
+ .driver = {
+ .name = "omap_dma_system"
+ },
+};
+
+static int __init omap_system_dma_init(void)
+{
+ return platform_driver_register(&omap_system_dma_driver);
+}
+arch_initcall(omap_system_dma_init);
+
+static void __exit omap_system_dma_exit(void)
+{
+ platform_driver_unregister(&omap_system_dma_driver);
}
-arch_initcall(omap_init_dma);
+MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc");
/*
* Reserve the omap SDMA channels using cmdline bootarg
projects / GitHub / exynos8895 / android_kernel_samsung_universal8895.git / commitdiff