V4L/DVB (9442): Revert back previous change to 90MHz

Note:
* At High Symbol Rates we do not have enouph machine cycles to handle the
  incoming symbols and hence might run into problems at the very end of the
  specified definition
* Most of the equations have been calculated for a master clock of 99 MHz,
  running at 90MHz, raises lot of issues such as the need to recalculate
  all of them , which is eventually very painful.

Signed-off-by: Manu Abraham <manu@linuxtv.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

diff --git a/drivers/media/dvb/ttpci/budget-av.c b/drivers/media/dvb/ttpci/budget-av.c
index ed9b06b4b30edeee2f503d94aa6df609889613bd..f996cef79ec1ff0930060f338aa43135074eeb07 100644 (file)
--- a/drivers/media/dvb/ttpci/budget-av.c
+++ b/drivers/media/dvb/ttpci/budget-av.c
@@ -965,7 +965,7 @@ static const struct stb0899_s1_reg knc1_stb0899_s1_init_1[] = {
        { STB0899_GPIO37CFG             , 0x82 },
        { STB0899_GPIO38CFG             , 0x82 },
        { STB0899_GPIO39CFG             , 0x82 },
-       { STB0899_NCOARSE               , 0x13 }, /* 0x13 = 27 Mhz Clock, F/3 = 180MHz, F/6 = 90MHz */
+       { STB0899_NCOARSE               , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
        { STB0899_SYNTCTRL              , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
        { STB0899_FILTCTRL              , 0x00 },
        { STB0899_SYSCTRL               , 0x00 },

diff --git a/drivers/media/dvb/ttpci/budget-ci.c b/drivers/media/dvb/ttpci/budget-ci.c
index 2a1b79d67b6d8dd6db613a996e2500230e2b1dce..3507463fdac96670bc9f6a11fa32151e404d4a60 100644 (file)
--- a/drivers/media/dvb/ttpci/budget-ci.c
+++ b/drivers/media/dvb/ttpci/budget-ci.c
@@ -1154,7 +1154,7 @@ static const struct stb0899_s1_reg tt3200_stb0899_s1_init_1[] = {
        { STB0899_GPIO37CFG             , 0x82 },
        { STB0899_GPIO38CFG             , 0x82 },
        { STB0899_GPIO39CFG             , 0x82 },
-       { STB0899_NCOARSE               , 0x13 }, /* 0x13 = 27 Mhz Clock, F/3 = 180MHz, F/6 = 90MHz */
+       { STB0899_NCOARSE               , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
        { STB0899_SYNTCTRL              , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
        { STB0899_FILTCTRL              , 0x00 },
        { STB0899_SYSCTRL               , 0x00 },