drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info

Updated the i915_drpc_info debugfs with coarse power gating & forcewake
info for Gen9.

v2: Change all IS_GEN9() by gen >= 9 (Damien)

v3: Rebase

Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1467038401-8283-1-git-send-email-akash.goel@intel.com

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 531ca0221c7f6c60da442728df75c535e888e1b8..7c42ec4612ab9bc312ec018ba15b5325a2df6b78 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1602,6 +1602,7 @@ static int gen6_drpc_info(struct seq_file *m)
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
+       u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
        unsigned forcewake_count;
        int count = 0, ret;
 
@@ -1629,6 +1630,10 @@ static int gen6_drpc_info(struct seq_file *m)
 
        rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
        rcctl1 = I915_READ(GEN6_RC_CONTROL);
+       if (INTEL_INFO(dev)->gen >= 9) {
+               gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
+               gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
+       }
        mutex_unlock(&dev->struct_mutex);
        mutex_lock(&dev_priv->rps.hw_lock);
        sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
@@ -1647,6 +1652,12 @@ static int gen6_drpc_info(struct seq_file *m)
                   yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
        seq_printf(m, "RC6 Enabled: %s\n",
                   yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
+       if (INTEL_INFO(dev)->gen >= 9) {
+               seq_printf(m, "Render Well Gating Enabled: %s\n",
+                       yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
+               seq_printf(m, "Media Well Gating Enabled: %s\n",
+                       yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
+       }
        seq_printf(m, "Deep RC6 Enabled: %s\n",
                   yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
        seq_printf(m, "Deepest RC6 Enabled: %s\n",
@@ -1675,6 +1686,14 @@ static int gen6_drpc_info(struct seq_file *m)
 
        seq_printf(m, "Core Power Down: %s\n",
                   yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
+       if (INTEL_INFO(dev)->gen >= 9) {
+               seq_printf(m, "Render Power Well: %s\n",
+                       (gen9_powergate_status &
+                        GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
+               seq_printf(m, "Media Power Well: %s\n",
+                       (gen9_powergate_status &
+                        GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
+       }
 
        /* Not exactly sure what this is */
        seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
@@ -1692,7 +1711,7 @@ static int gen6_drpc_info(struct seq_file *m)
                   GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
        seq_printf(m, "RC6++ voltage: %dmV\n",
                   GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
-       return 0;
+       return i915_forcewake_domains(m, NULL);
 }
 
 static int i915_drpc_info(struct seq_file *m, void *unused)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c79a79547e5ccb0060fa500a902f7ecd19f7642..2f93d4a9cc270083652b42244e3168b4b660033e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6960,6 +6960,9 @@ enum {
 #define  ECOBUS                                        _MMIO(0xa180)
 #define    FORCEWAKE_MT_ENABLE                 (1<<5)
 #define  VLV_SPAREG2H                          _MMIO(0xA194)
+#define  GEN9_PWRGT_DOMAIN_STATUS              _MMIO(0xA2A0)
+#define   GEN9_PWRGT_MEDIA_STATUS_MASK         (1 << 0)
+#define   GEN9_PWRGT_RENDER_STATUS_MASK                (1 << 1)
 
 #define  GTFIFODBG                             _MMIO(0x120000)
 #define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV   (0x1f << 20)