MIPS: Sanitise coherentio semantics

The coherentio variable has previously been used as a boolean value,
indicating whether the user specified that coherent I/O should be
enabled or disabled. It failed to take into account the case where the
user does not specify any preference, in which case it makes sense that
we should default to coherent I/O if the hardware supports it
(hw_coherentio is non-zero).

Introduce an enum to clarify the 3 different values of coherentio & use
it throughout the code, modifying plat_device_is_coherent() &
r4k_cache_init() to take into account the default case.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Paul Burton <paul.burton@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/14347/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 2902138b3e0f56f639896c571e5bc87172f74d2f..7faaa6d593a74c119cfe6523e4c3e29009b8116a 100644 (file)
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -48,17 +48,17 @@ void __init plat_mem_setup(void)
                clear_c0_config(1 << 19); /* Clear Config[OD] */
 
        hw_coherentio = 0;
-       coherentio = 1;
+       coherentio = IO_COHERENCE_ENABLED;
        switch (alchemy_get_cputype()) {
        case ALCHEMY_CPU_AU1000:
        case ALCHEMY_CPU_AU1500:
        case ALCHEMY_CPU_AU1100:
-               coherentio = 0;
+               coherentio = IO_COHERENCE_DISABLED;
                break;
        case ALCHEMY_CPU_AU1200:
                /* Au1200 AB USB does not support coherent memory */
                if (0 == (read_c0_prid() & PRID_REV_MASK))
-                       coherentio = 0;
+                       coherentio = IO_COHERENCE_DISABLED;
                break;
        }
 

diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h
index bc5e85d579e607a61420a7c0cd7a1c6b716d8f4c..4fbce79fb57faba49a3d96eeb9eef3d5e0f7a7e5 100644 (file)
--- a/arch/mips/include/asm/dma-coherence.h
+++ b/arch/mips/include/asm/dma-coherence.h
@@ -9,14 +9,20 @@
 #ifndef __ASM_DMA_COHERENCE_H
 #define __ASM_DMA_COHERENCE_H
 
+enum coherent_io_user_state {
+       IO_COHERENCE_DEFAULT,
+       IO_COHERENCE_ENABLED,
+       IO_COHERENCE_DISABLED,
+};
+
 #ifdef CONFIG_DMA_MAYBE_COHERENT
-extern int coherentio;
+extern enum coherent_io_user_state coherentio;
 extern int hw_coherentio;
 #else
 #ifdef CONFIG_DMA_COHERENT
-#define coherentio     1
+#define coherentio     IO_COHERENCE_ENABLED
 #else
-#define coherentio     0
+#define coherentio     IO_COHERENCE_DISABLED
 #endif
 #define hw_coherentio  0
 #endif /* CONFIG_DMA_MAYBE_COHERENT */

diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 0f8a354fd4686dc49cbd6718ef565e9b73786386..8484f82fc7941f9cee73050726eb316c3f90a7b6 100644 (file)
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -49,7 +49,15 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
 
 static inline int plat_device_is_coherent(struct device *dev)
 {
-       return coherentio;
+       switch (coherentio) {
+       default:
+       case IO_COHERENCE_DEFAULT:
+               return hw_coherentio;
+       case IO_COHERENCE_ENABLED:
+               return 1;
+       case IO_COHERENCE_DISABLED:
+               return 0;
+       }
 }
 
 #ifndef plat_post_dma_flush

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 1fc11184e999e5c00390d87501d1e0b5fa810954..78ac033a0f074e56ee367ace412c153573e13607 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1935,7 +1935,8 @@ void r4k_cache_init(void)
        __local_flush_icache_user_range = local_r4k_flush_icache_user_range;
 
 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
-       if (coherentio) {
+       if ((coherentio == IO_COHERENCE_ENABLED) ||
+           ((coherentio == IO_COHERENCE_DEFAULT) && hw_coherentio)) {
                _dma_cache_wback_inv    = (void *)cache_noop;
                _dma_cache_wback        = (void *)cache_noop;
                _dma_cache_inv          = (void *)cache_noop;

diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 755259c54976be17c1e42611fc74b90dd3ebb839..8b86c616823922d7ade6eaa3c63094f6c2bdbc91 100644 (file)
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -25,13 +25,14 @@
 #include <dma-coherence.h>
 
 #ifdef CONFIG_DMA_MAYBE_COHERENT
-int coherentio = 0;    /* User defined DMA coherency from command line. */
+/* User defined DMA coherency from command line. */
+enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT;
 EXPORT_SYMBOL_GPL(coherentio);
 int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */
 
 static int __init setcoherentio(char *str)
 {
-       coherentio = 1;
+       coherentio = IO_COHERENCE_ENABLED;
        pr_info("Hardware DMA cache coherency (command line)\n");
        return 0;
 }
@@ -39,7 +40,7 @@ early_param("coherentio", setcoherentio);
 
 static int __init setnocoherentio(char *str)
 {
-       coherentio = 0;
+       coherentio = IO_COHERENCE_DISABLED;
        pr_info("Software DMA cache coherency (command line)\n");
        return 0;
 }

diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index 7e7364b0501edc33f1746962dc9b3796000d3c69..f1b6074828b125cc0d4b3f32c7f4a5c1e848f96c 100644 (file)
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -154,12 +154,12 @@ static void __init plat_setup_iocoherency(void)
         * coherency instead.
         */
        if (plat_enable_iocoherency()) {
-               if (coherentio == 0)
+               if (coherentio == IO_COHERENCE_DISABLED)
                        pr_info("Hardware DMA cache coherency disabled\n");
                else
                        pr_info("Hardware DMA cache coherency enabled\n");
        } else {
-               if (coherentio == 1)
+               if (coherentio == IO_COHERENCE_ENABLED)
                        pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
                else
                        pr_info("Software DMA cache coherency enabled\n");

diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index c8994c156e2ddad2c0bde912c553f66015c8d757..e99ca7702d8ad81660ab011ae4c990c0fb954f96 100644 (file)
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -429,7 +429,8 @@ static int alchemy_pci_probe(struct platform_device *pdev)
 
        /* Au1500 revisions older than AD have borked coherent PCI */
        if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) &&
-           (read_c0_prid() < 0x01030202) && !coherentio) {
+           (read_c0_prid() < 0x01030202) &&
+           (coherentio == IO_COHERENCE_DISABLED)) {
                val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
                val |= PCI_CONFIG_NC;
                __raw_writel(val, ctx->regs + PCI_REG_CONFIG);