MIPS: Fix protected_cache(e)_op() for microMIPS

When building for microMIPS we need to ensure that the assembler always
knows that there is code at the target of a branch or jump. Commit
7170bdc77755 ("MIPS: Add return errors to protected cache ops")
introduced a fixup path to protected_cache(e)_op() which does not meet
this requirement. The fixup path jumps to the "2" label but the .section
pseudo-op immediately following it causes the label to be marked as
data. Linking then fails with:

  mips-img-linux-gnu-ld: arch/mips/mm/c-r4k.o: .fixup+0x0: Unsupported
  jump between ISA modes; consider recompiling with interlinking
  enabled.

Fix this by declaring that "2" labels code using the .insn directive.

Fixes: 7170bdc77755 ("MIPS: Add return errors to protected cache ops")
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Maciej W. Rozycki <macro@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Ralf Baechle <ralf@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/15274/
Signed-off-by: James Hogan <james.hogan@imgtec.com>

diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 7227c158cbf809697ea9d3cd95907421b0d3fe19..55fd94e6cd0b1f2c79294f59bf4bc3b0bc702c66 100644 (file)
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -154,7 +154,8 @@ static inline void flush_scache_line(unsigned long addr)
        "       .set    noreorder               \n"             \
        "       .set "MIPS_ISA_ARCH_LEVEL"      \n"             \
        "1:     cache   %1, (%2)                \n"             \
-       "2:     .set    pop                     \n"             \
+       "2:     .insn                           \n"             \
+       "       .set    pop                     \n"             \
        "       .section .fixup,\"ax\"          \n"             \
        "3:     li      %0, %3                  \n"             \
        "       j       2b                      \n"             \
@@ -177,7 +178,8 @@ static inline void flush_scache_line(unsigned long addr)
        "       .set    mips0                   \n"             \
        "       .set    eva                     \n"             \
        "1:     cachee  %1, (%2)                \n"             \
-       "2:     .set    pop                     \n"             \
+       "2:     .insn                           \n"             \
+       "       .set    pop                     \n"             \
        "       .section .fixup,\"ax\"          \n"             \
        "3:     li      %0, %3                  \n"             \
        "       j       2b                      \n"             \