via-*: Move the VIA drivers
authorJeff Kirsher <jeffrey.t.kirsher@intel.com>
Sat, 21 May 2011 03:43:09 +0000 (20:43 -0700)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Fri, 12 Aug 2011 07:21:56 +0000 (00:21 -0700)
Move the VIA drivers into drivers/net/ethernet/via/ and make the
necessary Kconfig and Makefile changes.

CC: Roger Luethi <rl@hellgate.ch>
CC: Francois Romieu <romieu@fr.zoreil.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
13 files changed:
MAINTAINERS
drivers/net/Kconfig
drivers/net/Makefile
drivers/net/ethernet/Kconfig
drivers/net/ethernet/Makefile
drivers/net/ethernet/via/Kconfig [new file with mode: 0644]
drivers/net/ethernet/via/Makefile [new file with mode: 0644]
drivers/net/ethernet/via/via-rhine.c [new file with mode: 0644]
drivers/net/ethernet/via/via-velocity.c [new file with mode: 0644]
drivers/net/ethernet/via/via-velocity.h [new file with mode: 0644]
drivers/net/via-rhine.c [deleted file]
drivers/net/via-velocity.c [deleted file]
drivers/net/via-velocity.h [deleted file]

index b9acfdee10e873c43b04dc4a766ff33c30336941..51d9281a30355f58a78bedcb133cf900b2cce448 100644 (file)
@@ -6988,7 +6988,7 @@ F:        include/linux/vhost.h
 VIA RHINE NETWORK DRIVER
 M:     Roger Luethi <rl@hellgate.ch>
 S:     Maintained
-F:     drivers/net/via-rhine.c
+F:     drivers/net/ethernet/via/via-rhine.c
 
 VIAPRO SMBUS DRIVER
 M:     Jean Delvare <khali@linux-fr.org>
@@ -7016,7 +7016,7 @@ VIA VELOCITY NETWORK DRIVER
 M:     Francois Romieu <romieu@fr.zoreil.com>
 L:     netdev@vger.kernel.org
 S:     Maintained
-F:     drivers/net/via-velocity.*
+F:     drivers/net/ethernet/via/via-velocity.*
 
 VLAN (802.1Q)
 M:     Patrick McHardy <kaber@trash.net>
index cb6c6947b3200ad6e79093a0bfc23aba52042c3d..c1e491add8f998940fbf6dc175f55209a4cf5c63 100644 (file)
@@ -614,30 +614,6 @@ config KS8851_MLL
          This platform driver is for Micrel KS8851 Address/data bus
          multiplexed network chip.
 
-config VIA_RHINE
-       tristate "VIA Rhine support"
-       depends on NET_PCI && PCI
-       select CRC32
-       select MII
-       help
-         If you have a VIA "Rhine" based network card (Rhine-I (VT86C100A),
-         Rhine-II (VT6102), or Rhine-III (VT6105)), say Y here. Rhine-type
-         Ethernet functions can also be found integrated on South Bridges
-         (e.g. VT8235).
-
-         To compile this driver as a module, choose M here. The module
-         will be called via-rhine.
-
-config VIA_RHINE_MMIO
-       bool "Use MMIO instead of PIO"
-       depends on VIA_RHINE
-       help
-         This instructs the driver to use PCI shared memory (MMIO) instead of
-         programmed I/O ports (PIO). Enabling this gives an improvement in
-         processing time in parts of the driver.
-
-         If unsure, say Y.
-
 config CPMAC
        tristate "TI AR7 CPMAC Ethernet support (EXPERIMENTAL)"
        depends on NET_ETHERNET && EXPERIMENTAL && AR7
@@ -793,18 +769,6 @@ config SIS190
          To compile this driver as a module, choose M here: the module
          will be called sis190.  This is recommended.
 
-config VIA_VELOCITY
-       tristate "VIA Velocity support"
-       depends on PCI
-       select CRC32
-       select CRC_CCITT
-       select MII
-       help
-         If you have a VIA "Velocity" based network card say Y here.
-
-         To compile this driver as a module, choose M here. The module
-         will be called via-velocity.
-
 config SPIDER_NET
        tristate "Spider Gigabit Ethernet driver"
        depends on PCI && (PPC_IBM_CELL_BLADE || PPC_CELLEB)
index 69ca6a009c59b7beab146d6a7743d8613aa47e31..7e1128fd62bdcd8ebf304a583e9aae9addfc9d73 100644 (file)
@@ -51,8 +51,6 @@ obj-$(CONFIG_KS8842)  += ks8842.o
 obj-$(CONFIG_KS8851)   += ks8851.o
 obj-$(CONFIG_KS8851_MLL)       += ks8851_mll.o
 obj-$(CONFIG_KSZ884X_PCI)      += ksz884x.o
-obj-$(CONFIG_VIA_RHINE) += via-rhine.o
-obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o
 obj-$(CONFIG_ADAPTEC_STARFIRE) += starfire.o
 obj-$(CONFIG_RIONET) += rionet.o
 obj-$(CONFIG_SH_ETH) += sh_eth.o
index 1c447d96d7e5dd6c00a4cffd8fa1ad30a77d1148..bdc0df873daf636761f281d6c7fdf6886a93d286 100644 (file)
@@ -45,5 +45,6 @@ source "drivers/net/ethernet/smsc/Kconfig"
 source "drivers/net/ethernet/stmicro/Kconfig"
 source "drivers/net/ethernet/sun/Kconfig"
 source "drivers/net/ethernet/tehuti/Kconfig"
+source "drivers/net/ethernet/via/Kconfig"
 
 endif # ETHERNET
index 48c8656b96c28bb0343b3d82aeaee0ec1fb22d0f..ac60ac9026bb895d7037726a809b7c319b5d4e34 100644 (file)
@@ -36,3 +36,4 @@ obj-$(CONFIG_NET_VENDOR_SMSC) += smsc/
 obj-$(CONFIG_NET_VENDOR_STMICRO) += stmicro/
 obj-$(CONFIG_NET_VENDOR_SUN) += sun/
 obj-$(CONFIG_NET_VENDOR_TEHUTI) += tehuti/
+obj-$(CONFIG_NET_VENDOR_VIA) += via/
diff --git a/drivers/net/ethernet/via/Kconfig b/drivers/net/ethernet/via/Kconfig
new file mode 100644 (file)
index 0000000..7199194
--- /dev/null
@@ -0,0 +1,56 @@
+#
+# VIA device configuration
+#
+
+config NET_VENDOR_VIA
+       bool "VIA devices"
+       depends on PCI
+       ---help---
+         If you have a network (Ethernet) card belonging to this class, say Y
+         and read the Ethernet-HOWTO, available from
+         <http://www.tldp.org/docs.html#howto>.
+
+         Note that the answer to this question doesn't directly affect the
+         kernel: saying N will just cause the configurator to skip all
+         the questions about VIA devices. If you say Y, you will be asked for
+         your specific card in the following questions.
+
+if NET_VENDOR_VIA
+
+config VIA_RHINE
+       tristate "VIA Rhine support"
+       depends on PCI
+       select CRC32
+       select MII
+       ---help---
+         If you have a VIA "Rhine" based network card (Rhine-I (VT86C100A),
+         Rhine-II (VT6102), or Rhine-III (VT6105)), say Y here. Rhine-type
+         Ethernet functions can also be found integrated on South Bridges
+         (e.g. VT8235).
+
+         To compile this driver as a module, choose M here. The module
+         will be called via-rhine.
+
+config VIA_RHINE_MMIO
+       bool "Use MMIO instead of PIO"
+       depends on VIA_RHINE
+       ---help---
+         This instructs the driver to use PCI shared memory (MMIO) instead of
+         programmed I/O ports (PIO). Enabling this gives an improvement in
+         processing time in parts of the driver.
+
+         If unsure, say Y.
+
+config VIA_VELOCITY
+       tristate "VIA Velocity support"
+       depends on PCI
+       select CRC32
+       select CRC_CCITT
+       select MII
+       ---help---
+         If you have a VIA "Velocity" based network card say Y here.
+
+         To compile this driver as a module, choose M here. The module
+         will be called via-velocity.
+
+endif # NET_VENDOR_VIA
diff --git a/drivers/net/ethernet/via/Makefile b/drivers/net/ethernet/via/Makefile
new file mode 100644 (file)
index 0000000..46c5d4a
--- /dev/null
@@ -0,0 +1,6 @@
+#
+# Makefile for the VIA device drivers.
+#
+
+obj-$(CONFIG_VIA_RHINE) += via-rhine.o
+obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o
diff --git a/drivers/net/ethernet/via/via-rhine.c b/drivers/net/ethernet/via/via-rhine.c
new file mode 100644 (file)
index 0000000..7f23ab9
--- /dev/null
@@ -0,0 +1,2340 @@
+/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
+/*
+       Written 1998-2001 by Donald Becker.
+
+       Current Maintainer: Roger Luethi <rl@hellgate.ch>
+
+       This software may be used and distributed according to the terms of
+       the GNU General Public License (GPL), incorporated herein by reference.
+       Drivers based on or derived from this code fall under the GPL and must
+       retain the authorship, copyright and license notice.  This file is not
+       a complete program and may only be used when the entire operating
+       system is licensed under the GPL.
+
+       This driver is designed for the VIA VT86C100A Rhine-I.
+       It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
+       and management NIC 6105M).
+
+       The author may be reached as becker@scyld.com, or C/O
+       Scyld Computing Corporation
+       410 Severn Ave., Suite 210
+       Annapolis MD 21403
+
+
+       This driver contains some changes from the original Donald Becker
+       version. He may or may not be interested in bug reports on this
+       code. You can find his versions at:
+       http://www.scyld.com/network/via-rhine.html
+       [link no longer provides useful info -jgarzik]
+
+*/
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#define DRV_NAME       "via-rhine"
+#define DRV_VERSION    "1.5.0"
+#define DRV_RELDATE    "2010-10-09"
+
+
+/* A few user-configurable values.
+   These may be modified when a driver module is loaded. */
+
+#define DEBUG
+static int debug = 1;  /* 1 normal messages, 0 quiet .. 7 verbose. */
+static int max_interrupt_work = 20;
+
+/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
+   Setting to > 1518 effectively disables this feature. */
+#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
+       defined(CONFIG_SPARC) || defined(__ia64__) ||              \
+       defined(__sh__) || defined(__mips__)
+static int rx_copybreak = 1518;
+#else
+static int rx_copybreak;
+#endif
+
+/* Work-around for broken BIOSes: they are unable to get the chip back out of
+   power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
+static int avoid_D3;
+
+/*
+ * In case you are looking for 'options[]' or 'full_duplex[]', they
+ * are gone. Use ethtool(8) instead.
+ */
+
+/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
+   The Rhine has a 64 element 8390-like hash table. */
+static const int multicast_filter_limit = 32;
+
+
+/* Operational parameters that are set at compile time. */
+
+/* Keep the ring sizes a power of two for compile efficiency.
+   The compiler will convert <unsigned>'%'<2^N> into a bit mask.
+   Making the Tx ring too large decreases the effectiveness of channel
+   bonding and packet priority.
+   There are no ill effects from too-large receive rings. */
+#define TX_RING_SIZE   16
+#define TX_QUEUE_LEN   10      /* Limit ring entries actually used. */
+#define RX_RING_SIZE   64
+
+/* Operational parameters that usually are not changed. */
+
+/* Time in jiffies before concluding the transmitter is hung. */
+#define TX_TIMEOUT     (2*HZ)
+
+#define PKT_BUF_SZ     1536    /* Size of each temporary Rx buffer.*/
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/dma-mapping.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/crc32.h>
+#include <linux/if_vlan.h>
+#include <linux/bitops.h>
+#include <linux/workqueue.h>
+#include <asm/processor.h>     /* Processor type for cache alignment. */
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <linux/dmi.h>
+
+/* These identify the driver base version and may not be removed. */
+static const char version[] __devinitconst =
+       "v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker";
+
+/* This driver was written to use PCI memory space. Some early versions
+   of the Rhine may only work correctly with I/O space accesses. */
+#ifdef CONFIG_VIA_RHINE_MMIO
+#define USE_MMIO
+#else
+#endif
+
+MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
+MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
+MODULE_LICENSE("GPL");
+
+module_param(max_interrupt_work, int, 0);
+module_param(debug, int, 0);
+module_param(rx_copybreak, int, 0);
+module_param(avoid_D3, bool, 0);
+MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
+MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
+MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
+MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
+
+#define MCAM_SIZE      32
+#define VCAM_SIZE      32
+
+/*
+               Theory of Operation
+
+I. Board Compatibility
+
+This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
+controller.
+
+II. Board-specific settings
+
+Boards with this chip are functional only in a bus-master PCI slot.
+
+Many operational settings are loaded from the EEPROM to the Config word at
+offset 0x78. For most of these settings, this driver assumes that they are
+correct.
+If this driver is compiled to use PCI memory space operations the EEPROM
+must be configured to enable memory ops.
+
+III. Driver operation
+
+IIIa. Ring buffers
+
+This driver uses two statically allocated fixed-size descriptor lists
+formed into rings by a branch from the final descriptor to the beginning of
+the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
+
+IIIb/c. Transmit/Receive Structure
+
+This driver attempts to use a zero-copy receive and transmit scheme.
+
+Alas, all data buffers are required to start on a 32 bit boundary, so
+the driver must often copy transmit packets into bounce buffers.
+
+The driver allocates full frame size skbuffs for the Rx ring buffers at
+open() time and passes the skb->data field to the chip as receive data
+buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
+a fresh skbuff is allocated and the frame is copied to the new skbuff.
+When the incoming frame is larger, the skbuff is passed directly up the
+protocol stack. Buffers consumed this way are replaced by newly allocated
+skbuffs in the last phase of rhine_rx().
+
+The RX_COPYBREAK value is chosen to trade-off the memory wasted by
+using a full-sized skbuff for small frames vs. the copying costs of larger
+frames. New boards are typically used in generously configured machines
+and the underfilled buffers have negligible impact compared to the benefit of
+a single allocation size, so the default value of zero results in never
+copying packets. When copying is done, the cost is usually mitigated by using
+a combined copy/checksum routine. Copying also preloads the cache, which is
+most useful with small frames.
+
+Since the VIA chips are only able to transfer data to buffers on 32 bit
+boundaries, the IP header at offset 14 in an ethernet frame isn't
+longword aligned for further processing. Copying these unaligned buffers
+has the beneficial effect of 16-byte aligning the IP header.
+
+IIId. Synchronization
+
+The driver runs as two independent, single-threaded flows of control. One
+is the send-packet routine, which enforces single-threaded use by the
+netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,
+which is single threaded by the hardware and interrupt handling software.
+
+The send packet thread has partial control over the Tx ring. It locks the
+netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in
+the ring is not available it stops the transmit queue by
+calling netif_stop_queue.
+
+The interrupt handler has exclusive control over the Rx ring and records stats
+from the Tx ring. After reaping the stats, it marks the Tx queue entry as
+empty by incrementing the dirty_tx mark. If at least half of the entries in
+the Rx ring are available the transmit queue is woken up if it was stopped.
+
+IV. Notes
+
+IVb. References
+
+Preliminary VT86C100A manual from http://www.via.com.tw/
+http://www.scyld.com/expert/100mbps.html
+http://www.scyld.com/expert/NWay.html
+ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
+ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
+
+
+IVc. Errata
+
+The VT86C100A manual is not reliable information.
+The 3043 chip does not handle unaligned transmit or receive buffers, resulting
+in significant performance degradation for bounce buffer copies on transmit
+and unaligned IP headers on receive.
+The chip does not pad to minimum transmit length.
+
+*/
+
+
+/* This table drives the PCI probe routines. It's mostly boilerplate in all
+   of the drivers, and will likely be provided by some future kernel.
+   Note the matching code -- the first table entry matchs all 56** cards but
+   second only the 1234 card.
+*/
+
+enum rhine_revs {
+       VT86C100A       = 0x00,
+       VTunknown0      = 0x20,
+       VT6102          = 0x40,
+       VT8231          = 0x50, /* Integrated MAC */
+       VT8233          = 0x60, /* Integrated MAC */
+       VT8235          = 0x74, /* Integrated MAC */
+       VT8237          = 0x78, /* Integrated MAC */
+       VTunknown1      = 0x7C,
+       VT6105          = 0x80,
+       VT6105_B0       = 0x83,
+       VT6105L         = 0x8A,
+       VT6107          = 0x8C,
+       VTunknown2      = 0x8E,
+       VT6105M         = 0x90, /* Management adapter */
+};
+
+enum rhine_quirks {
+       rqWOL           = 0x0001,       /* Wake-On-LAN support */
+       rqForceReset    = 0x0002,
+       rq6patterns     = 0x0040,       /* 6 instead of 4 patterns for WOL */
+       rqStatusWBRace  = 0x0080,       /* Tx Status Writeback Error possible */
+       rqRhineI        = 0x0100,       /* See comment below */
+};
+/*
+ * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
+ * MMIO as well as for the collision counter and the Tx FIFO underflow
+ * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
+ */
+
+/* Beware of PCI posted writes */
+#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
+
+static DEFINE_PCI_DEVICE_TABLE(rhine_pci_tbl) = {
+       { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, },    /* VT86C100A */
+       { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, },    /* VT6102 */
+       { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, },    /* 6105{,L,LOM} */
+       { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, },    /* VT6105M */
+       { }     /* terminate list */
+};
+MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
+
+
+/* Offsets to the device registers. */
+enum register_offsets {
+       StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
+       ChipCmd1=0x09, TQWake=0x0A,
+       IntrStatus=0x0C, IntrEnable=0x0E,
+       MulticastFilter0=0x10, MulticastFilter1=0x14,
+       RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
+       MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F,
+       MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
+       ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
+       RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
+       StickyHW=0x83, IntrStatus2=0x84,
+       CamMask=0x88, CamCon=0x92, CamAddr=0x93,
+       WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
+       WOLcrClr1=0xA6, WOLcgClr=0xA7,
+       PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
+};
+
+/* Bits in ConfigD */
+enum backoff_bits {
+       BackOptional=0x01, BackModify=0x02,
+       BackCaptureEffect=0x04, BackRandom=0x08
+};
+
+/* Bits in the TxConfig (TCR) register */
+enum tcr_bits {
+       TCR_PQEN=0x01,
+       TCR_LB0=0x02,           /* loopback[0] */
+       TCR_LB1=0x04,           /* loopback[1] */
+       TCR_OFSET=0x08,
+       TCR_RTGOPT=0x10,
+       TCR_RTFT0=0x20,
+       TCR_RTFT1=0x40,
+       TCR_RTSF=0x80,
+};
+
+/* Bits in the CamCon (CAMC) register */
+enum camcon_bits {
+       CAMC_CAMEN=0x01,
+       CAMC_VCAMSL=0x02,
+       CAMC_CAMWR=0x04,
+       CAMC_CAMRD=0x08,
+};
+
+/* Bits in the PCIBusConfig1 (BCR1) register */
+enum bcr1_bits {
+       BCR1_POT0=0x01,
+       BCR1_POT1=0x02,
+       BCR1_POT2=0x04,
+       BCR1_CTFT0=0x08,
+       BCR1_CTFT1=0x10,
+       BCR1_CTSF=0x20,
+       BCR1_TXQNOBK=0x40,      /* for VT6105 */
+       BCR1_VIDFR=0x80,        /* for VT6105 */
+       BCR1_MED0=0x40,         /* for VT6102 */
+       BCR1_MED1=0x80,         /* for VT6102 */
+};
+
+#ifdef USE_MMIO
+/* Registers we check that mmio and reg are the same. */
+static const int mmio_verify_registers[] = {
+       RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
+       0
+};
+#endif
+
+/* Bits in the interrupt status/mask registers. */
+enum intr_status_bits {
+       IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
+       IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
+       IntrPCIErr=0x0040,
+       IntrStatsMax=0x0080, IntrRxEarly=0x0100,
+       IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
+       IntrTxAborted=0x2000, IntrLinkChange=0x4000,
+       IntrRxWakeUp=0x8000,
+       IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
+       IntrTxDescRace=0x080000,        /* mapped from IntrStatus2 */
+       IntrTxErrSummary=0x082218,
+};
+
+/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
+enum wol_bits {
+       WOLucast        = 0x10,
+       WOLmagic        = 0x20,
+       WOLbmcast       = 0x30,
+       WOLlnkon        = 0x40,
+       WOLlnkoff       = 0x80,
+};
+
+/* The Rx and Tx buffer descriptors. */
+struct rx_desc {
+       __le32 rx_status;
+       __le32 desc_length; /* Chain flag, Buffer/frame length */
+       __le32 addr;
+       __le32 next_desc;
+};
+struct tx_desc {
+       __le32 tx_status;
+       __le32 desc_length; /* Chain flag, Tx Config, Frame length */
+       __le32 addr;
+       __le32 next_desc;
+};
+
+/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
+#define TXDESC         0x00e08000
+
+enum rx_status_bits {
+       RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
+};
+
+/* Bits in *_desc.*_status */
+enum desc_status_bits {
+       DescOwn=0x80000000
+};
+
+/* Bits in *_desc.*_length */
+enum desc_length_bits {
+       DescTag=0x00010000
+};
+
+/* Bits in ChipCmd. */
+enum chip_cmd_bits {
+       CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
+       CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
+       Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
+       Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
+};
+
+struct rhine_private {
+       /* Bit mask for configured VLAN ids */
+       unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
+
+       /* Descriptor rings */
+       struct rx_desc *rx_ring;
+       struct tx_desc *tx_ring;
+       dma_addr_t rx_ring_dma;
+       dma_addr_t tx_ring_dma;
+
+       /* The addresses of receive-in-place skbuffs. */
+       struct sk_buff *rx_skbuff[RX_RING_SIZE];
+       dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
+
+       /* The saved address of a sent-in-place packet/buffer, for later free(). */
+       struct sk_buff *tx_skbuff[TX_RING_SIZE];
+       dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
+
+       /* Tx bounce buffers (Rhine-I only) */
+       unsigned char *tx_buf[TX_RING_SIZE];
+       unsigned char *tx_bufs;
+       dma_addr_t tx_bufs_dma;
+
+       struct pci_dev *pdev;
+       long pioaddr;
+       struct net_device *dev;
+       struct napi_struct napi;
+       spinlock_t lock;
+       struct work_struct reset_task;
+
+       /* Frequently used values: keep some adjacent for cache effect. */
+       u32 quirks;
+       struct rx_desc *rx_head_desc;
+       unsigned int cur_rx, dirty_rx;  /* Producer/consumer ring indices */
+       unsigned int cur_tx, dirty_tx;
+       unsigned int rx_buf_sz;         /* Based on MTU+slack. */
+       u8 wolopts;
+
+       u8 tx_thresh, rx_thresh;
+
+       struct mii_if_info mii_if;
+       void __iomem *base;
+};
+
+#define BYTE_REG_BITS_ON(x, p)      do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
+#define WORD_REG_BITS_ON(x, p)      do { iowrite16((ioread16((p))|(x)), (p)); } while (0)
+#define DWORD_REG_BITS_ON(x, p)     do { iowrite32((ioread32((p))|(x)), (p)); } while (0)
+
+#define BYTE_REG_BITS_IS_ON(x, p)   (ioread8((p)) & (x))
+#define WORD_REG_BITS_IS_ON(x, p)   (ioread16((p)) & (x))
+#define DWORD_REG_BITS_IS_ON(x, p)  (ioread32((p)) & (x))
+
+#define BYTE_REG_BITS_OFF(x, p)     do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
+#define WORD_REG_BITS_OFF(x, p)     do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)
+#define DWORD_REG_BITS_OFF(x, p)    do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)
+
+#define BYTE_REG_BITS_SET(x, m, p)   do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
+#define WORD_REG_BITS_SET(x, m, p)   do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0)
+#define DWORD_REG_BITS_SET(x, m, p)  do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0)
+
+
+static int  mdio_read(struct net_device *dev, int phy_id, int location);
+static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
+static int  rhine_open(struct net_device *dev);
+static void rhine_reset_task(struct work_struct *work);
+static void rhine_tx_timeout(struct net_device *dev);
+static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
+                                 struct net_device *dev);
+static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
+static void rhine_tx(struct net_device *dev);
+static int rhine_rx(struct net_device *dev, int limit);
+static void rhine_error(struct net_device *dev, int intr_status);
+static void rhine_set_rx_mode(struct net_device *dev);
+static struct net_device_stats *rhine_get_stats(struct net_device *dev);
+static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
+static const struct ethtool_ops netdev_ethtool_ops;
+static int  rhine_close(struct net_device *dev);
+static void rhine_shutdown (struct pci_dev *pdev);
+static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid);
+static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid);
+static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr);
+static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr);
+static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask);
+static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask);
+static void rhine_init_cam_filter(struct net_device *dev);
+static void rhine_update_vcam(struct net_device *dev);
+
+#define RHINE_WAIT_FOR(condition)                              \
+do {                                                           \
+       int i = 1024;                                           \
+       while (!(condition) && --i)                             \
+               ;                                               \
+       if (debug > 1 && i < 512)                               \
+               pr_info("%4d cycles used @ %s:%d\n",            \
+                       1024 - i, __func__, __LINE__);          \
+} while (0)
+
+static inline u32 get_intr_status(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+       u32 intr_status;
+
+       intr_status = ioread16(ioaddr + IntrStatus);
+       /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
+       if (rp->quirks & rqStatusWBRace)
+               intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
+       return intr_status;
+}
+
+/*
+ * Get power related registers into sane state.
+ * Notify user about past WOL event.
+ */
+static void rhine_power_init(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+       u16 wolstat;
+
+       if (rp->quirks & rqWOL) {
+               /* Make sure chip is in power state D0 */
+               iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
+
+               /* Disable "force PME-enable" */
+               iowrite8(0x80, ioaddr + WOLcgClr);
+
+               /* Clear power-event config bits (WOL) */
+               iowrite8(0xFF, ioaddr + WOLcrClr);
+               /* More recent cards can manage two additional patterns */
+               if (rp->quirks & rq6patterns)
+                       iowrite8(0x03, ioaddr + WOLcrClr1);
+
+               /* Save power-event status bits */
+               wolstat = ioread8(ioaddr + PwrcsrSet);
+               if (rp->quirks & rq6patterns)
+                       wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
+
+               /* Clear power-event status bits */
+               iowrite8(0xFF, ioaddr + PwrcsrClr);
+               if (rp->quirks & rq6patterns)
+                       iowrite8(0x03, ioaddr + PwrcsrClr1);
+
+               if (wolstat) {
+                       char *reason;
+                       switch (wolstat) {
+                       case WOLmagic:
+                               reason = "Magic packet";
+                               break;
+                       case WOLlnkon:
+                               reason = "Link went up";
+                               break;
+                       case WOLlnkoff:
+                               reason = "Link went down";
+                               break;
+                       case WOLucast:
+                               reason = "Unicast packet";
+                               break;
+                       case WOLbmcast:
+                               reason = "Multicast/broadcast packet";
+                               break;
+                       default:
+                               reason = "Unknown";
+                       }
+                       netdev_info(dev, "Woke system up. Reason: %s\n",
+                                   reason);
+               }
+       }
+}
+
+static void rhine_chip_reset(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+
+       iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
+       IOSYNC;
+
+       if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
+               netdev_info(dev, "Reset not complete yet. Trying harder.\n");
+
+               /* Force reset */
+               if (rp->quirks & rqForceReset)
+                       iowrite8(0x40, ioaddr + MiscCmd);
+
+               /* Reset can take somewhat longer (rare) */
+               RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
+       }
+
+       if (debug > 1)
+               netdev_info(dev, "Reset %s\n",
+                           (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
+                           "failed" : "succeeded");
+}
+
+#ifdef USE_MMIO
+static void enable_mmio(long pioaddr, u32 quirks)
+{
+       int n;
+       if (quirks & rqRhineI) {
+               /* More recent docs say that this bit is reserved ... */
+               n = inb(pioaddr + ConfigA) | 0x20;
+               outb(n, pioaddr + ConfigA);
+       } else {
+               n = inb(pioaddr + ConfigD) | 0x80;
+               outb(n, pioaddr + ConfigD);
+       }
+}
+#endif
+
+/*
+ * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
+ * (plus 0x6C for Rhine-I/II)
+ */
+static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+
+       outb(0x20, pioaddr + MACRegEEcsr);
+       RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
+
+#ifdef USE_MMIO
+       /*
+        * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
+        * MMIO. If reloading EEPROM was done first this could be avoided, but
+        * it is not known if that still works with the "win98-reboot" problem.
+        */
+       enable_mmio(pioaddr, rp->quirks);
+#endif
+
+       /* Turn off EEPROM-controlled wake-up (magic packet) */
+       if (rp->quirks & rqWOL)
+               iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
+
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void rhine_poll(struct net_device *dev)
+{
+       disable_irq(dev->irq);
+       rhine_interrupt(dev->irq, (void *)dev);
+       enable_irq(dev->irq);
+}
+#endif
+
+static int rhine_napipoll(struct napi_struct *napi, int budget)
+{
+       struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
+       struct net_device *dev = rp->dev;
+       void __iomem *ioaddr = rp->base;
+       int work_done;
+
+       work_done = rhine_rx(dev, budget);
+
+       if (work_done < budget) {
+               napi_complete(napi);
+
+               iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
+                         IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
+                         IntrTxDone | IntrTxError | IntrTxUnderrun |
+                         IntrPCIErr | IntrStatsMax | IntrLinkChange,
+                         ioaddr + IntrEnable);
+       }
+       return work_done;
+}
+
+static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+
+       /* Reset the chip to erase previous misconfiguration. */
+       rhine_chip_reset(dev);
+
+       /* Rhine-I needs extra time to recuperate before EEPROM reload */
+       if (rp->quirks & rqRhineI)
+               msleep(5);
+
+       /* Reload EEPROM controlled bytes cleared by soft reset */
+       rhine_reload_eeprom(pioaddr, dev);
+}
+
+static const struct net_device_ops rhine_netdev_ops = {
+       .ndo_open                = rhine_open,
+       .ndo_stop                = rhine_close,
+       .ndo_start_xmit          = rhine_start_tx,
+       .ndo_get_stats           = rhine_get_stats,
+       .ndo_set_multicast_list  = rhine_set_rx_mode,
+       .ndo_change_mtu          = eth_change_mtu,
+       .ndo_validate_addr       = eth_validate_addr,
+       .ndo_set_mac_address     = eth_mac_addr,
+       .ndo_do_ioctl            = netdev_ioctl,
+       .ndo_tx_timeout          = rhine_tx_timeout,
+       .ndo_vlan_rx_add_vid     = rhine_vlan_rx_add_vid,
+       .ndo_vlan_rx_kill_vid    = rhine_vlan_rx_kill_vid,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+       .ndo_poll_controller     = rhine_poll,
+#endif
+};
+
+static int __devinit rhine_init_one(struct pci_dev *pdev,
+                                   const struct pci_device_id *ent)
+{
+       struct net_device *dev;
+       struct rhine_private *rp;
+       int i, rc;
+       u32 quirks;
+       long pioaddr;
+       long memaddr;
+       void __iomem *ioaddr;
+       int io_size, phy_id;
+       const char *name;
+#ifdef USE_MMIO
+       int bar = 1;
+#else
+       int bar = 0;
+#endif
+
+/* when built into the kernel, we only print version if device is found */
+#ifndef MODULE
+       pr_info_once("%s\n", version);
+#endif
+
+       io_size = 256;
+       phy_id = 0;
+       quirks = 0;
+       name = "Rhine";
+       if (pdev->revision < VTunknown0) {
+               quirks = rqRhineI;
+               io_size = 128;
+       }
+       else if (pdev->revision >= VT6102) {
+               quirks = rqWOL | rqForceReset;
+               if (pdev->revision < VT6105) {
+                       name = "Rhine II";
+                       quirks |= rqStatusWBRace;       /* Rhine-II exclusive */
+               }
+               else {
+                       phy_id = 1;     /* Integrated PHY, phy_id fixed to 1 */
+                       if (pdev->revision >= VT6105_B0)
+                               quirks |= rq6patterns;
+                       if (pdev->revision < VT6105M)
+                               name = "Rhine III";
+                       else
+                               name = "Rhine III (Management Adapter)";
+               }
+       }
+
+       rc = pci_enable_device(pdev);
+       if (rc)
+               goto err_out;
+
+       /* this should always be supported */
+       rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
+       if (rc) {
+               dev_err(&pdev->dev,
+                       "32-bit PCI DMA addresses not supported by the card!?\n");
+               goto err_out;
+       }
+
+       /* sanity check */
+       if ((pci_resource_len(pdev, 0) < io_size) ||
+           (pci_resource_len(pdev, 1) < io_size)) {
+               rc = -EIO;
+               dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
+               goto err_out;
+       }
+
+       pioaddr = pci_resource_start(pdev, 0);
+       memaddr = pci_resource_start(pdev, 1);
+
+       pci_set_master(pdev);
+
+       dev = alloc_etherdev(sizeof(struct rhine_private));
+       if (!dev) {
+               rc = -ENOMEM;
+               dev_err(&pdev->dev, "alloc_etherdev failed\n");
+               goto err_out;
+       }
+       SET_NETDEV_DEV(dev, &pdev->dev);
+
+       rp = netdev_priv(dev);
+       rp->dev = dev;
+       rp->quirks = quirks;
+       rp->pioaddr = pioaddr;
+       rp->pdev = pdev;
+
+       rc = pci_request_regions(pdev, DRV_NAME);
+       if (rc)
+               goto err_out_free_netdev;
+
+       ioaddr = pci_iomap(pdev, bar, io_size);
+       if (!ioaddr) {
+               rc = -EIO;
+               dev_err(&pdev->dev,
+                       "ioremap failed for device %s, region 0x%X @ 0x%lX\n",
+                       pci_name(pdev), io_size, memaddr);
+               goto err_out_free_res;
+       }
+
+#ifdef USE_MMIO
+       enable_mmio(pioaddr, quirks);
+
+       /* Check that selected MMIO registers match the PIO ones */
+       i = 0;
+       while (mmio_verify_registers[i]) {
+               int reg = mmio_verify_registers[i++];
+               unsigned char a = inb(pioaddr+reg);
+               unsigned char b = readb(ioaddr+reg);
+               if (a != b) {
+                       rc = -EIO;
+                       dev_err(&pdev->dev,
+                               "MMIO do not match PIO [%02x] (%02x != %02x)\n",
+                               reg, a, b);
+                       goto err_out_unmap;
+               }
+       }
+#endif /* USE_MMIO */
+
+       dev->base_addr = (unsigned long)ioaddr;
+       rp->base = ioaddr;
+
+       /* Get chip registers into a sane state */
+       rhine_power_init(dev);
+       rhine_hw_init(dev, pioaddr);
+
+       for (i = 0; i < 6; i++)
+               dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
+
+       if (!is_valid_ether_addr(dev->dev_addr)) {
+               /* Report it and use a random ethernet address instead */
+               netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr);
+               random_ether_addr(dev->dev_addr);
+               netdev_info(dev, "Using random MAC address: %pM\n",
+                           dev->dev_addr);
+       }
+       memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
+
+       /* For Rhine-I/II, phy_id is loaded from EEPROM */
+       if (!phy_id)
+               phy_id = ioread8(ioaddr + 0x6C);
+
+       dev->irq = pdev->irq;
+
+       spin_lock_init(&rp->lock);
+       INIT_WORK(&rp->reset_task, rhine_reset_task);
+
+       rp->mii_if.dev = dev;
+       rp->mii_if.mdio_read = mdio_read;
+       rp->mii_if.mdio_write = mdio_write;
+       rp->mii_if.phy_id_mask = 0x1f;
+       rp->mii_if.reg_num_mask = 0x1f;
+
+       /* The chip-specific entries in the device structure. */
+       dev->netdev_ops = &rhine_netdev_ops;
+       dev->ethtool_ops = &netdev_ethtool_ops,
+       dev->watchdog_timeo = TX_TIMEOUT;
+
+       netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
+
+       if (rp->quirks & rqRhineI)
+               dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
+
+       if (pdev->revision >= VT6105M)
+               dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
+               NETIF_F_HW_VLAN_FILTER;
+
+       /* dev->name not defined before register_netdev()! */
+       rc = register_netdev(dev);
+       if (rc)
+               goto err_out_unmap;
+
+       netdev_info(dev, "VIA %s at 0x%lx, %pM, IRQ %d\n",
+                   name,
+#ifdef USE_MMIO
+                   memaddr,
+#else
+                   (long)ioaddr,
+#endif
+                   dev->dev_addr, pdev->irq);
+
+       pci_set_drvdata(pdev, dev);
+
+       {
+               u16 mii_cmd;
+               int mii_status = mdio_read(dev, phy_id, 1);
+               mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
+               mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
+               if (mii_status != 0xffff && mii_status != 0x0000) {
+                       rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
+                       netdev_info(dev,
+                                   "MII PHY found at address %d, status 0x%04x advertising %04x Link %04x\n",
+                                   phy_id,
+                                   mii_status, rp->mii_if.advertising,
+                                   mdio_read(dev, phy_id, 5));
+
+                       /* set IFF_RUNNING */
+                       if (mii_status & BMSR_LSTATUS)
+                               netif_carrier_on(dev);
+                       else
+                               netif_carrier_off(dev);
+
+               }
+       }
+       rp->mii_if.phy_id = phy_id;
+       if (debug > 1 && avoid_D3)
+               netdev_info(dev, "No D3 power state at shutdown\n");
+
+       return 0;
+
+err_out_unmap:
+       pci_iounmap(pdev, ioaddr);
+err_out_free_res:
+       pci_release_regions(pdev);
+err_out_free_netdev:
+       free_netdev(dev);
+err_out:
+       return rc;
+}
+
+static int alloc_ring(struct net_device* dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void *ring;
+       dma_addr_t ring_dma;
+
+       ring = pci_alloc_consistent(rp->pdev,
+                                   RX_RING_SIZE * sizeof(struct rx_desc) +
+                                   TX_RING_SIZE * sizeof(struct tx_desc),
+                                   &ring_dma);
+       if (!ring) {
+               netdev_err(dev, "Could not allocate DMA memory\n");
+               return -ENOMEM;
+       }
+       if (rp->quirks & rqRhineI) {
+               rp->tx_bufs = pci_alloc_consistent(rp->pdev,
+                                                  PKT_BUF_SZ * TX_RING_SIZE,
+                                                  &rp->tx_bufs_dma);
+               if (rp->tx_bufs == NULL) {
+                       pci_free_consistent(rp->pdev,
+                                   RX_RING_SIZE * sizeof(struct rx_desc) +
+                                   TX_RING_SIZE * sizeof(struct tx_desc),
+                                   ring, ring_dma);
+                       return -ENOMEM;
+               }
+       }
+
+       rp->rx_ring = ring;
+       rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
+       rp->rx_ring_dma = ring_dma;
+       rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
+
+       return 0;
+}
+
+static void free_ring(struct net_device* dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+
+       pci_free_consistent(rp->pdev,
+                           RX_RING_SIZE * sizeof(struct rx_desc) +
+                           TX_RING_SIZE * sizeof(struct tx_desc),
+                           rp->rx_ring, rp->rx_ring_dma);
+       rp->tx_ring = NULL;
+
+       if (rp->tx_bufs)
+               pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
+                                   rp->tx_bufs, rp->tx_bufs_dma);
+
+       rp->tx_bufs = NULL;
+
+}
+
+static void alloc_rbufs(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       dma_addr_t next;
+       int i;
+
+       rp->dirty_rx = rp->cur_rx = 0;
+
+       rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
+       rp->rx_head_desc = &rp->rx_ring[0];
+       next = rp->rx_ring_dma;
+
+       /* Init the ring entries */
+       for (i = 0; i < RX_RING_SIZE; i++) {
+               rp->rx_ring[i].rx_status = 0;
+               rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
+               next += sizeof(struct rx_desc);
+               rp->rx_ring[i].next_desc = cpu_to_le32(next);
+               rp->rx_skbuff[i] = NULL;
+       }
+       /* Mark the last entry as wrapping the ring. */
+       rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
+
+       /* Fill in the Rx buffers.  Handle allocation failure gracefully. */
+       for (i = 0; i < RX_RING_SIZE; i++) {
+               struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
+               rp->rx_skbuff[i] = skb;
+               if (skb == NULL)
+                       break;
+               skb->dev = dev;                 /* Mark as being used by this device. */
+
+               rp->rx_skbuff_dma[i] =
+                       pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
+                                      PCI_DMA_FROMDEVICE);
+
+               rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
+               rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
+       }
+       rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
+}
+
+static void free_rbufs(struct net_device* dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       int i;
+
+       /* Free all the skbuffs in the Rx queue. */
+       for (i = 0; i < RX_RING_SIZE; i++) {
+               rp->rx_ring[i].rx_status = 0;
+               rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
+               if (rp->rx_skbuff[i]) {
+                       pci_unmap_single(rp->pdev,
+                                        rp->rx_skbuff_dma[i],
+                                        rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
+                       dev_kfree_skb(rp->rx_skbuff[i]);
+               }
+               rp->rx_skbuff[i] = NULL;
+       }
+}
+
+static void alloc_tbufs(struct net_device* dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       dma_addr_t next;
+       int i;
+
+       rp->dirty_tx = rp->cur_tx = 0;
+       next = rp->tx_ring_dma;
+       for (i = 0; i < TX_RING_SIZE; i++) {
+               rp->tx_skbuff[i] = NULL;
+               rp->tx_ring[i].tx_status = 0;
+               rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
+               next += sizeof(struct tx_desc);
+               rp->tx_ring[i].next_desc = cpu_to_le32(next);
+               if (rp->quirks & rqRhineI)
+                       rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
+       }
+       rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
+
+}
+
+static void free_tbufs(struct net_device* dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       int i;
+
+       for (i = 0; i < TX_RING_SIZE; i++) {
+               rp->tx_ring[i].tx_status = 0;
+               rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
+               rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
+               if (rp->tx_skbuff[i]) {
+                       if (rp->tx_skbuff_dma[i]) {
+                               pci_unmap_single(rp->pdev,
+                                                rp->tx_skbuff_dma[i],
+                                                rp->tx_skbuff[i]->len,
+                                                PCI_DMA_TODEVICE);
+                       }
+                       dev_kfree_skb(rp->tx_skbuff[i]);
+               }
+               rp->tx_skbuff[i] = NULL;
+               rp->tx_buf[i] = NULL;
+       }
+}
+
+static void rhine_check_media(struct net_device *dev, unsigned int init_media)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+
+       mii_check_media(&rp->mii_if, debug, init_media);
+
+       if (rp->mii_if.full_duplex)
+           iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
+                  ioaddr + ChipCmd1);
+       else
+           iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
+                  ioaddr + ChipCmd1);
+       if (debug > 1)
+               netdev_info(dev, "force_media %d, carrier %d\n",
+                           rp->mii_if.force_media, netif_carrier_ok(dev));
+}
+
+/* Called after status of force_media possibly changed */
+static void rhine_set_carrier(struct mii_if_info *mii)
+{
+       if (mii->force_media) {
+               /* autoneg is off: Link is always assumed to be up */
+               if (!netif_carrier_ok(mii->dev))
+                       netif_carrier_on(mii->dev);
+       }
+       else    /* Let MMI library update carrier status */
+               rhine_check_media(mii->dev, 0);
+       if (debug > 1)
+               netdev_info(mii->dev, "force_media %d, carrier %d\n",
+                           mii->force_media, netif_carrier_ok(mii->dev));
+}
+
+/**
+ * rhine_set_cam - set CAM multicast filters
+ * @ioaddr: register block of this Rhine
+ * @idx: multicast CAM index [0..MCAM_SIZE-1]
+ * @addr: multicast address (6 bytes)
+ *
+ * Load addresses into multicast filters.
+ */
+static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr)
+{
+       int i;
+
+       iowrite8(CAMC_CAMEN, ioaddr + CamCon);
+       wmb();
+
+       /* Paranoid -- idx out of range should never happen */
+       idx &= (MCAM_SIZE - 1);
+
+       iowrite8((u8) idx, ioaddr + CamAddr);
+
+       for (i = 0; i < 6; i++, addr++)
+               iowrite8(*addr, ioaddr + MulticastFilter0 + i);
+       udelay(10);
+       wmb();
+
+       iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
+       udelay(10);
+
+       iowrite8(0, ioaddr + CamCon);
+}
+
+/**
+ * rhine_set_vlan_cam - set CAM VLAN filters
+ * @ioaddr: register block of this Rhine
+ * @idx: VLAN CAM index [0..VCAM_SIZE-1]
+ * @addr: VLAN ID (2 bytes)
+ *
+ * Load addresses into VLAN filters.
+ */
+static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr)
+{
+       iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
+       wmb();
+
+       /* Paranoid -- idx out of range should never happen */
+       idx &= (VCAM_SIZE - 1);
+
+       iowrite8((u8) idx, ioaddr + CamAddr);
+
+       iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6);
+       udelay(10);
+       wmb();
+
+       iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
+       udelay(10);
+
+       iowrite8(0, ioaddr + CamCon);
+}
+
+/**
+ * rhine_set_cam_mask - set multicast CAM mask
+ * @ioaddr: register block of this Rhine
+ * @mask: multicast CAM mask
+ *
+ * Mask sets multicast filters active/inactive.
+ */
+static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask)
+{
+       iowrite8(CAMC_CAMEN, ioaddr + CamCon);
+       wmb();
+
+       /* write mask */
+       iowrite32(mask, ioaddr + CamMask);
+
+       /* disable CAMEN */
+       iowrite8(0, ioaddr + CamCon);
+}
+
+/**
+ * rhine_set_vlan_cam_mask - set VLAN CAM mask
+ * @ioaddr: register block of this Rhine
+ * @mask: VLAN CAM mask
+ *
+ * Mask sets VLAN filters active/inactive.
+ */
+static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask)
+{
+       iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
+       wmb();
+
+       /* write mask */
+       iowrite32(mask, ioaddr + CamMask);
+
+       /* disable CAMEN */
+       iowrite8(0, ioaddr + CamCon);
+}
+
+/**
+ * rhine_init_cam_filter - initialize CAM filters
+ * @dev: network device
+ *
+ * Initialize (disable) hardware VLAN and multicast support on this
+ * Rhine.
+ */
+static void rhine_init_cam_filter(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+
+       /* Disable all CAMs */
+       rhine_set_vlan_cam_mask(ioaddr, 0);
+       rhine_set_cam_mask(ioaddr, 0);
+
+       /* disable hardware VLAN support */
+       BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig);
+       BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
+}
+
+/**
+ * rhine_update_vcam - update VLAN CAM filters
+ * @rp: rhine_private data of this Rhine
+ *
+ * Update VLAN CAM filters to match configuration change.
+ */
+static void rhine_update_vcam(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+       u16 vid;
+       u32 vCAMmask = 0;       /* 32 vCAMs (6105M and better) */
+       unsigned int i = 0;
+
+       for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) {
+               rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid);
+               vCAMmask |= 1 << i;
+               if (++i >= VCAM_SIZE)
+                       break;
+       }
+       rhine_set_vlan_cam_mask(ioaddr, vCAMmask);
+}
+
+static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+
+       spin_lock_irq(&rp->lock);
+       set_bit(vid, rp->active_vlans);
+       rhine_update_vcam(dev);
+       spin_unlock_irq(&rp->lock);
+}
+
+static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+
+       spin_lock_irq(&rp->lock);
+       clear_bit(vid, rp->active_vlans);
+       rhine_update_vcam(dev);
+       spin_unlock_irq(&rp->lock);
+}
+
+static void init_registers(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+       int i;
+
+       for (i = 0; i < 6; i++)
+               iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
+
+       /* Initialize other registers. */
+       iowrite16(0x0006, ioaddr + PCIBusConfig);       /* Tune configuration??? */
+       /* Configure initial FIFO thresholds. */
+       iowrite8(0x20, ioaddr + TxConfig);
+       rp->tx_thresh = 0x20;
+       rp->rx_thresh = 0x60;           /* Written in rhine_set_rx_mode(). */
+
+       iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
+       iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
+
+       rhine_set_rx_mode(dev);
+
+       if (rp->pdev->revision >= VT6105M)
+               rhine_init_cam_filter(dev);
+
+       napi_enable(&rp->napi);
+
+       /* Enable interrupts by setting the interrupt mask. */
+       iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
+              IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
+              IntrTxDone | IntrTxError | IntrTxUnderrun |
+              IntrPCIErr | IntrStatsMax | IntrLinkChange,
+              ioaddr + IntrEnable);
+
+       iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
+              ioaddr + ChipCmd);
+       rhine_check_media(dev, 1);
+}
+
+/* Enable MII link status auto-polling (required for IntrLinkChange) */
+static void rhine_enable_linkmon(void __iomem *ioaddr)
+{
+       iowrite8(0, ioaddr + MIICmd);
+       iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
+       iowrite8(0x80, ioaddr + MIICmd);
+
+       RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
+
+       iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
+}
+
+/* Disable MII link status auto-polling (required for MDIO access) */
+static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
+{
+       iowrite8(0, ioaddr + MIICmd);
+
+       if (quirks & rqRhineI) {
+               iowrite8(0x01, ioaddr + MIIRegAddr);    // MII_BMSR
+
+               /* Can be called from ISR. Evil. */
+               mdelay(1);
+
+               /* 0x80 must be set immediately before turning it off */
+               iowrite8(0x80, ioaddr + MIICmd);
+
+               RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
+
+               /* Heh. Now clear 0x80 again. */
+               iowrite8(0, ioaddr + MIICmd);
+       }
+       else
+               RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
+}
+
+/* Read and write over the MII Management Data I/O (MDIO) interface. */
+
+static int mdio_read(struct net_device *dev, int phy_id, int regnum)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+       int result;
+
+       rhine_disable_linkmon(ioaddr, rp->quirks);
+
+       /* rhine_disable_linkmon already cleared MIICmd */
+       iowrite8(phy_id, ioaddr + MIIPhyAddr);
+       iowrite8(regnum, ioaddr + MIIRegAddr);
+       iowrite8(0x40, ioaddr + MIICmd);                /* Trigger read */
+       RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
+       result = ioread16(ioaddr + MIIData);
+
+       rhine_enable_linkmon(ioaddr);
+       return result;
+}
+
+static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+
+       rhine_disable_linkmon(ioaddr, rp->quirks);
+
+       /* rhine_disable_linkmon already cleared MIICmd */
+       iowrite8(phy_id, ioaddr + MIIPhyAddr);
+       iowrite8(regnum, ioaddr + MIIRegAddr);
+       iowrite16(value, ioaddr + MIIData);
+       iowrite8(0x20, ioaddr + MIICmd);                /* Trigger write */
+       RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
+
+       rhine_enable_linkmon(ioaddr);
+}
+
+static int rhine_open(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+       int rc;
+
+       rc = request_irq(rp->pdev->irq, rhine_interrupt, IRQF_SHARED, dev->name,
+                       dev);
+       if (rc)
+               return rc;
+
+       if (debug > 1)
+               netdev_dbg(dev, "%s() irq %d\n", __func__, rp->pdev->irq);
+
+       rc = alloc_ring(dev);
+       if (rc) {
+               free_irq(rp->pdev->irq, dev);
+               return rc;
+       }
+       alloc_rbufs(dev);
+       alloc_tbufs(dev);
+       rhine_chip_reset(dev);
+       init_registers(dev);
+       if (debug > 2)
+               netdev_dbg(dev, "%s() Done - status %04x MII status: %04x\n",
+                          __func__, ioread16(ioaddr + ChipCmd),
+                          mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
+
+       netif_start_queue(dev);
+
+       return 0;
+}
+
+static void rhine_reset_task(struct work_struct *work)
+{
+       struct rhine_private *rp = container_of(work, struct rhine_private,
+                                               reset_task);
+       struct net_device *dev = rp->dev;
+
+       /* protect against concurrent rx interrupts */
+       disable_irq(rp->pdev->irq);
+
+       napi_disable(&rp->napi);
+
+       spin_lock_bh(&rp->lock);
+
+       /* clear all descriptors */
+       free_tbufs(dev);
+       free_rbufs(dev);
+       alloc_tbufs(dev);
+       alloc_rbufs(dev);
+
+       /* Reinitialize the hardware. */
+       rhine_chip_reset(dev);
+       init_registers(dev);
+
+       spin_unlock_bh(&rp->lock);
+       enable_irq(rp->pdev->irq);
+
+       dev->trans_start = jiffies; /* prevent tx timeout */
+       dev->stats.tx_errors++;
+       netif_wake_queue(dev);
+}
+
+static void rhine_tx_timeout(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+
+       netdev_warn(dev, "Transmit timed out, status %04x, PHY status %04x, resetting...\n",
+                   ioread16(ioaddr + IntrStatus),
+                   mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
+
+       schedule_work(&rp->reset_task);
+}
+
+static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
+                                 struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+       unsigned entry;
+       unsigned long flags;
+
+       /* Caution: the write order is important here, set the field
+          with the "ownership" bits last. */
+
+       /* Calculate the next Tx descriptor entry. */
+       entry = rp->cur_tx % TX_RING_SIZE;
+
+       if (skb_padto(skb, ETH_ZLEN))
+               return NETDEV_TX_OK;
+
+       rp->tx_skbuff[entry] = skb;
+
+       if ((rp->quirks & rqRhineI) &&
+           (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
+               /* Must use alignment buffer. */
+               if (skb->len > PKT_BUF_SZ) {
+                       /* packet too long, drop it */
+                       dev_kfree_skb(skb);
+                       rp->tx_skbuff[entry] = NULL;
+                       dev->stats.tx_dropped++;
+                       return NETDEV_TX_OK;
+               }
+
+               /* Padding is not copied and so must be redone. */
+               skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
+               if (skb->len < ETH_ZLEN)
+                       memset(rp->tx_buf[entry] + skb->len, 0,
+                              ETH_ZLEN - skb->len);
+               rp->tx_skbuff_dma[entry] = 0;
+               rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
+                                                     (rp->tx_buf[entry] -
+                                                      rp->tx_bufs));
+       } else {
+               rp->tx_skbuff_dma[entry] =
+                       pci_map_single(rp->pdev, skb->data, skb->len,
+                                      PCI_DMA_TODEVICE);
+               rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
+       }
+
+       rp->tx_ring[entry].desc_length =
+               cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
+
+       if (unlikely(vlan_tx_tag_present(skb))) {
+               rp->tx_ring[entry].tx_status = cpu_to_le32((vlan_tx_tag_get(skb)) << 16);
+               /* request tagging */
+               rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);
+       }
+       else
+               rp->tx_ring[entry].tx_status = 0;
+
+       /* lock eth irq */
+       spin_lock_irqsave(&rp->lock, flags);
+       wmb();
+       rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn);
+       wmb();
+
+       rp->cur_tx++;
+
+       /* Non-x86 Todo: explicitly flush cache lines here. */
+
+       if (vlan_tx_tag_present(skb))
+               /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
+               BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
+
+       /* Wake the potentially-idle transmit channel */
+       iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
+              ioaddr + ChipCmd1);
+       IOSYNC;
+
+       if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
+               netif_stop_queue(dev);
+
+       spin_unlock_irqrestore(&rp->lock, flags);
+
+       if (debug > 4) {
+               netdev_dbg(dev, "Transmit frame #%d queued in slot %d\n",
+                          rp->cur_tx-1, entry);
+       }
+       return NETDEV_TX_OK;
+}
+
+/* The interrupt handler does all of the Rx thread work and cleans up
+   after the Tx thread. */
+static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
+{
+       struct net_device *dev = dev_instance;
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+       u32 intr_status;
+       int boguscnt = max_interrupt_work;
+       int handled = 0;
+
+       while ((intr_status = get_intr_status(dev))) {
+               handled = 1;
+
+               /* Acknowledge all of the current interrupt sources ASAP. */
+               if (intr_status & IntrTxDescRace)
+                       iowrite8(0x08, ioaddr + IntrStatus2);
+               iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
+               IOSYNC;
+
+               if (debug > 4)
+                       netdev_dbg(dev, "Interrupt, status %08x\n",
+                                  intr_status);
+
+               if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
+                                  IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {
+                       iowrite16(IntrTxAborted |
+                                 IntrTxDone | IntrTxError | IntrTxUnderrun |
+                                 IntrPCIErr | IntrStatsMax | IntrLinkChange,
+                                 ioaddr + IntrEnable);
+
+                       napi_schedule(&rp->napi);
+               }
+
+               if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
+                       if (intr_status & IntrTxErrSummary) {
+                               /* Avoid scavenging before Tx engine turned off */
+                               RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
+                               if (debug > 2 &&
+                                   ioread8(ioaddr+ChipCmd) & CmdTxOn)
+                                       netdev_warn(dev,
+                                                   "%s: Tx engine still on\n",
+                                                   __func__);
+                       }
+                       rhine_tx(dev);
+               }
+
+               /* Abnormal error summary/uncommon events handlers. */
+               if (intr_status & (IntrPCIErr | IntrLinkChange |
+                                  IntrStatsMax | IntrTxError | IntrTxAborted |
+                                  IntrTxUnderrun | IntrTxDescRace))
+                       rhine_error(dev, intr_status);
+
+               if (--boguscnt < 0) {
+                       netdev_warn(dev, "Too much work at interrupt, status=%#08x\n",
+                                   intr_status);
+                       break;
+               }
+       }
+
+       if (debug > 3)
+               netdev_dbg(dev, "exiting interrupt, status=%08x\n",
+                          ioread16(ioaddr + IntrStatus));
+       return IRQ_RETVAL(handled);
+}
+
+/* This routine is logically part of the interrupt handler, but isolated
+   for clarity. */
+static void rhine_tx(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
+
+       spin_lock(&rp->lock);
+
+       /* find and cleanup dirty tx descriptors */
+       while (rp->dirty_tx != rp->cur_tx) {
+               txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
+               if (debug > 6)
+                       netdev_dbg(dev, "Tx scavenge %d status %08x\n",
+                                  entry, txstatus);
+               if (txstatus & DescOwn)
+                       break;
+               if (txstatus & 0x8000) {
+                       if (debug > 1)
+                               netdev_dbg(dev, "Transmit error, Tx status %08x\n",
+                                          txstatus);
+                       dev->stats.tx_errors++;
+                       if (txstatus & 0x0400)
+                               dev->stats.tx_carrier_errors++;
+                       if (txstatus & 0x0200)
+                               dev->stats.tx_window_errors++;
+                       if (txstatus & 0x0100)
+                               dev->stats.tx_aborted_errors++;
+                       if (txstatus & 0x0080)
+                               dev->stats.tx_heartbeat_errors++;
+                       if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
+                           (txstatus & 0x0800) || (txstatus & 0x1000)) {
+                               dev->stats.tx_fifo_errors++;
+                               rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
+                               break; /* Keep the skb - we try again */
+                       }
+                       /* Transmitter restarted in 'abnormal' handler. */
+               } else {
+                       if (rp->quirks & rqRhineI)
+                               dev->stats.collisions += (txstatus >> 3) & 0x0F;
+                       else
+                               dev->stats.collisions += txstatus & 0x0F;
+                       if (debug > 6)
+                               netdev_dbg(dev, "collisions: %1.1x:%1.1x\n",
+                                          (txstatus >> 3) & 0xF,
+                                          txstatus & 0xF);
+                       dev->stats.tx_bytes += rp->tx_skbuff[entry]->len;
+                       dev->stats.tx_packets++;
+               }
+               /* Free the original skb. */
+               if (rp->tx_skbuff_dma[entry]) {
+                       pci_unmap_single(rp->pdev,
+                                        rp->tx_skbuff_dma[entry],
+                                        rp->tx_skbuff[entry]->len,
+                                        PCI_DMA_TODEVICE);
+               }
+               dev_kfree_skb_irq(rp->tx_skbuff[entry]);
+               rp->tx_skbuff[entry] = NULL;
+               entry = (++rp->dirty_tx) % TX_RING_SIZE;
+       }
+       if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
+               netif_wake_queue(dev);
+
+       spin_unlock(&rp->lock);
+}
+
+/**
+ * rhine_get_vlan_tci - extract TCI from Rx data buffer
+ * @skb: pointer to sk_buff
+ * @data_size: used data area of the buffer including CRC
+ *
+ * If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q
+ * packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte
+ * aligned following the CRC.
+ */
+static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size)
+{
+       u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2;
+       return be16_to_cpup((__be16 *)trailer);
+}
+
+/* Process up to limit frames from receive ring */
+static int rhine_rx(struct net_device *dev, int limit)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       int count;
+       int entry = rp->cur_rx % RX_RING_SIZE;
+
+       if (debug > 4) {
+               netdev_dbg(dev, "%s(), entry %d status %08x\n",
+                          __func__, entry,
+                          le32_to_cpu(rp->rx_head_desc->rx_status));
+       }
+
+       /* If EOP is set on the next entry, it's a new packet. Send it up. */
+       for (count = 0; count < limit; ++count) {
+               struct rx_desc *desc = rp->rx_head_desc;
+               u32 desc_status = le32_to_cpu(desc->rx_status);
+               u32 desc_length = le32_to_cpu(desc->desc_length);
+               int data_size = desc_status >> 16;
+
+               if (desc_status & DescOwn)
+                       break;
+
+               if (debug > 4)
+                       netdev_dbg(dev, "%s() status is %08x\n",
+                                  __func__, desc_status);
+
+               if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
+                       if ((desc_status & RxWholePkt) != RxWholePkt) {
+                               netdev_warn(dev,
+       "Oversized Ethernet frame spanned multiple buffers, "
+       "entry %#x length %d status %08x!\n",
+                                           entry, data_size,
+                                           desc_status);
+                               netdev_warn(dev,
+                                           "Oversized Ethernet frame %p vs %p\n",
+                                           rp->rx_head_desc,
+                                           &rp->rx_ring[entry]);
+                               dev->stats.rx_length_errors++;
+                       } else if (desc_status & RxErr) {
+                               /* There was a error. */
+                               if (debug > 2)
+                                       netdev_dbg(dev, "%s() Rx error was %08x\n",
+                                                  __func__, desc_status);
+                               dev->stats.rx_errors++;
+                               if (desc_status & 0x0030)
+                                       dev->stats.rx_length_errors++;
+                               if (desc_status & 0x0048)
+                                       dev->stats.rx_fifo_errors++;
+                               if (desc_status & 0x0004)
+                                       dev->stats.rx_frame_errors++;
+                               if (desc_status & 0x0002) {
+                                       /* this can also be updated outside the interrupt handler */
+                                       spin_lock(&rp->lock);
+                                       dev->stats.rx_crc_errors++;
+                                       spin_unlock(&rp->lock);
+                               }
+                       }
+               } else {
+                       struct sk_buff *skb = NULL;
+                       /* Length should omit the CRC */
+                       int pkt_len = data_size - 4;
+                       u16 vlan_tci = 0;
+
+                       /* Check if the packet is long enough to accept without
+                          copying to a minimally-sized skbuff. */
+                       if (pkt_len < rx_copybreak)
+                               skb = netdev_alloc_skb_ip_align(dev, pkt_len);
+                       if (skb) {
+                               pci_dma_sync_single_for_cpu(rp->pdev,
+                                                           rp->rx_skbuff_dma[entry],
+                                                           rp->rx_buf_sz,
+                                                           PCI_DMA_FROMDEVICE);
+
+                               skb_copy_to_linear_data(skb,
+                                                rp->rx_skbuff[entry]->data,
+                                                pkt_len);
+                               skb_put(skb, pkt_len);
+                               pci_dma_sync_single_for_device(rp->pdev,
+                                                              rp->rx_skbuff_dma[entry],
+                                                              rp->rx_buf_sz,
+                                                              PCI_DMA_FROMDEVICE);
+                       } else {
+                               skb = rp->rx_skbuff[entry];
+                               if (skb == NULL) {
+                                       netdev_err(dev, "Inconsistent Rx descriptor chain\n");
+                                       break;
+                               }
+                               rp->rx_skbuff[entry] = NULL;
+                               skb_put(skb, pkt_len);
+                               pci_unmap_single(rp->pdev,
+                                                rp->rx_skbuff_dma[entry],
+                                                rp->rx_buf_sz,
+                                                PCI_DMA_FROMDEVICE);
+                       }
+
+                       if (unlikely(desc_length & DescTag))
+                               vlan_tci = rhine_get_vlan_tci(skb, data_size);
+
+                       skb->protocol = eth_type_trans(skb, dev);
+
+                       if (unlikely(desc_length & DescTag))
+                               __vlan_hwaccel_put_tag(skb, vlan_tci);
+                       netif_receive_skb(skb);
+                       dev->stats.rx_bytes += pkt_len;
+                       dev->stats.rx_packets++;
+               }
+               entry = (++rp->cur_rx) % RX_RING_SIZE;
+               rp->rx_head_desc = &rp->rx_ring[entry];
+       }
+
+       /* Refill the Rx ring buffers. */
+       for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
+               struct sk_buff *skb;
+               entry = rp->dirty_rx % RX_RING_SIZE;
+               if (rp->rx_skbuff[entry] == NULL) {
+                       skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
+                       rp->rx_skbuff[entry] = skb;
+                       if (skb == NULL)
+                               break;  /* Better luck next round. */
+                       skb->dev = dev; /* Mark as being used by this device. */
+                       rp->rx_skbuff_dma[entry] =
+                               pci_map_single(rp->pdev, skb->data,
+                                              rp->rx_buf_sz,
+                                              PCI_DMA_FROMDEVICE);
+                       rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
+               }
+               rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
+       }
+
+       return count;
+}
+
+/*
+ * Clears the "tally counters" for CRC errors and missed frames(?).
+ * It has been reported that some chips need a write of 0 to clear
+ * these, for others the counters are set to 1 when written to and
+ * instead cleared when read. So we clear them both ways ...
+ */
+static inline void clear_tally_counters(void __iomem *ioaddr)
+{
+       iowrite32(0, ioaddr + RxMissed);
+       ioread16(ioaddr + RxCRCErrs);
+       ioread16(ioaddr + RxMissed);
+}
+
+static void rhine_restart_tx(struct net_device *dev) {
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+       int entry = rp->dirty_tx % TX_RING_SIZE;
+       u32 intr_status;
+
+       /*
+        * If new errors occurred, we need to sort them out before doing Tx.
+        * In that case the ISR will be back here RSN anyway.
+        */
+       intr_status = get_intr_status(dev);
+
+       if ((intr_status & IntrTxErrSummary) == 0) {
+
+               /* We know better than the chip where it should continue. */
+               iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
+                      ioaddr + TxRingPtr);
+
+               iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
+                      ioaddr + ChipCmd);
+
+               if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))
+                       /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
+                       BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
+
+               iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
+                      ioaddr + ChipCmd1);
+               IOSYNC;
+       }
+       else {
+               /* This should never happen */
+               if (debug > 1)
+                       netdev_warn(dev, "%s() Another error occurred %08x\n",
+                                  __func__, intr_status);
+       }
+
+}
+
+static void rhine_error(struct net_device *dev, int intr_status)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+
+       spin_lock(&rp->lock);
+
+       if (intr_status & IntrLinkChange)
+               rhine_check_media(dev, 0);
+       if (intr_status & IntrStatsMax) {
+               dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
+               dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
+               clear_tally_counters(ioaddr);
+       }
+       if (intr_status & IntrTxAborted) {
+               if (debug > 1)
+                       netdev_info(dev, "Abort %08x, frame dropped\n",
+                                   intr_status);
+       }
+       if (intr_status & IntrTxUnderrun) {
+               if (rp->tx_thresh < 0xE0)
+                       BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);
+               if (debug > 1)
+                       netdev_info(dev, "Transmitter underrun, Tx threshold now %02x\n",
+                                   rp->tx_thresh);
+       }
+       if (intr_status & IntrTxDescRace) {
+               if (debug > 2)
+                       netdev_info(dev, "Tx descriptor write-back race\n");
+       }
+       if ((intr_status & IntrTxError) &&
+           (intr_status & (IntrTxAborted |
+            IntrTxUnderrun | IntrTxDescRace)) == 0) {
+               if (rp->tx_thresh < 0xE0) {
+                       BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);
+               }
+               if (debug > 1)
+                       netdev_info(dev, "Unspecified error. Tx threshold now %02x\n",
+                                   rp->tx_thresh);
+       }
+       if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
+                          IntrTxError))
+               rhine_restart_tx(dev);
+
+       if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
+                           IntrTxError | IntrTxAborted | IntrNormalSummary |
+                           IntrTxDescRace)) {
+               if (debug > 1)
+                       netdev_err(dev, "Something Wicked happened! %08x\n",
+                                  intr_status);
+       }
+
+       spin_unlock(&rp->lock);
+}
+
+static struct net_device_stats *rhine_get_stats(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+       unsigned long flags;
+
+       spin_lock_irqsave(&rp->lock, flags);
+       dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
+       dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
+       clear_tally_counters(ioaddr);
+       spin_unlock_irqrestore(&rp->lock, flags);
+
+       return &dev->stats;
+}
+
+static void rhine_set_rx_mode(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+       u32 mc_filter[2];       /* Multicast hash filter */
+       u8 rx_mode = 0x0C;      /* Note: 0x02=accept runt, 0x01=accept errs */
+       struct netdev_hw_addr *ha;
+
+       if (dev->flags & IFF_PROMISC) {         /* Set promiscuous. */
+               rx_mode = 0x1C;
+               iowrite32(0xffffffff, ioaddr + MulticastFilter0);
+               iowrite32(0xffffffff, ioaddr + MulticastFilter1);
+       } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
+                  (dev->flags & IFF_ALLMULTI)) {
+               /* Too many to match, or accept all multicasts. */
+               iowrite32(0xffffffff, ioaddr + MulticastFilter0);
+               iowrite32(0xffffffff, ioaddr + MulticastFilter1);
+       } else if (rp->pdev->revision >= VT6105M) {
+               int i = 0;
+               u32 mCAMmask = 0;       /* 32 mCAMs (6105M and better) */
+               netdev_for_each_mc_addr(ha, dev) {
+                       if (i == MCAM_SIZE)
+                               break;
+                       rhine_set_cam(ioaddr, i, ha->addr);
+                       mCAMmask |= 1 << i;
+                       i++;
+               }
+               rhine_set_cam_mask(ioaddr, mCAMmask);
+       } else {
+               memset(mc_filter, 0, sizeof(mc_filter));
+               netdev_for_each_mc_addr(ha, dev) {
+                       int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
+
+                       mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
+               }
+               iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
+               iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
+       }
+       /* enable/disable VLAN receive filtering */
+       if (rp->pdev->revision >= VT6105M) {
+               if (dev->flags & IFF_PROMISC)
+                       BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
+               else
+                       BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1);
+       }
+       BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig);
+}
+
+static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+
+       strcpy(info->driver, DRV_NAME);
+       strcpy(info->version, DRV_VERSION);
+       strcpy(info->bus_info, pci_name(rp->pdev));
+}
+
+static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       int rc;
+
+       spin_lock_irq(&rp->lock);
+       rc = mii_ethtool_gset(&rp->mii_if, cmd);
+       spin_unlock_irq(&rp->lock);
+
+       return rc;
+}
+
+static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       int rc;
+
+       spin_lock_irq(&rp->lock);
+       rc = mii_ethtool_sset(&rp->mii_if, cmd);
+       spin_unlock_irq(&rp->lock);
+       rhine_set_carrier(&rp->mii_if);
+
+       return rc;
+}
+
+static int netdev_nway_reset(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+
+       return mii_nway_restart(&rp->mii_if);
+}
+
+static u32 netdev_get_link(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+
+       return mii_link_ok(&rp->mii_if);
+}
+
+static u32 netdev_get_msglevel(struct net_device *dev)
+{
+       return debug;
+}
+
+static void netdev_set_msglevel(struct net_device *dev, u32 value)
+{
+       debug = value;
+}
+
+static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+
+       if (!(rp->quirks & rqWOL))
+               return;
+
+       spin_lock_irq(&rp->lock);
+       wol->supported = WAKE_PHY | WAKE_MAGIC |
+                        WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;  /* Untested */
+       wol->wolopts = rp->wolopts;
+       spin_unlock_irq(&rp->lock);
+}
+
+static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       u32 support = WAKE_PHY | WAKE_MAGIC |
+                     WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;     /* Untested */
+
+       if (!(rp->quirks & rqWOL))
+               return -EINVAL;
+
+       if (wol->wolopts & ~support)
+               return -EINVAL;
+
+       spin_lock_irq(&rp->lock);
+       rp->wolopts = wol->wolopts;
+       spin_unlock_irq(&rp->lock);
+
+       return 0;
+}
+
+static const struct ethtool_ops netdev_ethtool_ops = {
+       .get_drvinfo            = netdev_get_drvinfo,
+       .get_settings           = netdev_get_settings,
+       .set_settings           = netdev_set_settings,
+       .nway_reset             = netdev_nway_reset,
+       .get_link               = netdev_get_link,
+       .get_msglevel           = netdev_get_msglevel,
+       .set_msglevel           = netdev_set_msglevel,
+       .get_wol                = rhine_get_wol,
+       .set_wol                = rhine_set_wol,
+};
+
+static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       int rc;
+
+       if (!netif_running(dev))
+               return -EINVAL;
+
+       spin_lock_irq(&rp->lock);
+       rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
+       spin_unlock_irq(&rp->lock);
+       rhine_set_carrier(&rp->mii_if);
+
+       return rc;
+}
+
+static int rhine_close(struct net_device *dev)
+{
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+
+       napi_disable(&rp->napi);
+       cancel_work_sync(&rp->reset_task);
+       netif_stop_queue(dev);
+
+       spin_lock_irq(&rp->lock);
+
+       if (debug > 1)
+               netdev_dbg(dev, "Shutting down ethercard, status was %04x\n",
+                          ioread16(ioaddr + ChipCmd));
+
+       /* Switch to loopback mode to avoid hardware races. */
+       iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
+
+       /* Disable interrupts by clearing the interrupt mask. */
+       iowrite16(0x0000, ioaddr + IntrEnable);
+
+       /* Stop the chip's Tx and Rx processes. */
+       iowrite16(CmdStop, ioaddr + ChipCmd);
+
+       spin_unlock_irq(&rp->lock);
+
+       free_irq(rp->pdev->irq, dev);
+       free_rbufs(dev);
+       free_tbufs(dev);
+       free_ring(dev);
+
+       return 0;
+}
+
+
+static void __devexit rhine_remove_one(struct pci_dev *pdev)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct rhine_private *rp = netdev_priv(dev);
+
+       unregister_netdev(dev);
+
+       pci_iounmap(pdev, rp->base);
+       pci_release_regions(pdev);
+
+       free_netdev(dev);
+       pci_disable_device(pdev);
+       pci_set_drvdata(pdev, NULL);
+}
+
+static void rhine_shutdown (struct pci_dev *pdev)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct rhine_private *rp = netdev_priv(dev);
+       void __iomem *ioaddr = rp->base;
+
+       if (!(rp->quirks & rqWOL))
+               return; /* Nothing to do for non-WOL adapters */
+
+       rhine_power_init(dev);
+
+       /* Make sure we use pattern 0, 1 and not 4, 5 */
+       if (rp->quirks & rq6patterns)
+               iowrite8(0x04, ioaddr + WOLcgClr);
+
+       if (rp->wolopts & WAKE_MAGIC) {
+               iowrite8(WOLmagic, ioaddr + WOLcrSet);
+               /*
+                * Turn EEPROM-controlled wake-up back on -- some hardware may
+                * not cooperate otherwise.
+                */
+               iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
+       }
+
+       if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
+               iowrite8(WOLbmcast, ioaddr + WOLcgSet);
+
+       if (rp->wolopts & WAKE_PHY)
+               iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
+
+       if (rp->wolopts & WAKE_UCAST)
+               iowrite8(WOLucast, ioaddr + WOLcrSet);
+
+       if (rp->wolopts) {
+               /* Enable legacy WOL (for old motherboards) */
+               iowrite8(0x01, ioaddr + PwcfgSet);
+               iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
+       }
+
+       /* Hit power state D3 (sleep) */
+       if (!avoid_D3)
+               iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
+
+       /* TODO: Check use of pci_enable_wake() */
+
+}
+
+#ifdef CONFIG_PM
+static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct rhine_private *rp = netdev_priv(dev);
+       unsigned long flags;
+
+       if (!netif_running(dev))
+               return 0;
+
+       napi_disable(&rp->napi);
+
+       netif_device_detach(dev);
+       pci_save_state(pdev);
+
+       spin_lock_irqsave(&rp->lock, flags);
+       rhine_shutdown(pdev);
+       spin_unlock_irqrestore(&rp->lock, flags);
+
+       free_irq(dev->irq, dev);
+       return 0;
+}
+
+static int rhine_resume(struct pci_dev *pdev)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct rhine_private *rp = netdev_priv(dev);
+       unsigned long flags;
+       int ret;
+
+       if (!netif_running(dev))
+               return 0;
+
+       if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
+               netdev_err(dev, "request_irq failed\n");
+
+       ret = pci_set_power_state(pdev, PCI_D0);
+       if (debug > 1)
+               netdev_info(dev, "Entering power state D0 %s (%d)\n",
+                           ret ? "failed" : "succeeded", ret);
+
+       pci_restore_state(pdev);
+
+       spin_lock_irqsave(&rp->lock, flags);
+#ifdef USE_MMIO
+       enable_mmio(rp->pioaddr, rp->quirks);
+#endif
+       rhine_power_init(dev);
+       free_tbufs(dev);
+       free_rbufs(dev);
+       alloc_tbufs(dev);
+       alloc_rbufs(dev);
+       init_registers(dev);
+       spin_unlock_irqrestore(&rp->lock, flags);
+
+       netif_device_attach(dev);
+
+       return 0;
+}
+#endif /* CONFIG_PM */
+
+static struct pci_driver rhine_driver = {
+       .name           = DRV_NAME,
+       .id_table       = rhine_pci_tbl,
+       .probe          = rhine_init_one,
+       .remove         = __devexit_p(rhine_remove_one),
+#ifdef CONFIG_PM
+       .suspend        = rhine_suspend,
+       .resume         = rhine_resume,
+#endif /* CONFIG_PM */
+       .shutdown =     rhine_shutdown,
+};
+
+static struct dmi_system_id __initdata rhine_dmi_table[] = {
+       {
+               .ident = "EPIA-M",
+               .matches = {
+                       DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
+                       DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
+               },
+       },
+       {
+               .ident = "KV7",
+               .matches = {
+                       DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
+                       DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
+               },
+       },
+       { NULL }
+};
+
+static int __init rhine_init(void)
+{
+/* when a module, this is printed whether or not devices are found in probe */
+#ifdef MODULE
+       pr_info("%s\n", version);
+#endif
+       if (dmi_check_system(rhine_dmi_table)) {
+               /* these BIOSes fail at PXE boot if chip is in D3 */
+               avoid_D3 = 1;
+               pr_warn("Broken BIOS detected, avoid_D3 enabled\n");
+       }
+       else if (avoid_D3)
+               pr_info("avoid_D3 set\n");
+
+       return pci_register_driver(&rhine_driver);
+}
+
+
+static void __exit rhine_cleanup(void)
+{
+       pci_unregister_driver(&rhine_driver);
+}
+
+
+module_init(rhine_init);
+module_exit(rhine_cleanup);
diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
new file mode 100644 (file)
index 0000000..490ec5b
--- /dev/null
@@ -0,0 +1,3592 @@
+/*
+ * This code is derived from the VIA reference driver (copyright message
+ * below) provided to Red Hat by VIA Networking Technologies, Inc. for
+ * addition to the Linux kernel.
+ *
+ * The code has been merged into one source file, cleaned up to follow
+ * Linux coding style,  ported to the Linux 2.6 kernel tree and cleaned
+ * for 64bit hardware platforms.
+ *
+ * TODO
+ *     rx_copybreak/alignment
+ *     More testing
+ *
+ * The changes are (c) Copyright 2004, Red Hat Inc. <alan@lxorguk.ukuu.org.uk>
+ * Additional fixes and clean up: Francois Romieu
+ *
+ * This source has not been verified for use in safety critical systems.
+ *
+ * Please direct queries about the revamped driver to the linux-kernel
+ * list not VIA.
+ *
+ * Original code:
+ *
+ * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
+ * All rights reserved.
+ *
+ * This software may be redistributed and/or modified under
+ * the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * Author: Chuang Liang-Shing, AJ Jiang
+ *
+ * Date: Jan 24, 2003
+ *
+ * MODULE_LICENSE("GPL");
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/bitops.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/delay.h>
+#include <linux/timer.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/string.h>
+#include <linux/wait.h>
+#include <linux/io.h>
+#include <linux/if.h>
+#include <linux/uaccess.h>
+#include <linux/proc_fs.h>
+#include <linux/inetdevice.h>
+#include <linux/reboot.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <linux/in.h>
+#include <linux/if_arp.h>
+#include <linux/if_vlan.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/udp.h>
+#include <linux/crc-ccitt.h>
+#include <linux/crc32.h>
+
+#include "via-velocity.h"
+
+
+static int velocity_nics;
+static int msglevel = MSG_LEVEL_INFO;
+
+/**
+ *     mac_get_cam_mask        -       Read a CAM mask
+ *     @regs: register block for this velocity
+ *     @mask: buffer to store mask
+ *
+ *     Fetch the mask bits of the selected CAM and store them into the
+ *     provided mask buffer.
+ */
+static void mac_get_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
+{
+       int i;
+
+       /* Select CAM mask */
+       BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
+
+       writeb(0, &regs->CAMADDR);
+
+       /* read mask */
+       for (i = 0; i < 8; i++)
+               *mask++ = readb(&(regs->MARCAM[i]));
+
+       /* disable CAMEN */
+       writeb(0, &regs->CAMADDR);
+
+       /* Select mar */
+       BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
+}
+
+/**
+ *     mac_set_cam_mask        -       Set a CAM mask
+ *     @regs: register block for this velocity
+ *     @mask: CAM mask to load
+ *
+ *     Store a new mask into a CAM
+ */
+static void mac_set_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
+{
+       int i;
+       /* Select CAM mask */
+       BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
+
+       writeb(CAMADDR_CAMEN, &regs->CAMADDR);
+
+       for (i = 0; i < 8; i++)
+               writeb(*mask++, &(regs->MARCAM[i]));
+
+       /* disable CAMEN */
+       writeb(0, &regs->CAMADDR);
+
+       /* Select mar */
+       BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
+}
+
+static void mac_set_vlan_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
+{
+       int i;
+       /* Select CAM mask */
+       BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
+
+       writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL, &regs->CAMADDR);
+
+       for (i = 0; i < 8; i++)
+               writeb(*mask++, &(regs->MARCAM[i]));
+
+       /* disable CAMEN */
+       writeb(0, &regs->CAMADDR);
+
+       /* Select mar */
+       BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
+}
+
+/**
+ *     mac_set_cam     -       set CAM data
+ *     @regs: register block of this velocity
+ *     @idx: Cam index
+ *     @addr: 2 or 6 bytes of CAM data
+ *
+ *     Load an address or vlan tag into a CAM
+ */
+static void mac_set_cam(struct mac_regs __iomem *regs, int idx, const u8 *addr)
+{
+       int i;
+
+       /* Select CAM mask */
+       BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
+
+       idx &= (64 - 1);
+
+       writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
+
+       for (i = 0; i < 6; i++)
+               writeb(*addr++, &(regs->MARCAM[i]));
+
+       BYTE_REG_BITS_ON(CAMCR_CAMWR, &regs->CAMCR);
+
+       udelay(10);
+
+       writeb(0, &regs->CAMADDR);
+
+       /* Select mar */
+       BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
+}
+
+static void mac_set_vlan_cam(struct mac_regs __iomem *regs, int idx,
+                            const u8 *addr)
+{
+
+       /* Select CAM mask */
+       BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
+
+       idx &= (64 - 1);
+
+       writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx, &regs->CAMADDR);
+       writew(*((u16 *) addr), &regs->MARCAM[0]);
+
+       BYTE_REG_BITS_ON(CAMCR_CAMWR, &regs->CAMCR);
+
+       udelay(10);
+
+       writeb(0, &regs->CAMADDR);
+
+       /* Select mar */
+       BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
+}
+
+
+/**
+ *     mac_wol_reset   -       reset WOL after exiting low power
+ *     @regs: register block of this velocity
+ *
+ *     Called after we drop out of wake on lan mode in order to
+ *     reset the Wake on lan features. This function doesn't restore
+ *     the rest of the logic from the result of sleep/wakeup
+ */
+static void mac_wol_reset(struct mac_regs __iomem *regs)
+{
+
+       /* Turn off SWPTAG right after leaving power mode */
+       BYTE_REG_BITS_OFF(STICKHW_SWPTAG, &regs->STICKHW);
+       /* clear sticky bits */
+       BYTE_REG_BITS_OFF((STICKHW_DS1 | STICKHW_DS0), &regs->STICKHW);
+
+       BYTE_REG_BITS_OFF(CHIPGCR_FCGMII, &regs->CHIPGCR);
+       BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, &regs->CHIPGCR);
+       /* disable force PME-enable */
+       writeb(WOLCFG_PMEOVR, &regs->WOLCFGClr);
+       /* disable power-event config bit */
+       writew(0xFFFF, &regs->WOLCRClr);
+       /* clear power status */
+       writew(0xFFFF, &regs->WOLSRClr);
+}
+
+static const struct ethtool_ops velocity_ethtool_ops;
+
+/*
+    Define module options
+*/
+
+MODULE_AUTHOR("VIA Networking Technologies, Inc.");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("VIA Networking Velocity Family Gigabit Ethernet Adapter Driver");
+
+#define VELOCITY_PARAM(N, D) \
+       static int N[MAX_UNITS] = OPTION_DEFAULT;\
+       module_param_array(N, int, NULL, 0); \
+       MODULE_PARM_DESC(N, D);
+
+#define RX_DESC_MIN     64
+#define RX_DESC_MAX     255
+#define RX_DESC_DEF     64
+VELOCITY_PARAM(RxDescriptors, "Number of receive descriptors");
+
+#define TX_DESC_MIN     16
+#define TX_DESC_MAX     256
+#define TX_DESC_DEF     64
+VELOCITY_PARAM(TxDescriptors, "Number of transmit descriptors");
+
+#define RX_THRESH_MIN   0
+#define RX_THRESH_MAX   3
+#define RX_THRESH_DEF   0
+/* rx_thresh[] is used for controlling the receive fifo threshold.
+   0: indicate the rxfifo threshold is 128 bytes.
+   1: indicate the rxfifo threshold is 512 bytes.
+   2: indicate the rxfifo threshold is 1024 bytes.
+   3: indicate the rxfifo threshold is store & forward.
+*/
+VELOCITY_PARAM(rx_thresh, "Receive fifo threshold");
+
+#define DMA_LENGTH_MIN  0
+#define DMA_LENGTH_MAX  7
+#define DMA_LENGTH_DEF  6
+
+/* DMA_length[] is used for controlling the DMA length
+   0: 8 DWORDs
+   1: 16 DWORDs
+   2: 32 DWORDs
+   3: 64 DWORDs
+   4: 128 DWORDs
+   5: 256 DWORDs
+   6: SF(flush till emply)
+   7: SF(flush till emply)
+*/
+VELOCITY_PARAM(DMA_length, "DMA length");
+
+#define IP_ALIG_DEF     0
+/* IP_byte_align[] is used for IP header DWORD byte aligned
+   0: indicate the IP header won't be DWORD byte aligned.(Default) .
+   1: indicate the IP header will be DWORD byte aligned.
+      In some environment, the IP header should be DWORD byte aligned,
+      or the packet will be droped when we receive it. (eg: IPVS)
+*/
+VELOCITY_PARAM(IP_byte_align, "Enable IP header dword aligned");
+
+#define FLOW_CNTL_DEF   1
+#define FLOW_CNTL_MIN   1
+#define FLOW_CNTL_MAX   5
+
+/* flow_control[] is used for setting the flow control ability of NIC.
+   1: hardware deafult - AUTO (default). Use Hardware default value in ANAR.
+   2: enable TX flow control.
+   3: enable RX flow control.
+   4: enable RX/TX flow control.
+   5: disable
+*/
+VELOCITY_PARAM(flow_control, "Enable flow control ability");
+
+#define MED_LNK_DEF 0
+#define MED_LNK_MIN 0
+#define MED_LNK_MAX 5
+/* speed_duplex[] is used for setting the speed and duplex mode of NIC.
+   0: indicate autonegotiation for both speed and duplex mode
+   1: indicate 100Mbps half duplex mode
+   2: indicate 100Mbps full duplex mode
+   3: indicate 10Mbps half duplex mode
+   4: indicate 10Mbps full duplex mode
+   5: indicate 1000Mbps full duplex mode
+
+   Note:
+   if EEPROM have been set to the force mode, this option is ignored
+   by driver.
+*/
+VELOCITY_PARAM(speed_duplex, "Setting the speed and duplex mode");
+
+#define VAL_PKT_LEN_DEF     0
+/* ValPktLen[] is used for setting the checksum offload ability of NIC.
+   0: Receive frame with invalid layer 2 length (Default)
+   1: Drop frame with invalid layer 2 length
+*/
+VELOCITY_PARAM(ValPktLen, "Receiving or Drop invalid 802.3 frame");
+
+#define WOL_OPT_DEF     0
+#define WOL_OPT_MIN     0
+#define WOL_OPT_MAX     7
+/* wol_opts[] is used for controlling wake on lan behavior.
+   0: Wake up if recevied a magic packet. (Default)
+   1: Wake up if link status is on/off.
+   2: Wake up if recevied an arp packet.
+   4: Wake up if recevied any unicast packet.
+   Those value can be sumed up to support more than one option.
+*/
+VELOCITY_PARAM(wol_opts, "Wake On Lan options");
+
+static int rx_copybreak = 200;
+module_param(rx_copybreak, int, 0644);
+MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
+
+/*
+ *     Internal board variants. At the moment we have only one
+ */
+static struct velocity_info_tbl chip_info_table[] = {
+       {CHIP_TYPE_VT6110, "VIA Networking Velocity Family Gigabit Ethernet Adapter", 1, 0x00FFFFFFUL},
+       { }
+};
+
+/*
+ *     Describe the PCI device identifiers that we support in this
+ *     device driver. Used for hotplug autoloading.
+ */
+static DEFINE_PCI_DEVICE_TABLE(velocity_id_table) = {
+       { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X) },
+       { }
+};
+
+MODULE_DEVICE_TABLE(pci, velocity_id_table);
+
+/**
+ *     get_chip_name   -       identifier to name
+ *     @id: chip identifier
+ *
+ *     Given a chip identifier return a suitable description. Returns
+ *     a pointer a static string valid while the driver is loaded.
+ */
+static const char __devinit *get_chip_name(enum chip_type chip_id)
+{
+       int i;
+       for (i = 0; chip_info_table[i].name != NULL; i++)
+               if (chip_info_table[i].chip_id == chip_id)
+                       break;
+       return chip_info_table[i].name;
+}
+
+/**
+ *     velocity_remove1        -       device unplug
+ *     @pdev: PCI device being removed
+ *
+ *     Device unload callback. Called on an unplug or on module
+ *     unload for each active device that is present. Disconnects
+ *     the device from the network layer and frees all the resources
+ */
+static void __devexit velocity_remove1(struct pci_dev *pdev)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct velocity_info *vptr = netdev_priv(dev);
+
+       unregister_netdev(dev);
+       iounmap(vptr->mac_regs);
+       pci_release_regions(pdev);
+       pci_disable_device(pdev);
+       pci_set_drvdata(pdev, NULL);
+       free_netdev(dev);
+
+       velocity_nics--;
+}
+
+/**
+ *     velocity_set_int_opt    -       parser for integer options
+ *     @opt: pointer to option value
+ *     @val: value the user requested (or -1 for default)
+ *     @min: lowest value allowed
+ *     @max: highest value allowed
+ *     @def: default value
+ *     @name: property name
+ *     @dev: device name
+ *
+ *     Set an integer property in the module options. This function does
+ *     all the verification and checking as well as reporting so that
+ *     we don't duplicate code for each option.
+ */
+static void __devinit velocity_set_int_opt(int *opt, int val, int min, int max, int def, char *name, const char *devname)
+{
+       if (val == -1)
+               *opt = def;
+       else if (val < min || val > max) {
+               VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (%d-%d)\n",
+                                       devname, name, min, max);
+               *opt = def;
+       } else {
+               VELOCITY_PRT(MSG_LEVEL_INFO, KERN_INFO "%s: set value of parameter %s to %d\n",
+                                       devname, name, val);
+               *opt = val;
+       }
+}
+
+/**
+ *     velocity_set_bool_opt   -       parser for boolean options
+ *     @opt: pointer to option value
+ *     @val: value the user requested (or -1 for default)
+ *     @def: default value (yes/no)
+ *     @flag: numeric value to set for true.
+ *     @name: property name
+ *     @dev: device name
+ *
+ *     Set a boolean property in the module options. This function does
+ *     all the verification and checking as well as reporting so that
+ *     we don't duplicate code for each option.
+ */
+static void __devinit velocity_set_bool_opt(u32 *opt, int val, int def, u32 flag, char *name, const char *devname)
+{
+       (*opt) &= (~flag);
+       if (val == -1)
+               *opt |= (def ? flag : 0);
+       else if (val < 0 || val > 1) {
+               printk(KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (0-1)\n",
+                       devname, name);
+               *opt |= (def ? flag : 0);
+       } else {
+               printk(KERN_INFO "%s: set parameter %s to %s\n",
+                       devname, name, val ? "TRUE" : "FALSE");
+               *opt |= (val ? flag : 0);
+       }
+}
+
+/**
+ *     velocity_get_options    -       set options on device
+ *     @opts: option structure for the device
+ *     @index: index of option to use in module options array
+ *     @devname: device name
+ *
+ *     Turn the module and command options into a single structure
+ *     for the current device
+ */
+static void __devinit velocity_get_options(struct velocity_opt *opts, int index, const char *devname)
+{
+
+       velocity_set_int_opt(&opts->rx_thresh, rx_thresh[index], RX_THRESH_MIN, RX_THRESH_MAX, RX_THRESH_DEF, "rx_thresh", devname);
+       velocity_set_int_opt(&opts->DMA_length, DMA_length[index], DMA_LENGTH_MIN, DMA_LENGTH_MAX, DMA_LENGTH_DEF, "DMA_length", devname);
+       velocity_set_int_opt(&opts->numrx, RxDescriptors[index], RX_DESC_MIN, RX_DESC_MAX, RX_DESC_DEF, "RxDescriptors", devname);
+       velocity_set_int_opt(&opts->numtx, TxDescriptors[index], TX_DESC_MIN, TX_DESC_MAX, TX_DESC_DEF, "TxDescriptors", devname);
+
+       velocity_set_int_opt(&opts->flow_cntl, flow_control[index], FLOW_CNTL_MIN, FLOW_CNTL_MAX, FLOW_CNTL_DEF, "flow_control", devname);
+       velocity_set_bool_opt(&opts->flags, IP_byte_align[index], IP_ALIG_DEF, VELOCITY_FLAGS_IP_ALIGN, "IP_byte_align", devname);
+       velocity_set_bool_opt(&opts->flags, ValPktLen[index], VAL_PKT_LEN_DEF, VELOCITY_FLAGS_VAL_PKT_LEN, "ValPktLen", devname);
+       velocity_set_int_opt((int *) &opts->spd_dpx, speed_duplex[index], MED_LNK_MIN, MED_LNK_MAX, MED_LNK_DEF, "Media link mode", devname);
+       velocity_set_int_opt((int *) &opts->wol_opts, wol_opts[index], WOL_OPT_MIN, WOL_OPT_MAX, WOL_OPT_DEF, "Wake On Lan options", devname);
+       opts->numrx = (opts->numrx & ~3);
+}
+
+/**
+ *     velocity_init_cam_filter        -       initialise CAM
+ *     @vptr: velocity to program
+ *
+ *     Initialize the content addressable memory used for filters. Load
+ *     appropriately according to the presence of VLAN
+ */
+static void velocity_init_cam_filter(struct velocity_info *vptr)
+{
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+       unsigned int vid, i = 0;
+
+       /* Turn on MCFG_PQEN, turn off MCFG_RTGOPT */
+       WORD_REG_BITS_SET(MCFG_PQEN, MCFG_RTGOPT, &regs->MCFG);
+       WORD_REG_BITS_ON(MCFG_VIDFR, &regs->MCFG);
+
+       /* Disable all CAMs */
+       memset(vptr->vCAMmask, 0, sizeof(u8) * 8);
+       memset(vptr->mCAMmask, 0, sizeof(u8) * 8);
+       mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
+       mac_set_cam_mask(regs, vptr->mCAMmask);
+
+       /* Enable VCAMs */
+
+       if (test_bit(0, vptr->active_vlans))
+               WORD_REG_BITS_ON(MCFG_RTGOPT, &regs->MCFG);
+
+       for_each_set_bit(vid, vptr->active_vlans, VLAN_N_VID) {
+               mac_set_vlan_cam(regs, i, (u8 *) &vid);
+               vptr->vCAMmask[i / 8] |= 0x1 << (i % 8);
+               if (++i >= VCAM_SIZE)
+                       break;
+       }
+       mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
+}
+
+static void velocity_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+
+       spin_lock_irq(&vptr->lock);
+       set_bit(vid, vptr->active_vlans);
+       velocity_init_cam_filter(vptr);
+       spin_unlock_irq(&vptr->lock);
+}
+
+static void velocity_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+
+       spin_lock_irq(&vptr->lock);
+       clear_bit(vid, vptr->active_vlans);
+       velocity_init_cam_filter(vptr);
+       spin_unlock_irq(&vptr->lock);
+}
+
+static void velocity_init_rx_ring_indexes(struct velocity_info *vptr)
+{
+       vptr->rx.dirty = vptr->rx.filled = vptr->rx.curr = 0;
+}
+
+/**
+ *     velocity_rx_reset       -       handle a receive reset
+ *     @vptr: velocity we are resetting
+ *
+ *     Reset the ownership and status for the receive ring side.
+ *     Hand all the receive queue to the NIC.
+ */
+static void velocity_rx_reset(struct velocity_info *vptr)
+{
+
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+       int i;
+
+       velocity_init_rx_ring_indexes(vptr);
+
+       /*
+        *      Init state, all RD entries belong to the NIC
+        */
+       for (i = 0; i < vptr->options.numrx; ++i)
+               vptr->rx.ring[i].rdesc0.len |= OWNED_BY_NIC;
+
+       writew(vptr->options.numrx, &regs->RBRDU);
+       writel(vptr->rx.pool_dma, &regs->RDBaseLo);
+       writew(0, &regs->RDIdx);
+       writew(vptr->options.numrx - 1, &regs->RDCSize);
+}
+
+/**
+ *     velocity_get_opt_media_mode     -       get media selection
+ *     @vptr: velocity adapter
+ *
+ *     Get the media mode stored in EEPROM or module options and load
+ *     mii_status accordingly. The requested link state information
+ *     is also returned.
+ */
+static u32 velocity_get_opt_media_mode(struct velocity_info *vptr)
+{
+       u32 status = 0;
+
+       switch (vptr->options.spd_dpx) {
+       case SPD_DPX_AUTO:
+               status = VELOCITY_AUTONEG_ENABLE;
+               break;
+       case SPD_DPX_100_FULL:
+               status = VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL;
+               break;
+       case SPD_DPX_10_FULL:
+               status = VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL;
+               break;
+       case SPD_DPX_100_HALF:
+               status = VELOCITY_SPEED_100;
+               break;
+       case SPD_DPX_10_HALF:
+               status = VELOCITY_SPEED_10;
+               break;
+       case SPD_DPX_1000_FULL:
+               status = VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
+               break;
+       }
+       vptr->mii_status = status;
+       return status;
+}
+
+/**
+ *     safe_disable_mii_autopoll       -       autopoll off
+ *     @regs: velocity registers
+ *
+ *     Turn off the autopoll and wait for it to disable on the chip
+ */
+static void safe_disable_mii_autopoll(struct mac_regs __iomem *regs)
+{
+       u16 ww;
+
+       /*  turn off MAUTO */
+       writeb(0, &regs->MIICR);
+       for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
+               udelay(1);
+               if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, &regs->MIISR))
+                       break;
+       }
+}
+
+/**
+ *     enable_mii_autopoll     -       turn on autopolling
+ *     @regs: velocity registers
+ *
+ *     Enable the MII link status autopoll feature on the Velocity
+ *     hardware. Wait for it to enable.
+ */
+static void enable_mii_autopoll(struct mac_regs __iomem *regs)
+{
+       int ii;
+
+       writeb(0, &(regs->MIICR));
+       writeb(MIIADR_SWMPL, &regs->MIIADR);
+
+       for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
+               udelay(1);
+               if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, &regs->MIISR))
+                       break;
+       }
+
+       writeb(MIICR_MAUTO, &regs->MIICR);
+
+       for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
+               udelay(1);
+               if (!BYTE_REG_BITS_IS_ON(MIISR_MIDLE, &regs->MIISR))
+                       break;
+       }
+
+}
+
+/**
+ *     velocity_mii_read       -       read MII data
+ *     @regs: velocity registers
+ *     @index: MII register index
+ *     @data: buffer for received data
+ *
+ *     Perform a single read of an MII 16bit register. Returns zero
+ *     on success or -ETIMEDOUT if the PHY did not respond.
+ */
+static int velocity_mii_read(struct mac_regs __iomem *regs, u8 index, u16 *data)
+{
+       u16 ww;
+
+       /*
+        *      Disable MIICR_MAUTO, so that mii addr can be set normally
+        */
+       safe_disable_mii_autopoll(regs);
+
+       writeb(index, &regs->MIIADR);
+
+       BYTE_REG_BITS_ON(MIICR_RCMD, &regs->MIICR);
+
+       for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
+               if (!(readb(&regs->MIICR) & MIICR_RCMD))
+                       break;
+       }
+
+       *data = readw(&regs->MIIDATA);
+
+       enable_mii_autopoll(regs);
+       if (ww == W_MAX_TIMEOUT)
+               return -ETIMEDOUT;
+       return 0;
+}
+
+/**
+ *     mii_check_media_mode    -       check media state
+ *     @regs: velocity registers
+ *
+ *     Check the current MII status and determine the link status
+ *     accordingly
+ */
+static u32 mii_check_media_mode(struct mac_regs __iomem *regs)
+{
+       u32 status = 0;
+       u16 ANAR;
+
+       if (!MII_REG_BITS_IS_ON(BMSR_LSTATUS, MII_BMSR, regs))
+               status |= VELOCITY_LINK_FAIL;
+
+       if (MII_REG_BITS_IS_ON(ADVERTISE_1000FULL, MII_CTRL1000, regs))
+               status |= VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
+       else if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF, MII_CTRL1000, regs))
+               status |= (VELOCITY_SPEED_1000);
+       else {
+               velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
+               if (ANAR & ADVERTISE_100FULL)
+                       status |= (VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL);
+               else if (ANAR & ADVERTISE_100HALF)
+                       status |= VELOCITY_SPEED_100;
+               else if (ANAR & ADVERTISE_10FULL)
+                       status |= (VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL);
+               else
+                       status |= (VELOCITY_SPEED_10);
+       }
+
+       if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) {
+               velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
+               if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF))
+                   == (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) {
+                       if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
+                               status |= VELOCITY_AUTONEG_ENABLE;
+               }
+       }
+
+       return status;
+}
+
+/**
+ *     velocity_mii_write      -       write MII data
+ *     @regs: velocity registers
+ *     @index: MII register index
+ *     @data: 16bit data for the MII register
+ *
+ *     Perform a single write to an MII 16bit register. Returns zero
+ *     on success or -ETIMEDOUT if the PHY did not respond.
+ */
+static int velocity_mii_write(struct mac_regs __iomem *regs, u8 mii_addr, u16 data)
+{
+       u16 ww;
+
+       /*
+        *      Disable MIICR_MAUTO, so that mii addr can be set normally
+        */
+       safe_disable_mii_autopoll(regs);
+
+       /* MII reg offset */
+       writeb(mii_addr, &regs->MIIADR);
+       /* set MII data */
+       writew(data, &regs->MIIDATA);
+
+       /* turn on MIICR_WCMD */
+       BYTE_REG_BITS_ON(MIICR_WCMD, &regs->MIICR);
+
+       /* W_MAX_TIMEOUT is the timeout period */
+       for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
+               udelay(5);
+               if (!(readb(&regs->MIICR) & MIICR_WCMD))
+                       break;
+       }
+       enable_mii_autopoll(regs);
+
+       if (ww == W_MAX_TIMEOUT)
+               return -ETIMEDOUT;
+       return 0;
+}
+
+/**
+ *     set_mii_flow_control    -       flow control setup
+ *     @vptr: velocity interface
+ *
+ *     Set up the flow control on this interface according to
+ *     the supplied user/eeprom options.
+ */
+static void set_mii_flow_control(struct velocity_info *vptr)
+{
+       /*Enable or Disable PAUSE in ANAR */
+       switch (vptr->options.flow_cntl) {
+       case FLOW_CNTL_TX:
+               MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
+               MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
+               break;
+
+       case FLOW_CNTL_RX:
+               MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
+               MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
+               break;
+
+       case FLOW_CNTL_TX_RX:
+               MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
+               MII_REG_BITS_OFF(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
+               break;
+
+       case FLOW_CNTL_DISABLE:
+               MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
+               MII_REG_BITS_OFF(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
+               break;
+       default:
+               break;
+       }
+}
+
+/**
+ *     mii_set_auto_on         -       autonegotiate on
+ *     @vptr: velocity
+ *
+ *     Enable autonegotation on this interface
+ */
+static void mii_set_auto_on(struct velocity_info *vptr)
+{
+       if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs))
+               MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
+       else
+               MII_REG_BITS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs);
+}
+
+static u32 check_connection_type(struct mac_regs __iomem *regs)
+{
+       u32 status = 0;
+       u8 PHYSR0;
+       u16 ANAR;
+       PHYSR0 = readb(&regs->PHYSR0);
+
+       /*
+          if (!(PHYSR0 & PHYSR0_LINKGD))
+          status|=VELOCITY_LINK_FAIL;
+        */
+
+       if (PHYSR0 & PHYSR0_FDPX)
+               status |= VELOCITY_DUPLEX_FULL;
+
+       if (PHYSR0 & PHYSR0_SPDG)
+               status |= VELOCITY_SPEED_1000;
+       else if (PHYSR0 & PHYSR0_SPD10)
+               status |= VELOCITY_SPEED_10;
+       else
+               status |= VELOCITY_SPEED_100;
+
+       if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) {
+               velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
+               if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF))
+                   == (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) {
+                       if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
+                               status |= VELOCITY_AUTONEG_ENABLE;
+               }
+       }
+
+       return status;
+}
+
+/**
+ *     velocity_set_media_mode         -       set media mode
+ *     @mii_status: old MII link state
+ *
+ *     Check the media link state and configure the flow control
+ *     PHY and also velocity hardware setup accordingly. In particular
+ *     we need to set up CD polling and frame bursting.
+ */
+static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status)
+{
+       u32 curr_status;
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+
+       vptr->mii_status = mii_check_media_mode(vptr->mac_regs);
+       curr_status = vptr->mii_status & (~VELOCITY_LINK_FAIL);
+
+       /* Set mii link status */
+       set_mii_flow_control(vptr);
+
+       /*
+          Check if new status is consistent with current status
+          if (((mii_status & curr_status) & VELOCITY_AUTONEG_ENABLE) ||
+              (mii_status==curr_status)) {
+          vptr->mii_status=mii_check_media_mode(vptr->mac_regs);
+          vptr->mii_status=check_connection_type(vptr->mac_regs);
+          VELOCITY_PRT(MSG_LEVEL_INFO, "Velocity link no change\n");
+          return 0;
+          }
+        */
+
+       if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
+               MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
+
+       /*
+        *      If connection type is AUTO
+        */
+       if (mii_status & VELOCITY_AUTONEG_ENABLE) {
+               VELOCITY_PRT(MSG_LEVEL_INFO, "Velocity is AUTO mode\n");
+               /* clear force MAC mode bit */
+               BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, &regs->CHIPGCR);
+               /* set duplex mode of MAC according to duplex mode of MII */
+               MII_REG_BITS_ON(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF, MII_ADVERTISE, vptr->mac_regs);
+               MII_REG_BITS_ON(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
+               MII_REG_BITS_ON(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs);
+
+               /* enable AUTO-NEGO mode */
+               mii_set_auto_on(vptr);
+       } else {
+               u16 CTRL1000;
+               u16 ANAR;
+               u8 CHIPGCR;
+
+               /*
+                * 1. if it's 3119, disable frame bursting in halfduplex mode
+                *    and enable it in fullduplex mode
+                * 2. set correct MII/GMII and half/full duplex mode in CHIPGCR
+                * 3. only enable CD heart beat counter in 10HD mode
+                */
+
+               /* set force MAC mode bit */
+               BYTE_REG_BITS_ON(CHIPGCR_FCMODE, &regs->CHIPGCR);
+
+               CHIPGCR = readb(&regs->CHIPGCR);
+
+               if (mii_status & VELOCITY_SPEED_1000)
+                       CHIPGCR |= CHIPGCR_FCGMII;
+               else
+                       CHIPGCR &= ~CHIPGCR_FCGMII;
+
+               if (mii_status & VELOCITY_DUPLEX_FULL) {
+                       CHIPGCR |= CHIPGCR_FCFDX;
+                       writeb(CHIPGCR, &regs->CHIPGCR);
+                       VELOCITY_PRT(MSG_LEVEL_INFO, "set Velocity to forced full mode\n");
+                       if (vptr->rev_id < REV_ID_VT3216_A0)
+                               BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR);
+               } else {
+                       CHIPGCR &= ~CHIPGCR_FCFDX;
+                       VELOCITY_PRT(MSG_LEVEL_INFO, "set Velocity to forced half mode\n");
+                       writeb(CHIPGCR, &regs->CHIPGCR);
+                       if (vptr->rev_id < REV_ID_VT3216_A0)
+                               BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR);
+               }
+
+               velocity_mii_read(vptr->mac_regs, MII_CTRL1000, &CTRL1000);
+               CTRL1000 &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
+               if ((mii_status & VELOCITY_SPEED_1000) &&
+                   (mii_status & VELOCITY_DUPLEX_FULL)) {
+                       CTRL1000 |= ADVERTISE_1000FULL;
+               }
+               velocity_mii_write(vptr->mac_regs, MII_CTRL1000, CTRL1000);
+
+               if (!(mii_status & VELOCITY_DUPLEX_FULL) && (mii_status & VELOCITY_SPEED_10))
+                       BYTE_REG_BITS_OFF(TESTCFG_HBDIS, &regs->TESTCFG);
+               else
+                       BYTE_REG_BITS_ON(TESTCFG_HBDIS, &regs->TESTCFG);
+
+               /* MII_REG_BITS_OFF(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs); */
+               velocity_mii_read(vptr->mac_regs, MII_ADVERTISE, &ANAR);
+               ANAR &= (~(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF));
+               if (mii_status & VELOCITY_SPEED_100) {
+                       if (mii_status & VELOCITY_DUPLEX_FULL)
+                               ANAR |= ADVERTISE_100FULL;
+                       else
+                               ANAR |= ADVERTISE_100HALF;
+               } else if (mii_status & VELOCITY_SPEED_10) {
+                       if (mii_status & VELOCITY_DUPLEX_FULL)
+                               ANAR |= ADVERTISE_10FULL;
+                       else
+                               ANAR |= ADVERTISE_10HALF;
+               }
+               velocity_mii_write(vptr->mac_regs, MII_ADVERTISE, ANAR);
+               /* enable AUTO-NEGO mode */
+               mii_set_auto_on(vptr);
+               /* MII_REG_BITS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs); */
+       }
+       /* vptr->mii_status=mii_check_media_mode(vptr->mac_regs); */
+       /* vptr->mii_status=check_connection_type(vptr->mac_regs); */
+       return VELOCITY_LINK_CHANGE;
+}
+
+/**
+ *     velocity_print_link_status      -       link status reporting
+ *     @vptr: velocity to report on
+ *
+ *     Turn the link status of the velocity card into a kernel log
+ *     description of the new link state, detailing speed and duplex
+ *     status
+ */
+static void velocity_print_link_status(struct velocity_info *vptr)
+{
+
+       if (vptr->mii_status & VELOCITY_LINK_FAIL) {
+               VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->dev->name);
+       } else if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
+               VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->dev->name);
+
+               if (vptr->mii_status & VELOCITY_SPEED_1000)
+                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps");
+               else if (vptr->mii_status & VELOCITY_SPEED_100)
+                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps");
+               else
+                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps");
+
+               if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
+                       VELOCITY_PRT(MSG_LEVEL_INFO, " full duplex\n");
+               else
+                       VELOCITY_PRT(MSG_LEVEL_INFO, " half duplex\n");
+       } else {
+               VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->dev->name);
+               switch (vptr->options.spd_dpx) {
+               case SPD_DPX_1000_FULL:
+                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps full duplex\n");
+                       break;
+               case SPD_DPX_100_HALF:
+                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps half duplex\n");
+                       break;
+               case SPD_DPX_100_FULL:
+                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps full duplex\n");
+                       break;
+               case SPD_DPX_10_HALF:
+                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps half duplex\n");
+                       break;
+               case SPD_DPX_10_FULL:
+                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps full duplex\n");
+                       break;
+               default:
+                       break;
+               }
+       }
+}
+
+/**
+ *     enable_flow_control_ability     -       flow control
+ *     @vptr: veloity to configure
+ *
+ *     Set up flow control according to the flow control options
+ *     determined by the eeprom/configuration.
+ */
+static void enable_flow_control_ability(struct velocity_info *vptr)
+{
+
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+
+       switch (vptr->options.flow_cntl) {
+
+       case FLOW_CNTL_DEFAULT:
+               if (BYTE_REG_BITS_IS_ON(PHYSR0_RXFLC, &regs->PHYSR0))
+                       writel(CR0_FDXRFCEN, &regs->CR0Set);
+               else
+                       writel(CR0_FDXRFCEN, &regs->CR0Clr);
+
+               if (BYTE_REG_BITS_IS_ON(PHYSR0_TXFLC, &regs->PHYSR0))
+                       writel(CR0_FDXTFCEN, &regs->CR0Set);
+               else
+                       writel(CR0_FDXTFCEN, &regs->CR0Clr);
+               break;
+
+       case FLOW_CNTL_TX:
+               writel(CR0_FDXTFCEN, &regs->CR0Set);
+               writel(CR0_FDXRFCEN, &regs->CR0Clr);
+               break;
+
+       case FLOW_CNTL_RX:
+               writel(CR0_FDXRFCEN, &regs->CR0Set);
+               writel(CR0_FDXTFCEN, &regs->CR0Clr);
+               break;
+
+       case FLOW_CNTL_TX_RX:
+               writel(CR0_FDXTFCEN, &regs->CR0Set);
+               writel(CR0_FDXRFCEN, &regs->CR0Set);
+               break;
+
+       case FLOW_CNTL_DISABLE:
+               writel(CR0_FDXRFCEN, &regs->CR0Clr);
+               writel(CR0_FDXTFCEN, &regs->CR0Clr);
+               break;
+
+       default:
+               break;
+       }
+
+}
+
+/**
+ *     velocity_soft_reset     -       soft reset
+ *     @vptr: velocity to reset
+ *
+ *     Kick off a soft reset of the velocity adapter and then poll
+ *     until the reset sequence has completed before returning.
+ */
+static int velocity_soft_reset(struct velocity_info *vptr)
+{
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+       int i = 0;
+
+       writel(CR0_SFRST, &regs->CR0Set);
+
+       for (i = 0; i < W_MAX_TIMEOUT; i++) {
+               udelay(5);
+               if (!DWORD_REG_BITS_IS_ON(CR0_SFRST, &regs->CR0Set))
+                       break;
+       }
+
+       if (i == W_MAX_TIMEOUT) {
+               writel(CR0_FORSRST, &regs->CR0Set);
+               /* FIXME: PCI POSTING */
+               /* delay 2ms */
+               mdelay(2);
+       }
+       return 0;
+}
+
+/**
+ *     velocity_set_multi      -       filter list change callback
+ *     @dev: network device
+ *
+ *     Called by the network layer when the filter lists need to change
+ *     for a velocity adapter. Reload the CAMs with the new address
+ *     filter ruleset.
+ */
+static void velocity_set_multi(struct net_device *dev)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+       u8 rx_mode;
+       int i;
+       struct netdev_hw_addr *ha;
+
+       if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
+               writel(0xffffffff, &regs->MARCAM[0]);
+               writel(0xffffffff, &regs->MARCAM[4]);
+               rx_mode = (RCR_AM | RCR_AB | RCR_PROM);
+       } else if ((netdev_mc_count(dev) > vptr->multicast_limit) ||
+                  (dev->flags & IFF_ALLMULTI)) {
+               writel(0xffffffff, &regs->MARCAM[0]);
+               writel(0xffffffff, &regs->MARCAM[4]);
+               rx_mode = (RCR_AM | RCR_AB);
+       } else {
+               int offset = MCAM_SIZE - vptr->multicast_limit;
+               mac_get_cam_mask(regs, vptr->mCAMmask);
+
+               i = 0;
+               netdev_for_each_mc_addr(ha, dev) {
+                       mac_set_cam(regs, i + offset, ha->addr);
+                       vptr->mCAMmask[(offset + i) / 8] |= 1 << ((offset + i) & 7);
+                       i++;
+               }
+
+               mac_set_cam_mask(regs, vptr->mCAMmask);
+               rx_mode = RCR_AM | RCR_AB | RCR_AP;
+       }
+       if (dev->mtu > 1500)
+               rx_mode |= RCR_AL;
+
+       BYTE_REG_BITS_ON(rx_mode, &regs->RCR);
+
+}
+
+/*
+ * MII access , media link mode setting functions
+ */
+
+/**
+ *     mii_init        -       set up MII
+ *     @vptr: velocity adapter
+ *     @mii_status:  links tatus
+ *
+ *     Set up the PHY for the current link state.
+ */
+static void mii_init(struct velocity_info *vptr, u32 mii_status)
+{
+       u16 BMCR;
+
+       switch (PHYID_GET_PHY_ID(vptr->phy_id)) {
+       case PHYID_CICADA_CS8201:
+               /*
+                *      Reset to hardware default
+                */
+               MII_REG_BITS_OFF((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
+               /*
+                *      Turn on ECHODIS bit in NWay-forced full mode and turn it
+                *      off it in NWay-forced half mode for NWay-forced v.s.
+                *      legacy-forced issue.
+                */
+               if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
+                       MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
+               else
+                       MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
+               /*
+                *      Turn on Link/Activity LED enable bit for CIS8201
+                */
+               MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
+               break;
+       case PHYID_VT3216_32BIT:
+       case PHYID_VT3216_64BIT:
+               /*
+                *      Reset to hardware default
+                */
+               MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
+               /*
+                *      Turn on ECHODIS bit in NWay-forced full mode and turn it
+                *      off it in NWay-forced half mode for NWay-forced v.s.
+                *      legacy-forced issue
+                */
+               if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
+                       MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
+               else
+                       MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
+               break;
+
+       case PHYID_MARVELL_1000:
+       case PHYID_MARVELL_1000S:
+               /*
+                *      Assert CRS on Transmit
+                */
+               MII_REG_BITS_ON(PSCR_ACRSTX, MII_REG_PSCR, vptr->mac_regs);
+               /*
+                *      Reset to hardware default
+                */
+               MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
+               break;
+       default:
+               ;
+       }
+       velocity_mii_read(vptr->mac_regs, MII_BMCR, &BMCR);
+       if (BMCR & BMCR_ISOLATE) {
+               BMCR &= ~BMCR_ISOLATE;
+               velocity_mii_write(vptr->mac_regs, MII_BMCR, BMCR);
+       }
+}
+
+/**
+ * setup_queue_timers  -       Setup interrupt timers
+ *
+ * Setup interrupt frequency during suppression (timeout if the frame
+ * count isn't filled).
+ */
+static void setup_queue_timers(struct velocity_info *vptr)
+{
+       /* Only for newer revisions */
+       if (vptr->rev_id >= REV_ID_VT3216_A0) {
+               u8 txqueue_timer = 0;
+               u8 rxqueue_timer = 0;
+
+               if (vptr->mii_status & (VELOCITY_SPEED_1000 |
+                               VELOCITY_SPEED_100)) {
+                       txqueue_timer = vptr->options.txqueue_timer;
+                       rxqueue_timer = vptr->options.rxqueue_timer;
+               }
+
+               writeb(txqueue_timer, &vptr->mac_regs->TQETMR);
+               writeb(rxqueue_timer, &vptr->mac_regs->RQETMR);
+       }
+}
+
+/**
+ * setup_adaptive_interrupts  -  Setup interrupt suppression
+ *
+ * @vptr velocity adapter
+ *
+ * The velocity is able to suppress interrupt during high interrupt load.
+ * This function turns on that feature.
+ */
+static void setup_adaptive_interrupts(struct velocity_info *vptr)
+{
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+       u16 tx_intsup = vptr->options.tx_intsup;
+       u16 rx_intsup = vptr->options.rx_intsup;
+
+       /* Setup default interrupt mask (will be changed below) */
+       vptr->int_mask = INT_MASK_DEF;
+
+       /* Set Tx Interrupt Suppression Threshold */
+       writeb(CAMCR_PS0, &regs->CAMCR);
+       if (tx_intsup != 0) {
+               vptr->int_mask &= ~(ISR_PTXI | ISR_PTX0I | ISR_PTX1I |
+                               ISR_PTX2I | ISR_PTX3I);
+               writew(tx_intsup, &regs->ISRCTL);
+       } else
+               writew(ISRCTL_TSUPDIS, &regs->ISRCTL);
+
+       /* Set Rx Interrupt Suppression Threshold */
+       writeb(CAMCR_PS1, &regs->CAMCR);
+       if (rx_intsup != 0) {
+               vptr->int_mask &= ~ISR_PRXI;
+               writew(rx_intsup, &regs->ISRCTL);
+       } else
+               writew(ISRCTL_RSUPDIS, &regs->ISRCTL);
+
+       /* Select page to interrupt hold timer */
+       writeb(0, &regs->CAMCR);
+}
+
+/**
+ *     velocity_init_registers -       initialise MAC registers
+ *     @vptr: velocity to init
+ *     @type: type of initialisation (hot or cold)
+ *
+ *     Initialise the MAC on a reset or on first set up on the
+ *     hardware.
+ */
+static void velocity_init_registers(struct velocity_info *vptr,
+                                   enum velocity_init_type type)
+{
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+       int i, mii_status;
+
+       mac_wol_reset(regs);
+
+       switch (type) {
+       case VELOCITY_INIT_RESET:
+       case VELOCITY_INIT_WOL:
+
+               netif_stop_queue(vptr->dev);
+
+               /*
+                *      Reset RX to prevent RX pointer not on the 4X location
+                */
+               velocity_rx_reset(vptr);
+               mac_rx_queue_run(regs);
+               mac_rx_queue_wake(regs);
+
+               mii_status = velocity_get_opt_media_mode(vptr);
+               if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
+                       velocity_print_link_status(vptr);
+                       if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
+                               netif_wake_queue(vptr->dev);
+               }
+
+               enable_flow_control_ability(vptr);
+
+               mac_clear_isr(regs);
+               writel(CR0_STOP, &regs->CR0Clr);
+               writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT),
+                                                       &regs->CR0Set);
+
+               break;
+
+       case VELOCITY_INIT_COLD:
+       default:
+               /*
+                *      Do reset
+                */
+               velocity_soft_reset(vptr);
+               mdelay(5);
+
+               mac_eeprom_reload(regs);
+               for (i = 0; i < 6; i++)
+                       writeb(vptr->dev->dev_addr[i], &(regs->PAR[i]));
+
+               /*
+                *      clear Pre_ACPI bit.
+                */
+               BYTE_REG_BITS_OFF(CFGA_PACPI, &(regs->CFGA));
+               mac_set_rx_thresh(regs, vptr->options.rx_thresh);
+               mac_set_dma_length(regs, vptr->options.DMA_length);
+
+               writeb(WOLCFG_SAM | WOLCFG_SAB, &regs->WOLCFGSet);
+               /*
+                *      Back off algorithm use original IEEE standard
+                */
+               BYTE_REG_BITS_SET(CFGB_OFSET, (CFGB_CRANDOM | CFGB_CAP | CFGB_MBA | CFGB_BAKOPT), &regs->CFGB);
+
+               /*
+                *      Init CAM filter
+                */
+               velocity_init_cam_filter(vptr);
+
+               /*
+                *      Set packet filter: Receive directed and broadcast address
+                */
+               velocity_set_multi(vptr->dev);
+
+               /*
+                *      Enable MII auto-polling
+                */
+               enable_mii_autopoll(regs);
+
+               setup_adaptive_interrupts(vptr);
+
+               writel(vptr->rx.pool_dma, &regs->RDBaseLo);
+               writew(vptr->options.numrx - 1, &regs->RDCSize);
+               mac_rx_queue_run(regs);
+               mac_rx_queue_wake(regs);
+
+               writew(vptr->options.numtx - 1, &regs->TDCSize);
+
+               for (i = 0; i < vptr->tx.numq; i++) {
+                       writel(vptr->tx.pool_dma[i], &regs->TDBaseLo[i]);
+                       mac_tx_queue_run(regs, i);
+               }
+
+               init_flow_control_register(vptr);
+
+               writel(CR0_STOP, &regs->CR0Clr);
+               writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT), &regs->CR0Set);
+
+               mii_status = velocity_get_opt_media_mode(vptr);
+               netif_stop_queue(vptr->dev);
+
+               mii_init(vptr, mii_status);
+
+               if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
+                       velocity_print_link_status(vptr);
+                       if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
+                               netif_wake_queue(vptr->dev);
+               }
+
+               enable_flow_control_ability(vptr);
+               mac_hw_mibs_init(regs);
+               mac_write_int_mask(vptr->int_mask, regs);
+               mac_clear_isr(regs);
+
+       }
+}
+
+static void velocity_give_many_rx_descs(struct velocity_info *vptr)
+{
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+       int avail, dirty, unusable;
+
+       /*
+        * RD number must be equal to 4X per hardware spec
+        * (programming guide rev 1.20, p.13)
+        */
+       if (vptr->rx.filled < 4)
+               return;
+
+       wmb();
+
+       unusable = vptr->rx.filled & 0x0003;
+       dirty = vptr->rx.dirty - unusable;
+       for (avail = vptr->rx.filled & 0xfffc; avail; avail--) {
+               dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1;
+               vptr->rx.ring[dirty].rdesc0.len |= OWNED_BY_NIC;
+       }
+
+       writew(vptr->rx.filled & 0xfffc, &regs->RBRDU);
+       vptr->rx.filled = unusable;
+}
+
+/**
+ *     velocity_init_dma_rings -       set up DMA rings
+ *     @vptr: Velocity to set up
+ *
+ *     Allocate PCI mapped DMA rings for the receive and transmit layer
+ *     to use.
+ */
+static int velocity_init_dma_rings(struct velocity_info *vptr)
+{
+       struct velocity_opt *opt = &vptr->options;
+       const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc);
+       const unsigned int tx_ring_size = opt->numtx * sizeof(struct tx_desc);
+       struct pci_dev *pdev = vptr->pdev;
+       dma_addr_t pool_dma;
+       void *pool;
+       unsigned int i;
+
+       /*
+        * Allocate all RD/TD rings a single pool.
+        *
+        * pci_alloc_consistent() fulfills the requirement for 64 bytes
+        * alignment
+        */
+       pool = pci_alloc_consistent(pdev, tx_ring_size * vptr->tx.numq +
+                                   rx_ring_size, &pool_dma);
+       if (!pool) {
+               dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
+                       vptr->dev->name);
+               return -ENOMEM;
+       }
+
+       vptr->rx.ring = pool;
+       vptr->rx.pool_dma = pool_dma;
+
+       pool += rx_ring_size;
+       pool_dma += rx_ring_size;
+
+       for (i = 0; i < vptr->tx.numq; i++) {
+               vptr->tx.rings[i] = pool;
+               vptr->tx.pool_dma[i] = pool_dma;
+               pool += tx_ring_size;
+               pool_dma += tx_ring_size;
+       }
+
+       return 0;
+}
+
+static void velocity_set_rxbufsize(struct velocity_info *vptr, int mtu)
+{
+       vptr->rx.buf_sz = (mtu <= ETH_DATA_LEN) ? PKT_BUF_SZ : mtu + 32;
+}
+
+/**
+ *     velocity_alloc_rx_buf   -       allocate aligned receive buffer
+ *     @vptr: velocity
+ *     @idx: ring index
+ *
+ *     Allocate a new full sized buffer for the reception of a frame and
+ *     map it into PCI space for the hardware to use. The hardware
+ *     requires *64* byte alignment of the buffer which makes life
+ *     less fun than would be ideal.
+ */
+static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
+{
+       struct rx_desc *rd = &(vptr->rx.ring[idx]);
+       struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
+
+       rd_info->skb = dev_alloc_skb(vptr->rx.buf_sz + 64);
+       if (rd_info->skb == NULL)
+               return -ENOMEM;
+
+       /*
+        *      Do the gymnastics to get the buffer head for data at
+        *      64byte alignment.
+        */
+       skb_reserve(rd_info->skb,
+                       64 - ((unsigned long) rd_info->skb->data & 63));
+       rd_info->skb_dma = pci_map_single(vptr->pdev, rd_info->skb->data,
+                                       vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
+
+       /*
+        *      Fill in the descriptor to match
+        */
+
+       *((u32 *) & (rd->rdesc0)) = 0;
+       rd->size = cpu_to_le16(vptr->rx.buf_sz) | RX_INTEN;
+       rd->pa_low = cpu_to_le32(rd_info->skb_dma);
+       rd->pa_high = 0;
+       return 0;
+}
+
+
+static int velocity_rx_refill(struct velocity_info *vptr)
+{
+       int dirty = vptr->rx.dirty, done = 0;
+
+       do {
+               struct rx_desc *rd = vptr->rx.ring + dirty;
+
+               /* Fine for an all zero Rx desc at init time as well */
+               if (rd->rdesc0.len & OWNED_BY_NIC)
+                       break;
+
+               if (!vptr->rx.info[dirty].skb) {
+                       if (velocity_alloc_rx_buf(vptr, dirty) < 0)
+                               break;
+               }
+               done++;
+               dirty = (dirty < vptr->options.numrx - 1) ? dirty + 1 : 0;
+       } while (dirty != vptr->rx.curr);
+
+       if (done) {
+               vptr->rx.dirty = dirty;
+               vptr->rx.filled += done;
+       }
+
+       return done;
+}
+
+/**
+ *     velocity_free_rd_ring   -       free receive ring
+ *     @vptr: velocity to clean up
+ *
+ *     Free the receive buffers for each ring slot and any
+ *     attached socket buffers that need to go away.
+ */
+static void velocity_free_rd_ring(struct velocity_info *vptr)
+{
+       int i;
+
+       if (vptr->rx.info == NULL)
+               return;
+
+       for (i = 0; i < vptr->options.numrx; i++) {
+               struct velocity_rd_info *rd_info = &(vptr->rx.info[i]);
+               struct rx_desc *rd = vptr->rx.ring + i;
+
+               memset(rd, 0, sizeof(*rd));
+
+               if (!rd_info->skb)
+                       continue;
+               pci_unmap_single(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
+                                PCI_DMA_FROMDEVICE);
+               rd_info->skb_dma = 0;
+
+               dev_kfree_skb(rd_info->skb);
+               rd_info->skb = NULL;
+       }
+
+       kfree(vptr->rx.info);
+       vptr->rx.info = NULL;
+}
+
+/**
+ *     velocity_init_rd_ring   -       set up receive ring
+ *     @vptr: velocity to configure
+ *
+ *     Allocate and set up the receive buffers for each ring slot and
+ *     assign them to the network adapter.
+ */
+static int velocity_init_rd_ring(struct velocity_info *vptr)
+{
+       int ret = -ENOMEM;
+
+       vptr->rx.info = kcalloc(vptr->options.numrx,
+                               sizeof(struct velocity_rd_info), GFP_KERNEL);
+       if (!vptr->rx.info)
+               goto out;
+
+       velocity_init_rx_ring_indexes(vptr);
+
+       if (velocity_rx_refill(vptr) != vptr->options.numrx) {
+               VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR
+                       "%s: failed to allocate RX buffer.\n", vptr->dev->name);
+               velocity_free_rd_ring(vptr);
+               goto out;
+       }
+
+       ret = 0;
+out:
+       return ret;
+}
+
+/**
+ *     velocity_init_td_ring   -       set up transmit ring
+ *     @vptr:  velocity
+ *
+ *     Set up the transmit ring and chain the ring pointers together.
+ *     Returns zero on success or a negative posix errno code for
+ *     failure.
+ */
+static int velocity_init_td_ring(struct velocity_info *vptr)
+{
+       int j;
+
+       /* Init the TD ring entries */
+       for (j = 0; j < vptr->tx.numq; j++) {
+
+               vptr->tx.infos[j] = kcalloc(vptr->options.numtx,
+                                           sizeof(struct velocity_td_info),
+                                           GFP_KERNEL);
+               if (!vptr->tx.infos[j]) {
+                       while (--j >= 0)
+                               kfree(vptr->tx.infos[j]);
+                       return -ENOMEM;
+               }
+
+               vptr->tx.tail[j] = vptr->tx.curr[j] = vptr->tx.used[j] = 0;
+       }
+       return 0;
+}
+
+/**
+ *     velocity_free_dma_rings -       free PCI ring pointers
+ *     @vptr: Velocity to free from
+ *
+ *     Clean up the PCI ring buffers allocated to this velocity.
+ */
+static void velocity_free_dma_rings(struct velocity_info *vptr)
+{
+       const int size = vptr->options.numrx * sizeof(struct rx_desc) +
+               vptr->options.numtx * sizeof(struct tx_desc) * vptr->tx.numq;
+
+       pci_free_consistent(vptr->pdev, size, vptr->rx.ring, vptr->rx.pool_dma);
+}
+
+static int velocity_init_rings(struct velocity_info *vptr, int mtu)
+{
+       int ret;
+
+       velocity_set_rxbufsize(vptr, mtu);
+
+       ret = velocity_init_dma_rings(vptr);
+       if (ret < 0)
+               goto out;
+
+       ret = velocity_init_rd_ring(vptr);
+       if (ret < 0)
+               goto err_free_dma_rings_0;
+
+       ret = velocity_init_td_ring(vptr);
+       if (ret < 0)
+               goto err_free_rd_ring_1;
+out:
+       return ret;
+
+err_free_rd_ring_1:
+       velocity_free_rd_ring(vptr);
+err_free_dma_rings_0:
+       velocity_free_dma_rings(vptr);
+       goto out;
+}
+
+/**
+ *     velocity_free_tx_buf    -       free transmit buffer
+ *     @vptr: velocity
+ *     @tdinfo: buffer
+ *
+ *     Release an transmit buffer. If the buffer was preallocated then
+ *     recycle it, if not then unmap the buffer.
+ */
+static void velocity_free_tx_buf(struct velocity_info *vptr,
+               struct velocity_td_info *tdinfo, struct tx_desc *td)
+{
+       struct sk_buff *skb = tdinfo->skb;
+
+       /*
+        *      Don't unmap the pre-allocated tx_bufs
+        */
+       if (tdinfo->skb_dma) {
+               int i;
+
+               for (i = 0; i < tdinfo->nskb_dma; i++) {
+                       size_t pktlen = max_t(size_t, skb->len, ETH_ZLEN);
+
+                       /* For scatter-gather */
+                       if (skb_shinfo(skb)->nr_frags > 0)
+                               pktlen = max_t(size_t, pktlen,
+                                               td->td_buf[i].size & ~TD_QUEUE);
+
+                       pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i],
+                                       le16_to_cpu(pktlen), PCI_DMA_TODEVICE);
+               }
+       }
+       dev_kfree_skb_irq(skb);
+       tdinfo->skb = NULL;
+}
+
+/*
+ *     FIXME: could we merge this with velocity_free_tx_buf ?
+ */
+static void velocity_free_td_ring_entry(struct velocity_info *vptr,
+                                                        int q, int n)
+{
+       struct velocity_td_info *td_info = &(vptr->tx.infos[q][n]);
+       int i;
+
+       if (td_info == NULL)
+               return;
+
+       if (td_info->skb) {
+               for (i = 0; i < td_info->nskb_dma; i++) {
+                       if (td_info->skb_dma[i]) {
+                               pci_unmap_single(vptr->pdev, td_info->skb_dma[i],
+                                       td_info->skb->len, PCI_DMA_TODEVICE);
+                               td_info->skb_dma[i] = 0;
+                       }
+               }
+               dev_kfree_skb(td_info->skb);
+               td_info->skb = NULL;
+       }
+}
+
+/**
+ *     velocity_free_td_ring   -       free td ring
+ *     @vptr: velocity
+ *
+ *     Free up the transmit ring for this particular velocity adapter.
+ *     We free the ring contents but not the ring itself.
+ */
+static void velocity_free_td_ring(struct velocity_info *vptr)
+{
+       int i, j;
+
+       for (j = 0; j < vptr->tx.numq; j++) {
+               if (vptr->tx.infos[j] == NULL)
+                       continue;
+               for (i = 0; i < vptr->options.numtx; i++)
+                       velocity_free_td_ring_entry(vptr, j, i);
+
+               kfree(vptr->tx.infos[j]);
+               vptr->tx.infos[j] = NULL;
+       }
+}
+
+static void velocity_free_rings(struct velocity_info *vptr)
+{
+       velocity_free_td_ring(vptr);
+       velocity_free_rd_ring(vptr);
+       velocity_free_dma_rings(vptr);
+}
+
+/**
+ *     velocity_error  -       handle error from controller
+ *     @vptr: velocity
+ *     @status: card status
+ *
+ *     Process an error report from the hardware and attempt to recover
+ *     the card itself. At the moment we cannot recover from some
+ *     theoretically impossible errors but this could be fixed using
+ *     the pci_device_failed logic to bounce the hardware
+ *
+ */
+static void velocity_error(struct velocity_info *vptr, int status)
+{
+
+       if (status & ISR_TXSTLI) {
+               struct mac_regs __iomem *regs = vptr->mac_regs;
+
+               printk(KERN_ERR "TD structure error TDindex=%hx\n", readw(&regs->TDIdx[0]));
+               BYTE_REG_BITS_ON(TXESR_TDSTR, &regs->TXESR);
+               writew(TRDCSR_RUN, &regs->TDCSRClr);
+               netif_stop_queue(vptr->dev);
+
+               /* FIXME: port over the pci_device_failed code and use it
+                  here */
+       }
+
+       if (status & ISR_SRCI) {
+               struct mac_regs __iomem *regs = vptr->mac_regs;
+               int linked;
+
+               if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
+                       vptr->mii_status = check_connection_type(regs);
+
+                       /*
+                        *      If it is a 3119, disable frame bursting in
+                        *      halfduplex mode and enable it in fullduplex
+                        *       mode
+                        */
+                       if (vptr->rev_id < REV_ID_VT3216_A0) {
+                               if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
+                                       BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR);
+                               else
+                                       BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR);
+                       }
+                       /*
+                        *      Only enable CD heart beat counter in 10HD mode
+                        */
+                       if (!(vptr->mii_status & VELOCITY_DUPLEX_FULL) && (vptr->mii_status & VELOCITY_SPEED_10))
+                               BYTE_REG_BITS_OFF(TESTCFG_HBDIS, &regs->TESTCFG);
+                       else
+                               BYTE_REG_BITS_ON(TESTCFG_HBDIS, &regs->TESTCFG);
+
+                       setup_queue_timers(vptr);
+               }
+               /*
+                *      Get link status from PHYSR0
+                */
+               linked = readb(&regs->PHYSR0) & PHYSR0_LINKGD;
+
+               if (linked) {
+                       vptr->mii_status &= ~VELOCITY_LINK_FAIL;
+                       netif_carrier_on(vptr->dev);
+               } else {
+                       vptr->mii_status |= VELOCITY_LINK_FAIL;
+                       netif_carrier_off(vptr->dev);
+               }
+
+               velocity_print_link_status(vptr);
+               enable_flow_control_ability(vptr);
+
+               /*
+                *      Re-enable auto-polling because SRCI will disable
+                *      auto-polling
+                */
+
+               enable_mii_autopoll(regs);
+
+               if (vptr->mii_status & VELOCITY_LINK_FAIL)
+                       netif_stop_queue(vptr->dev);
+               else
+                       netif_wake_queue(vptr->dev);
+
+       }
+       if (status & ISR_MIBFI)
+               velocity_update_hw_mibs(vptr);
+       if (status & ISR_LSTEI)
+               mac_rx_queue_wake(vptr->mac_regs);
+}
+
+/**
+ *     tx_srv          -       transmit interrupt service
+ *     @vptr; Velocity
+ *
+ *     Scan the queues looking for transmitted packets that
+ *     we can complete and clean up. Update any statistics as
+ *     necessary/
+ */
+static int velocity_tx_srv(struct velocity_info *vptr)
+{
+       struct tx_desc *td;
+       int qnum;
+       int full = 0;
+       int idx;
+       int works = 0;
+       struct velocity_td_info *tdinfo;
+       struct net_device_stats *stats = &vptr->dev->stats;
+
+       for (qnum = 0; qnum < vptr->tx.numq; qnum++) {
+               for (idx = vptr->tx.tail[qnum]; vptr->tx.used[qnum] > 0;
+                       idx = (idx + 1) % vptr->options.numtx) {
+
+                       /*
+                        *      Get Tx Descriptor
+                        */
+                       td = &(vptr->tx.rings[qnum][idx]);
+                       tdinfo = &(vptr->tx.infos[qnum][idx]);
+
+                       if (td->tdesc0.len & OWNED_BY_NIC)
+                               break;
+
+                       if ((works++ > 15))
+                               break;
+
+                       if (td->tdesc0.TSR & TSR0_TERR) {
+                               stats->tx_errors++;
+                               stats->tx_dropped++;
+                               if (td->tdesc0.TSR & TSR0_CDH)
+                                       stats->tx_heartbeat_errors++;
+                               if (td->tdesc0.TSR & TSR0_CRS)
+                                       stats->tx_carrier_errors++;
+                               if (td->tdesc0.TSR & TSR0_ABT)
+                                       stats->tx_aborted_errors++;
+                               if (td->tdesc0.TSR & TSR0_OWC)
+                                       stats->tx_window_errors++;
+                       } else {
+                               stats->tx_packets++;
+                               stats->tx_bytes += tdinfo->skb->len;
+                       }
+                       velocity_free_tx_buf(vptr, tdinfo, td);
+                       vptr->tx.used[qnum]--;
+               }
+               vptr->tx.tail[qnum] = idx;
+
+               if (AVAIL_TD(vptr, qnum) < 1)
+                       full = 1;
+       }
+       /*
+        *      Look to see if we should kick the transmit network
+        *      layer for more work.
+        */
+       if (netif_queue_stopped(vptr->dev) && (full == 0) &&
+           (!(vptr->mii_status & VELOCITY_LINK_FAIL))) {
+               netif_wake_queue(vptr->dev);
+       }
+       return works;
+}
+
+/**
+ *     velocity_rx_csum        -       checksum process
+ *     @rd: receive packet descriptor
+ *     @skb: network layer packet buffer
+ *
+ *     Process the status bits for the received packet and determine
+ *     if the checksum was computed and verified by the hardware
+ */
+static inline void velocity_rx_csum(struct rx_desc *rd, struct sk_buff *skb)
+{
+       skb_checksum_none_assert(skb);
+
+       if (rd->rdesc1.CSM & CSM_IPKT) {
+               if (rd->rdesc1.CSM & CSM_IPOK) {
+                       if ((rd->rdesc1.CSM & CSM_TCPKT) ||
+                                       (rd->rdesc1.CSM & CSM_UDPKT)) {
+                               if (!(rd->rdesc1.CSM & CSM_TUPOK))
+                                       return;
+                       }
+                       skb->ip_summed = CHECKSUM_UNNECESSARY;
+               }
+       }
+}
+
+/**
+ *     velocity_rx_copy        -       in place Rx copy for small packets
+ *     @rx_skb: network layer packet buffer candidate
+ *     @pkt_size: received data size
+ *     @rd: receive packet descriptor
+ *     @dev: network device
+ *
+ *     Replace the current skb that is scheduled for Rx processing by a
+ *     shorter, immediately allocated skb, if the received packet is small
+ *     enough. This function returns a negative value if the received
+ *     packet is too big or if memory is exhausted.
+ */
+static int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
+                           struct velocity_info *vptr)
+{
+       int ret = -1;
+       if (pkt_size < rx_copybreak) {
+               struct sk_buff *new_skb;
+
+               new_skb = netdev_alloc_skb_ip_align(vptr->dev, pkt_size);
+               if (new_skb) {
+                       new_skb->ip_summed = rx_skb[0]->ip_summed;
+                       skb_copy_from_linear_data(*rx_skb, new_skb->data, pkt_size);
+                       *rx_skb = new_skb;
+                       ret = 0;
+               }
+
+       }
+       return ret;
+}
+
+/**
+ *     velocity_iph_realign    -       IP header alignment
+ *     @vptr: velocity we are handling
+ *     @skb: network layer packet buffer
+ *     @pkt_size: received data size
+ *
+ *     Align IP header on a 2 bytes boundary. This behavior can be
+ *     configured by the user.
+ */
+static inline void velocity_iph_realign(struct velocity_info *vptr,
+                                       struct sk_buff *skb, int pkt_size)
+{
+       if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN) {
+               memmove(skb->data + 2, skb->data, pkt_size);
+               skb_reserve(skb, 2);
+       }
+}
+
+/**
+ *     velocity_receive_frame  -       received packet processor
+ *     @vptr: velocity we are handling
+ *     @idx: ring index
+ *
+ *     A packet has arrived. We process the packet and if appropriate
+ *     pass the frame up the network stack
+ */
+static int velocity_receive_frame(struct velocity_info *vptr, int idx)
+{
+       void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
+       struct net_device_stats *stats = &vptr->dev->stats;
+       struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
+       struct rx_desc *rd = &(vptr->rx.ring[idx]);
+       int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff;
+       struct sk_buff *skb;
+
+       if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
+               VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->dev->name);
+               stats->rx_length_errors++;
+               return -EINVAL;
+       }
+
+       if (rd->rdesc0.RSR & RSR_MAR)
+               stats->multicast++;
+
+       skb = rd_info->skb;
+
+       pci_dma_sync_single_for_cpu(vptr->pdev, rd_info->skb_dma,
+                                   vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
+
+       /*
+        *      Drop frame not meeting IEEE 802.3
+        */
+
+       if (vptr->flags & VELOCITY_FLAGS_VAL_PKT_LEN) {
+               if (rd->rdesc0.RSR & RSR_RL) {
+                       stats->rx_length_errors++;
+                       return -EINVAL;
+               }
+       }
+
+       pci_action = pci_dma_sync_single_for_device;
+
+       velocity_rx_csum(rd, skb);
+
+       if (velocity_rx_copy(&skb, pkt_len, vptr) < 0) {
+               velocity_iph_realign(vptr, skb, pkt_len);
+               pci_action = pci_unmap_single;
+               rd_info->skb = NULL;
+       }
+
+       pci_action(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
+                  PCI_DMA_FROMDEVICE);
+
+       skb_put(skb, pkt_len - 4);
+       skb->protocol = eth_type_trans(skb, vptr->dev);
+
+       if (rd->rdesc0.RSR & RSR_DETAG) {
+               u16 vid = swab16(le16_to_cpu(rd->rdesc1.PQTAG));
+
+               __vlan_hwaccel_put_tag(skb, vid);
+       }
+       netif_rx(skb);
+
+       stats->rx_bytes += pkt_len;
+       stats->rx_packets++;
+
+       return 0;
+}
+
+/**
+ *     velocity_rx_srv         -       service RX interrupt
+ *     @vptr: velocity
+ *
+ *     Walk the receive ring of the velocity adapter and remove
+ *     any received packets from the receive queue. Hand the ring
+ *     slots back to the adapter for reuse.
+ */
+static int velocity_rx_srv(struct velocity_info *vptr, int budget_left)
+{
+       struct net_device_stats *stats = &vptr->dev->stats;
+       int rd_curr = vptr->rx.curr;
+       int works = 0;
+
+       while (works < budget_left) {
+               struct rx_desc *rd = vptr->rx.ring + rd_curr;
+
+               if (!vptr->rx.info[rd_curr].skb)
+                       break;
+
+               if (rd->rdesc0.len & OWNED_BY_NIC)
+                       break;
+
+               rmb();
+
+               /*
+                *      Don't drop CE or RL error frame although RXOK is off
+                */
+               if (rd->rdesc0.RSR & (RSR_RXOK | RSR_CE | RSR_RL)) {
+                       if (velocity_receive_frame(vptr, rd_curr) < 0)
+                               stats->rx_dropped++;
+               } else {
+                       if (rd->rdesc0.RSR & RSR_CRC)
+                               stats->rx_crc_errors++;
+                       if (rd->rdesc0.RSR & RSR_FAE)
+                               stats->rx_frame_errors++;
+
+                       stats->rx_dropped++;
+               }
+
+               rd->size |= RX_INTEN;
+
+               rd_curr++;
+               if (rd_curr >= vptr->options.numrx)
+                       rd_curr = 0;
+               works++;
+       }
+
+       vptr->rx.curr = rd_curr;
+
+       if ((works > 0) && (velocity_rx_refill(vptr) > 0))
+               velocity_give_many_rx_descs(vptr);
+
+       VAR_USED(stats);
+       return works;
+}
+
+static int velocity_poll(struct napi_struct *napi, int budget)
+{
+       struct velocity_info *vptr = container_of(napi,
+                       struct velocity_info, napi);
+       unsigned int rx_done;
+       unsigned long flags;
+
+       spin_lock_irqsave(&vptr->lock, flags);
+       /*
+        * Do rx and tx twice for performance (taken from the VIA
+        * out-of-tree driver).
+        */
+       rx_done = velocity_rx_srv(vptr, budget / 2);
+       velocity_tx_srv(vptr);
+       rx_done += velocity_rx_srv(vptr, budget - rx_done);
+       velocity_tx_srv(vptr);
+
+       /* If budget not fully consumed, exit the polling mode */
+       if (rx_done < budget) {
+               napi_complete(napi);
+               mac_enable_int(vptr->mac_regs);
+       }
+       spin_unlock_irqrestore(&vptr->lock, flags);
+
+       return rx_done;
+}
+
+/**
+ *     velocity_intr           -       interrupt callback
+ *     @irq: interrupt number
+ *     @dev_instance: interrupting device
+ *
+ *     Called whenever an interrupt is generated by the velocity
+ *     adapter IRQ line. We may not be the source of the interrupt
+ *     and need to identify initially if we are, and if not exit as
+ *     efficiently as possible.
+ */
+static irqreturn_t velocity_intr(int irq, void *dev_instance)
+{
+       struct net_device *dev = dev_instance;
+       struct velocity_info *vptr = netdev_priv(dev);
+       u32 isr_status;
+
+       spin_lock(&vptr->lock);
+       isr_status = mac_read_isr(vptr->mac_regs);
+
+       /* Not us ? */
+       if (isr_status == 0) {
+               spin_unlock(&vptr->lock);
+               return IRQ_NONE;
+       }
+
+       /* Ack the interrupt */
+       mac_write_isr(vptr->mac_regs, isr_status);
+
+       if (likely(napi_schedule_prep(&vptr->napi))) {
+               mac_disable_int(vptr->mac_regs);
+               __napi_schedule(&vptr->napi);
+       }
+
+       if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI)))
+               velocity_error(vptr, isr_status);
+
+       spin_unlock(&vptr->lock);
+
+       return IRQ_HANDLED;
+}
+
+/**
+ *     velocity_open           -       interface activation callback
+ *     @dev: network layer device to open
+ *
+ *     Called when the network layer brings the interface up. Returns
+ *     a negative posix error code on failure, or zero on success.
+ *
+ *     All the ring allocation and set up is done on open for this
+ *     adapter to minimise memory usage when inactive
+ */
+static int velocity_open(struct net_device *dev)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+       int ret;
+
+       ret = velocity_init_rings(vptr, dev->mtu);
+       if (ret < 0)
+               goto out;
+
+       /* Ensure chip is running */
+       pci_set_power_state(vptr->pdev, PCI_D0);
+
+       velocity_init_registers(vptr, VELOCITY_INIT_COLD);
+
+       ret = request_irq(vptr->pdev->irq, velocity_intr, IRQF_SHARED,
+                         dev->name, dev);
+       if (ret < 0) {
+               /* Power down the chip */
+               pci_set_power_state(vptr->pdev, PCI_D3hot);
+               velocity_free_rings(vptr);
+               goto out;
+       }
+
+       velocity_give_many_rx_descs(vptr);
+
+       mac_enable_int(vptr->mac_regs);
+       netif_start_queue(dev);
+       napi_enable(&vptr->napi);
+       vptr->flags |= VELOCITY_FLAGS_OPENED;
+out:
+       return ret;
+}
+
+/**
+ *     velocity_shutdown       -       shut down the chip
+ *     @vptr: velocity to deactivate
+ *
+ *     Shuts down the internal operations of the velocity and
+ *     disables interrupts, autopolling, transmit and receive
+ */
+static void velocity_shutdown(struct velocity_info *vptr)
+{
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+       mac_disable_int(regs);
+       writel(CR0_STOP, &regs->CR0Set);
+       writew(0xFFFF, &regs->TDCSRClr);
+       writeb(0xFF, &regs->RDCSRClr);
+       safe_disable_mii_autopoll(regs);
+       mac_clear_isr(regs);
+}
+
+/**
+ *     velocity_change_mtu     -       MTU change callback
+ *     @dev: network device
+ *     @new_mtu: desired MTU
+ *
+ *     Handle requests from the networking layer for MTU change on
+ *     this interface. It gets called on a change by the network layer.
+ *     Return zero for success or negative posix error code.
+ */
+static int velocity_change_mtu(struct net_device *dev, int new_mtu)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+       int ret = 0;
+
+       if ((new_mtu < VELOCITY_MIN_MTU) || new_mtu > (VELOCITY_MAX_MTU)) {
+               VELOCITY_PRT(MSG_LEVEL_ERR, KERN_NOTICE "%s: Invalid MTU.\n",
+                               vptr->dev->name);
+               ret = -EINVAL;
+               goto out_0;
+       }
+
+       if (!netif_running(dev)) {
+               dev->mtu = new_mtu;
+               goto out_0;
+       }
+
+       if (dev->mtu != new_mtu) {
+               struct velocity_info *tmp_vptr;
+               unsigned long flags;
+               struct rx_info rx;
+               struct tx_info tx;
+
+               tmp_vptr = kzalloc(sizeof(*tmp_vptr), GFP_KERNEL);
+               if (!tmp_vptr) {
+                       ret = -ENOMEM;
+                       goto out_0;
+               }
+
+               tmp_vptr->dev = dev;
+               tmp_vptr->pdev = vptr->pdev;
+               tmp_vptr->options = vptr->options;
+               tmp_vptr->tx.numq = vptr->tx.numq;
+
+               ret = velocity_init_rings(tmp_vptr, new_mtu);
+               if (ret < 0)
+                       goto out_free_tmp_vptr_1;
+
+               spin_lock_irqsave(&vptr->lock, flags);
+
+               netif_stop_queue(dev);
+               velocity_shutdown(vptr);
+
+               rx = vptr->rx;
+               tx = vptr->tx;
+
+               vptr->rx = tmp_vptr->rx;
+               vptr->tx = tmp_vptr->tx;
+
+               tmp_vptr->rx = rx;
+               tmp_vptr->tx = tx;
+
+               dev->mtu = new_mtu;
+
+               velocity_init_registers(vptr, VELOCITY_INIT_COLD);
+
+               velocity_give_many_rx_descs(vptr);
+
+               mac_enable_int(vptr->mac_regs);
+               netif_start_queue(dev);
+
+               spin_unlock_irqrestore(&vptr->lock, flags);
+
+               velocity_free_rings(tmp_vptr);
+
+out_free_tmp_vptr_1:
+               kfree(tmp_vptr);
+       }
+out_0:
+       return ret;
+}
+
+/**
+ *     velocity_mii_ioctl              -       MII ioctl handler
+ *     @dev: network device
+ *     @ifr: the ifreq block for the ioctl
+ *     @cmd: the command
+ *
+ *     Process MII requests made via ioctl from the network layer. These
+ *     are used by tools like kudzu to interrogate the link state of the
+ *     hardware
+ */
+static int velocity_mii_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+       unsigned long flags;
+       struct mii_ioctl_data *miidata = if_mii(ifr);
+       int err;
+
+       switch (cmd) {
+       case SIOCGMIIPHY:
+               miidata->phy_id = readb(&regs->MIIADR) & 0x1f;
+               break;
+       case SIOCGMIIREG:
+               if (velocity_mii_read(vptr->mac_regs, miidata->reg_num & 0x1f, &(miidata->val_out)) < 0)
+                       return -ETIMEDOUT;
+               break;
+       case SIOCSMIIREG:
+               spin_lock_irqsave(&vptr->lock, flags);
+               err = velocity_mii_write(vptr->mac_regs, miidata->reg_num & 0x1f, miidata->val_in);
+               spin_unlock_irqrestore(&vptr->lock, flags);
+               check_connection_type(vptr->mac_regs);
+               if (err)
+                       return err;
+               break;
+       default:
+               return -EOPNOTSUPP;
+       }
+       return 0;
+}
+
+/**
+ *     velocity_ioctl          -       ioctl entry point
+ *     @dev: network device
+ *     @rq: interface request ioctl
+ *     @cmd: command code
+ *
+ *     Called when the user issues an ioctl request to the network
+ *     device in question. The velocity interface supports MII.
+ */
+static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+       int ret;
+
+       /* If we are asked for information and the device is power
+          saving then we need to bring the device back up to talk to it */
+
+       if (!netif_running(dev))
+               pci_set_power_state(vptr->pdev, PCI_D0);
+
+       switch (cmd) {
+       case SIOCGMIIPHY:       /* Get address of MII PHY in use. */
+       case SIOCGMIIREG:       /* Read MII PHY register. */
+       case SIOCSMIIREG:       /* Write to MII PHY register. */
+               ret = velocity_mii_ioctl(dev, rq, cmd);
+               break;
+
+       default:
+               ret = -EOPNOTSUPP;
+       }
+       if (!netif_running(dev))
+               pci_set_power_state(vptr->pdev, PCI_D3hot);
+
+
+       return ret;
+}
+
+/**
+ *     velocity_get_status     -       statistics callback
+ *     @dev: network device
+ *
+ *     Callback from the network layer to allow driver statistics
+ *     to be resynchronized with hardware collected state. In the
+ *     case of the velocity we need to pull the MIB counters from
+ *     the hardware into the counters before letting the network
+ *     layer display them.
+ */
+static struct net_device_stats *velocity_get_stats(struct net_device *dev)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+
+       /* If the hardware is down, don't touch MII */
+       if (!netif_running(dev))
+               return &dev->stats;
+
+       spin_lock_irq(&vptr->lock);
+       velocity_update_hw_mibs(vptr);
+       spin_unlock_irq(&vptr->lock);
+
+       dev->stats.rx_packets = vptr->mib_counter[HW_MIB_ifRxAllPkts];
+       dev->stats.rx_errors = vptr->mib_counter[HW_MIB_ifRxErrorPkts];
+       dev->stats.rx_length_errors = vptr->mib_counter[HW_MIB_ifInRangeLengthErrors];
+
+//  unsigned long   rx_dropped;     /* no space in linux buffers    */
+       dev->stats.collisions = vptr->mib_counter[HW_MIB_ifTxEtherCollisions];
+       /* detailed rx_errors: */
+//  unsigned long   rx_length_errors;
+//  unsigned long   rx_over_errors;     /* receiver ring buff overflow  */
+       dev->stats.rx_crc_errors = vptr->mib_counter[HW_MIB_ifRxPktCRCE];
+//  unsigned long   rx_frame_errors;    /* recv'd frame alignment error */
+//  unsigned long   rx_fifo_errors;     /* recv'r fifo overrun      */
+//  unsigned long   rx_missed_errors;   /* receiver missed packet   */
+
+       /* detailed tx_errors */
+//  unsigned long   tx_fifo_errors;
+
+       return &dev->stats;
+}
+
+/**
+ *     velocity_close          -       close adapter callback
+ *     @dev: network device
+ *
+ *     Callback from the network layer when the velocity is being
+ *     deactivated by the network layer
+ */
+static int velocity_close(struct net_device *dev)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+
+       napi_disable(&vptr->napi);
+       netif_stop_queue(dev);
+       velocity_shutdown(vptr);
+
+       if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED)
+               velocity_get_ip(vptr);
+       if (dev->irq != 0)
+               free_irq(dev->irq, dev);
+
+       /* Power down the chip */
+       pci_set_power_state(vptr->pdev, PCI_D3hot);
+
+       velocity_free_rings(vptr);
+
+       vptr->flags &= (~VELOCITY_FLAGS_OPENED);
+       return 0;
+}
+
+/**
+ *     velocity_xmit           -       transmit packet callback
+ *     @skb: buffer to transmit
+ *     @dev: network device
+ *
+ *     Called by the networ layer to request a packet is queued to
+ *     the velocity. Returns zero on success.
+ */
+static netdev_tx_t velocity_xmit(struct sk_buff *skb,
+                                struct net_device *dev)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+       int qnum = 0;
+       struct tx_desc *td_ptr;
+       struct velocity_td_info *tdinfo;
+       unsigned long flags;
+       int pktlen;
+       int index, prev;
+       int i = 0;
+
+       if (skb_padto(skb, ETH_ZLEN))
+               goto out;
+
+       /* The hardware can handle at most 7 memory segments, so merge
+        * the skb if there are more */
+       if (skb_shinfo(skb)->nr_frags > 6 && __skb_linearize(skb)) {
+               kfree_skb(skb);
+               return NETDEV_TX_OK;
+       }
+
+       pktlen = skb_shinfo(skb)->nr_frags == 0 ?
+                       max_t(unsigned int, skb->len, ETH_ZLEN) :
+                               skb_headlen(skb);
+
+       spin_lock_irqsave(&vptr->lock, flags);
+
+       index = vptr->tx.curr[qnum];
+       td_ptr = &(vptr->tx.rings[qnum][index]);
+       tdinfo = &(vptr->tx.infos[qnum][index]);
+
+       td_ptr->tdesc1.TCR = TCR0_TIC;
+       td_ptr->td_buf[0].size &= ~TD_QUEUE;
+
+       /*
+        *      Map the linear network buffer into PCI space and
+        *      add it to the transmit ring.
+        */
+       tdinfo->skb = skb;
+       tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE);
+       td_ptr->tdesc0.len = cpu_to_le16(pktlen);
+       td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
+       td_ptr->td_buf[0].pa_high = 0;
+       td_ptr->td_buf[0].size = cpu_to_le16(pktlen);
+
+       /* Handle fragments */
+       for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+               skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+
+               tdinfo->skb_dma[i + 1] = pci_map_page(vptr->pdev, frag->page,
+                               frag->page_offset, frag->size,
+                               PCI_DMA_TODEVICE);
+
+               td_ptr->td_buf[i + 1].pa_low = cpu_to_le32(tdinfo->skb_dma[i + 1]);
+               td_ptr->td_buf[i + 1].pa_high = 0;
+               td_ptr->td_buf[i + 1].size = cpu_to_le16(frag->size);
+       }
+       tdinfo->nskb_dma = i + 1;
+
+       td_ptr->tdesc1.cmd = TCPLS_NORMAL + (tdinfo->nskb_dma + 1) * 16;
+
+       if (vlan_tx_tag_present(skb)) {
+               td_ptr->tdesc1.vlan = cpu_to_le16(vlan_tx_tag_get(skb));
+               td_ptr->tdesc1.TCR |= TCR0_VETAG;
+       }
+
+       /*
+        *      Handle hardware checksum
+        */
+       if (skb->ip_summed == CHECKSUM_PARTIAL) {
+               const struct iphdr *ip = ip_hdr(skb);
+               if (ip->protocol == IPPROTO_TCP)
+                       td_ptr->tdesc1.TCR |= TCR0_TCPCK;
+               else if (ip->protocol == IPPROTO_UDP)
+                       td_ptr->tdesc1.TCR |= (TCR0_UDPCK);
+               td_ptr->tdesc1.TCR |= TCR0_IPCK;
+       }
+
+       prev = index - 1;
+       if (prev < 0)
+               prev = vptr->options.numtx - 1;
+       td_ptr->tdesc0.len |= OWNED_BY_NIC;
+       vptr->tx.used[qnum]++;
+       vptr->tx.curr[qnum] = (index + 1) % vptr->options.numtx;
+
+       if (AVAIL_TD(vptr, qnum) < 1)
+               netif_stop_queue(dev);
+
+       td_ptr = &(vptr->tx.rings[qnum][prev]);
+       td_ptr->td_buf[0].size |= TD_QUEUE;
+       mac_tx_queue_wake(vptr->mac_regs, qnum);
+
+       spin_unlock_irqrestore(&vptr->lock, flags);
+out:
+       return NETDEV_TX_OK;
+}
+
+static const struct net_device_ops velocity_netdev_ops = {
+       .ndo_open               = velocity_open,
+       .ndo_stop               = velocity_close,
+       .ndo_start_xmit         = velocity_xmit,
+       .ndo_get_stats          = velocity_get_stats,
+       .ndo_validate_addr      = eth_validate_addr,
+       .ndo_set_mac_address    = eth_mac_addr,
+       .ndo_set_multicast_list = velocity_set_multi,
+       .ndo_change_mtu         = velocity_change_mtu,
+       .ndo_do_ioctl           = velocity_ioctl,
+       .ndo_vlan_rx_add_vid    = velocity_vlan_rx_add_vid,
+       .ndo_vlan_rx_kill_vid   = velocity_vlan_rx_kill_vid,
+};
+
+/**
+ *     velocity_init_info      -       init private data
+ *     @pdev: PCI device
+ *     @vptr: Velocity info
+ *     @info: Board type
+ *
+ *     Set up the initial velocity_info struct for the device that has been
+ *     discovered.
+ */
+static void __devinit velocity_init_info(struct pci_dev *pdev,
+                                        struct velocity_info *vptr,
+                                        const struct velocity_info_tbl *info)
+{
+       memset(vptr, 0, sizeof(struct velocity_info));
+
+       vptr->pdev = pdev;
+       vptr->chip_id = info->chip_id;
+       vptr->tx.numq = info->txqueue;
+       vptr->multicast_limit = MCAM_SIZE;
+       spin_lock_init(&vptr->lock);
+}
+
+/**
+ *     velocity_get_pci_info   -       retrieve PCI info for device
+ *     @vptr: velocity device
+ *     @pdev: PCI device it matches
+ *
+ *     Retrieve the PCI configuration space data that interests us from
+ *     the kernel PCI layer
+ */
+static int __devinit velocity_get_pci_info(struct velocity_info *vptr, struct pci_dev *pdev)
+{
+       vptr->rev_id = pdev->revision;
+
+       pci_set_master(pdev);
+
+       vptr->ioaddr = pci_resource_start(pdev, 0);
+       vptr->memaddr = pci_resource_start(pdev, 1);
+
+       if (!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
+               dev_err(&pdev->dev,
+                          "region #0 is not an I/O resource, aborting.\n");
+               return -EINVAL;
+       }
+
+       if ((pci_resource_flags(pdev, 1) & IORESOURCE_IO)) {
+               dev_err(&pdev->dev,
+                          "region #1 is an I/O resource, aborting.\n");
+               return -EINVAL;
+       }
+
+       if (pci_resource_len(pdev, 1) < VELOCITY_IO_SIZE) {
+               dev_err(&pdev->dev, "region #1 is too small.\n");
+               return -EINVAL;
+       }
+       vptr->pdev = pdev;
+
+       return 0;
+}
+
+/**
+ *     velocity_print_info     -       per driver data
+ *     @vptr: velocity
+ *
+ *     Print per driver data as the kernel driver finds Velocity
+ *     hardware
+ */
+static void __devinit velocity_print_info(struct velocity_info *vptr)
+{
+       struct net_device *dev = vptr->dev;
+
+       printk(KERN_INFO "%s: %s\n", dev->name, get_chip_name(vptr->chip_id));
+       printk(KERN_INFO "%s: Ethernet Address: %pM\n",
+               dev->name, dev->dev_addr);
+}
+
+static u32 velocity_get_link(struct net_device *dev)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+       return BYTE_REG_BITS_IS_ON(PHYSR0_LINKGD, &regs->PHYSR0) ? 1 : 0;
+}
+
+/**
+ *     velocity_found1         -       set up discovered velocity card
+ *     @pdev: PCI device
+ *     @ent: PCI device table entry that matched
+ *
+ *     Configure a discovered adapter from scratch. Return a negative
+ *     errno error code on failure paths.
+ */
+static int __devinit velocity_found1(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+       static int first = 1;
+       struct net_device *dev;
+       int i;
+       const char *drv_string;
+       const struct velocity_info_tbl *info = &chip_info_table[ent->driver_data];
+       struct velocity_info *vptr;
+       struct mac_regs __iomem *regs;
+       int ret = -ENOMEM;
+
+       /* FIXME: this driver, like almost all other ethernet drivers,
+        * can support more than MAX_UNITS.
+        */
+       if (velocity_nics >= MAX_UNITS) {
+               dev_notice(&pdev->dev, "already found %d NICs.\n",
+                          velocity_nics);
+               return -ENODEV;
+       }
+
+       dev = alloc_etherdev(sizeof(struct velocity_info));
+       if (!dev) {
+               dev_err(&pdev->dev, "allocate net device failed.\n");
+               goto out;
+       }
+
+       /* Chain it all together */
+
+       SET_NETDEV_DEV(dev, &pdev->dev);
+       vptr = netdev_priv(dev);
+
+
+       if (first) {
+               printk(KERN_INFO "%s Ver. %s\n",
+                       VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
+               printk(KERN_INFO "Copyright (c) 2002, 2003 VIA Networking Technologies, Inc.\n");
+               printk(KERN_INFO "Copyright (c) 2004 Red Hat Inc.\n");
+               first = 0;
+       }
+
+       velocity_init_info(pdev, vptr, info);
+
+       vptr->dev = dev;
+
+       ret = pci_enable_device(pdev);
+       if (ret < 0)
+               goto err_free_dev;
+
+       dev->irq = pdev->irq;
+
+       ret = velocity_get_pci_info(vptr, pdev);
+       if (ret < 0) {
+               /* error message already printed */
+               goto err_disable;
+       }
+
+       ret = pci_request_regions(pdev, VELOCITY_NAME);
+       if (ret < 0) {
+               dev_err(&pdev->dev, "No PCI resources.\n");
+               goto err_disable;
+       }
+
+       regs = ioremap(vptr->memaddr, VELOCITY_IO_SIZE);
+       if (regs == NULL) {
+               ret = -EIO;
+               goto err_release_res;
+       }
+
+       vptr->mac_regs = regs;
+
+       mac_wol_reset(regs);
+
+       dev->base_addr = vptr->ioaddr;
+
+       for (i = 0; i < 6; i++)
+               dev->dev_addr[i] = readb(&regs->PAR[i]);
+
+
+       drv_string = dev_driver_string(&pdev->dev);
+
+       velocity_get_options(&vptr->options, velocity_nics, drv_string);
+
+       /*
+        *      Mask out the options cannot be set to the chip
+        */
+
+       vptr->options.flags &= info->flags;
+
+       /*
+        *      Enable the chip specified capbilities
+        */
+
+       vptr->flags = vptr->options.flags | (info->flags & 0xFF000000UL);
+
+       vptr->wol_opts = vptr->options.wol_opts;
+       vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
+
+       vptr->phy_id = MII_GET_PHY_ID(vptr->mac_regs);
+
+       dev->irq = pdev->irq;
+       dev->netdev_ops = &velocity_netdev_ops;
+       dev->ethtool_ops = &velocity_ethtool_ops;
+       netif_napi_add(dev, &vptr->napi, velocity_poll, VELOCITY_NAPI_WEIGHT);
+
+       dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HW_VLAN_TX;
+       dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER |
+               NETIF_F_HW_VLAN_RX | NETIF_F_IP_CSUM;
+
+       ret = register_netdev(dev);
+       if (ret < 0)
+               goto err_iounmap;
+
+       if (!velocity_get_link(dev)) {
+               netif_carrier_off(dev);
+               vptr->mii_status |= VELOCITY_LINK_FAIL;
+       }
+
+       velocity_print_info(vptr);
+       pci_set_drvdata(pdev, dev);
+
+       /* and leave the chip powered down */
+
+       pci_set_power_state(pdev, PCI_D3hot);
+       velocity_nics++;
+out:
+       return ret;
+
+err_iounmap:
+       iounmap(regs);
+err_release_res:
+       pci_release_regions(pdev);
+err_disable:
+       pci_disable_device(pdev);
+err_free_dev:
+       free_netdev(dev);
+       goto out;
+}
+
+#ifdef CONFIG_PM
+/**
+ *     wol_calc_crc            -       WOL CRC
+ *     @pattern: data pattern
+ *     @mask_pattern: mask
+ *
+ *     Compute the wake on lan crc hashes for the packet header
+ *     we are interested in.
+ */
+static u16 wol_calc_crc(int size, u8 *pattern, u8 *mask_pattern)
+{
+       u16 crc = 0xFFFF;
+       u8 mask;
+       int i, j;
+
+       for (i = 0; i < size; i++) {
+               mask = mask_pattern[i];
+
+               /* Skip this loop if the mask equals to zero */
+               if (mask == 0x00)
+                       continue;
+
+               for (j = 0; j < 8; j++) {
+                       if ((mask & 0x01) == 0) {
+                               mask >>= 1;
+                               continue;
+                       }
+                       mask >>= 1;
+                       crc = crc_ccitt(crc, &(pattern[i * 8 + j]), 1);
+               }
+       }
+       /*      Finally, invert the result once to get the correct data */
+       crc = ~crc;
+       return bitrev32(crc) >> 16;
+}
+
+/**
+ *     velocity_set_wol        -       set up for wake on lan
+ *     @vptr: velocity to set WOL status on
+ *
+ *     Set a card up for wake on lan either by unicast or by
+ *     ARP packet.
+ *
+ *     FIXME: check static buffer is safe here
+ */
+static int velocity_set_wol(struct velocity_info *vptr)
+{
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+       enum speed_opt spd_dpx = vptr->options.spd_dpx;
+       static u8 buf[256];
+       int i;
+
+       static u32 mask_pattern[2][4] = {
+               {0x00203000, 0x000003C0, 0x00000000, 0x0000000}, /* ARP */
+               {0xfffff000, 0xffffffff, 0xffffffff, 0x000ffff}  /* Magic Packet */
+       };
+
+       writew(0xFFFF, &regs->WOLCRClr);
+       writeb(WOLCFG_SAB | WOLCFG_SAM, &regs->WOLCFGSet);
+       writew(WOLCR_MAGIC_EN, &regs->WOLCRSet);
+
+       /*
+          if (vptr->wol_opts & VELOCITY_WOL_PHY)
+          writew((WOLCR_LINKON_EN|WOLCR_LINKOFF_EN), &regs->WOLCRSet);
+        */
+
+       if (vptr->wol_opts & VELOCITY_WOL_UCAST)
+               writew(WOLCR_UNICAST_EN, &regs->WOLCRSet);
+
+       if (vptr->wol_opts & VELOCITY_WOL_ARP) {
+               struct arp_packet *arp = (struct arp_packet *) buf;
+               u16 crc;
+               memset(buf, 0, sizeof(struct arp_packet) + 7);
+
+               for (i = 0; i < 4; i++)
+                       writel(mask_pattern[0][i], &regs->ByteMask[0][i]);
+
+               arp->type = htons(ETH_P_ARP);
+               arp->ar_op = htons(1);
+
+               memcpy(arp->ar_tip, vptr->ip_addr, 4);
+
+               crc = wol_calc_crc((sizeof(struct arp_packet) + 7) / 8, buf,
+                               (u8 *) & mask_pattern[0][0]);
+
+               writew(crc, &regs->PatternCRC[0]);
+               writew(WOLCR_ARP_EN, &regs->WOLCRSet);
+       }
+
+       BYTE_REG_BITS_ON(PWCFG_WOLTYPE, &regs->PWCFGSet);
+       BYTE_REG_BITS_ON(PWCFG_LEGACY_WOLEN, &regs->PWCFGSet);
+
+       writew(0x0FFF, &regs->WOLSRClr);
+
+       if (spd_dpx == SPD_DPX_1000_FULL)
+               goto mac_done;
+
+       if (spd_dpx != SPD_DPX_AUTO)
+               goto advertise_done;
+
+       if (vptr->mii_status & VELOCITY_AUTONEG_ENABLE) {
+               if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
+                       MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
+
+               MII_REG_BITS_OFF(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
+       }
+
+       if (vptr->mii_status & VELOCITY_SPEED_1000)
+               MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
+
+advertise_done:
+       BYTE_REG_BITS_ON(CHIPGCR_FCMODE, &regs->CHIPGCR);
+
+       {
+               u8 GCR;
+               GCR = readb(&regs->CHIPGCR);
+               GCR = (GCR & ~CHIPGCR_FCGMII) | CHIPGCR_FCFDX;
+               writeb(GCR, &regs->CHIPGCR);
+       }
+
+mac_done:
+       BYTE_REG_BITS_OFF(ISR_PWEI, &regs->ISR);
+       /* Turn on SWPTAG just before entering power mode */
+       BYTE_REG_BITS_ON(STICKHW_SWPTAG, &regs->STICKHW);
+       /* Go to bed ..... */
+       BYTE_REG_BITS_ON((STICKHW_DS1 | STICKHW_DS0), &regs->STICKHW);
+
+       return 0;
+}
+
+/**
+ *     velocity_save_context   -       save registers
+ *     @vptr: velocity
+ *     @context: buffer for stored context
+ *
+ *     Retrieve the current configuration from the velocity hardware
+ *     and stash it in the context structure, for use by the context
+ *     restore functions. This allows us to save things we need across
+ *     power down states
+ */
+static void velocity_save_context(struct velocity_info *vptr, struct velocity_context *context)
+{
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+       u16 i;
+       u8 __iomem *ptr = (u8 __iomem *)regs;
+
+       for (i = MAC_REG_PAR; i < MAC_REG_CR0_CLR; i += 4)
+               *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
+
+       for (i = MAC_REG_MAR; i < MAC_REG_TDCSR_CLR; i += 4)
+               *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
+
+       for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
+               *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
+
+}
+
+static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct velocity_info *vptr = netdev_priv(dev);
+       unsigned long flags;
+
+       if (!netif_running(vptr->dev))
+               return 0;
+
+       netif_device_detach(vptr->dev);
+
+       spin_lock_irqsave(&vptr->lock, flags);
+       pci_save_state(pdev);
+
+       if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED) {
+               velocity_get_ip(vptr);
+               velocity_save_context(vptr, &vptr->context);
+               velocity_shutdown(vptr);
+               velocity_set_wol(vptr);
+               pci_enable_wake(pdev, PCI_D3hot, 1);
+               pci_set_power_state(pdev, PCI_D3hot);
+       } else {
+               velocity_save_context(vptr, &vptr->context);
+               velocity_shutdown(vptr);
+               pci_disable_device(pdev);
+               pci_set_power_state(pdev, pci_choose_state(pdev, state));
+       }
+
+       spin_unlock_irqrestore(&vptr->lock, flags);
+       return 0;
+}
+
+/**
+ *     velocity_restore_context        -       restore registers
+ *     @vptr: velocity
+ *     @context: buffer for stored context
+ *
+ *     Reload the register configuration from the velocity context
+ *     created by velocity_save_context.
+ */
+static void velocity_restore_context(struct velocity_info *vptr, struct velocity_context *context)
+{
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+       int i;
+       u8 __iomem *ptr = (u8 __iomem *)regs;
+
+       for (i = MAC_REG_PAR; i < MAC_REG_CR0_SET; i += 4)
+               writel(*((u32 *) (context->mac_reg + i)), ptr + i);
+
+       /* Just skip cr0 */
+       for (i = MAC_REG_CR1_SET; i < MAC_REG_CR0_CLR; i++) {
+               /* Clear */
+               writeb(~(*((u8 *) (context->mac_reg + i))), ptr + i + 4);
+               /* Set */
+               writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
+       }
+
+       for (i = MAC_REG_MAR; i < MAC_REG_IMR; i += 4)
+               writel(*((u32 *) (context->mac_reg + i)), ptr + i);
+
+       for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
+               writel(*((u32 *) (context->mac_reg + i)), ptr + i);
+
+       for (i = MAC_REG_TDCSR_SET; i <= MAC_REG_RDCSR_SET; i++)
+               writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
+}
+
+static int velocity_resume(struct pci_dev *pdev)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct velocity_info *vptr = netdev_priv(dev);
+       unsigned long flags;
+       int i;
+
+       if (!netif_running(vptr->dev))
+               return 0;
+
+       pci_set_power_state(pdev, PCI_D0);
+       pci_enable_wake(pdev, 0, 0);
+       pci_restore_state(pdev);
+
+       mac_wol_reset(vptr->mac_regs);
+
+       spin_lock_irqsave(&vptr->lock, flags);
+       velocity_restore_context(vptr, &vptr->context);
+       velocity_init_registers(vptr, VELOCITY_INIT_WOL);
+       mac_disable_int(vptr->mac_regs);
+
+       velocity_tx_srv(vptr);
+
+       for (i = 0; i < vptr->tx.numq; i++) {
+               if (vptr->tx.used[i])
+                       mac_tx_queue_wake(vptr->mac_regs, i);
+       }
+
+       mac_enable_int(vptr->mac_regs);
+       spin_unlock_irqrestore(&vptr->lock, flags);
+       netif_device_attach(vptr->dev);
+
+       return 0;
+}
+#endif
+
+/*
+ *     Definition for our device driver. The PCI layer interface
+ *     uses this to handle all our card discover and plugging
+ */
+static struct pci_driver velocity_driver = {
+       .name           = VELOCITY_NAME,
+       .id_table       = velocity_id_table,
+       .probe          = velocity_found1,
+       .remove         = __devexit_p(velocity_remove1),
+#ifdef CONFIG_PM
+       .suspend        = velocity_suspend,
+       .resume         = velocity_resume,
+#endif
+};
+
+
+/**
+ *     velocity_ethtool_up     -       pre hook for ethtool
+ *     @dev: network device
+ *
+ *     Called before an ethtool operation. We need to make sure the
+ *     chip is out of D3 state before we poke at it.
+ */
+static int velocity_ethtool_up(struct net_device *dev)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+       if (!netif_running(dev))
+               pci_set_power_state(vptr->pdev, PCI_D0);
+       return 0;
+}
+
+/**
+ *     velocity_ethtool_down   -       post hook for ethtool
+ *     @dev: network device
+ *
+ *     Called after an ethtool operation. Restore the chip back to D3
+ *     state if it isn't running.
+ */
+static void velocity_ethtool_down(struct net_device *dev)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+       if (!netif_running(dev))
+               pci_set_power_state(vptr->pdev, PCI_D3hot);
+}
+
+static int velocity_get_settings(struct net_device *dev,
+                                struct ethtool_cmd *cmd)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+       struct mac_regs __iomem *regs = vptr->mac_regs;
+       u32 status;
+       status = check_connection_type(vptr->mac_regs);
+
+       cmd->supported = SUPPORTED_TP |
+                       SUPPORTED_Autoneg |
+                       SUPPORTED_10baseT_Half |
+                       SUPPORTED_10baseT_Full |
+                       SUPPORTED_100baseT_Half |
+                       SUPPORTED_100baseT_Full |
+                       SUPPORTED_1000baseT_Half |
+                       SUPPORTED_1000baseT_Full;
+
+       cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
+       if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
+               cmd->advertising |=
+                       ADVERTISED_10baseT_Half |
+                       ADVERTISED_10baseT_Full |
+                       ADVERTISED_100baseT_Half |
+                       ADVERTISED_100baseT_Full |
+                       ADVERTISED_1000baseT_Half |
+                       ADVERTISED_1000baseT_Full;
+       } else {
+               switch (vptr->options.spd_dpx) {
+               case SPD_DPX_1000_FULL:
+                       cmd->advertising |= ADVERTISED_1000baseT_Full;
+                       break;
+               case SPD_DPX_100_HALF:
+                       cmd->advertising |= ADVERTISED_100baseT_Half;
+                       break;
+               case SPD_DPX_100_FULL:
+                       cmd->advertising |= ADVERTISED_100baseT_Full;
+                       break;
+               case SPD_DPX_10_HALF:
+                       cmd->advertising |= ADVERTISED_10baseT_Half;
+                       break;
+               case SPD_DPX_10_FULL:
+                       cmd->advertising |= ADVERTISED_10baseT_Full;
+                       break;
+               default:
+                       break;
+               }
+       }
+
+       if (status & VELOCITY_SPEED_1000)
+               ethtool_cmd_speed_set(cmd, SPEED_1000);
+       else if (status & VELOCITY_SPEED_100)
+               ethtool_cmd_speed_set(cmd, SPEED_100);
+       else
+               ethtool_cmd_speed_set(cmd, SPEED_10);
+
+       cmd->autoneg = (status & VELOCITY_AUTONEG_ENABLE) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
+       cmd->port = PORT_TP;
+       cmd->transceiver = XCVR_INTERNAL;
+       cmd->phy_address = readb(&regs->MIIADR) & 0x1F;
+
+       if (status & VELOCITY_DUPLEX_FULL)
+               cmd->duplex = DUPLEX_FULL;
+       else
+               cmd->duplex = DUPLEX_HALF;
+
+       return 0;
+}
+
+static int velocity_set_settings(struct net_device *dev,
+                                struct ethtool_cmd *cmd)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+       u32 speed = ethtool_cmd_speed(cmd);
+       u32 curr_status;
+       u32 new_status = 0;
+       int ret = 0;
+
+       curr_status = check_connection_type(vptr->mac_regs);
+       curr_status &= (~VELOCITY_LINK_FAIL);
+
+       new_status |= ((cmd->autoneg) ? VELOCITY_AUTONEG_ENABLE : 0);
+       new_status |= ((speed == SPEED_1000) ? VELOCITY_SPEED_1000 : 0);
+       new_status |= ((speed == SPEED_100) ? VELOCITY_SPEED_100 : 0);
+       new_status |= ((speed == SPEED_10) ? VELOCITY_SPEED_10 : 0);
+       new_status |= ((cmd->duplex == DUPLEX_FULL) ? VELOCITY_DUPLEX_FULL : 0);
+
+       if ((new_status & VELOCITY_AUTONEG_ENABLE) &&
+           (new_status != (curr_status | VELOCITY_AUTONEG_ENABLE))) {
+               ret = -EINVAL;
+       } else {
+               enum speed_opt spd_dpx;
+
+               if (new_status & VELOCITY_AUTONEG_ENABLE)
+                       spd_dpx = SPD_DPX_AUTO;
+               else if ((new_status & VELOCITY_SPEED_1000) &&
+                        (new_status & VELOCITY_DUPLEX_FULL)) {
+                       spd_dpx = SPD_DPX_1000_FULL;
+               } else if (new_status & VELOCITY_SPEED_100)
+                       spd_dpx = (new_status & VELOCITY_DUPLEX_FULL) ?
+                               SPD_DPX_100_FULL : SPD_DPX_100_HALF;
+               else if (new_status & VELOCITY_SPEED_10)
+                       spd_dpx = (new_status & VELOCITY_DUPLEX_FULL) ?
+                               SPD_DPX_10_FULL : SPD_DPX_10_HALF;
+               else
+                       return -EOPNOTSUPP;
+
+               vptr->options.spd_dpx = spd_dpx;
+
+               velocity_set_media_mode(vptr, new_status);
+       }
+
+       return ret;
+}
+
+static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+       strcpy(info->driver, VELOCITY_NAME);
+       strcpy(info->version, VELOCITY_VERSION);
+       strcpy(info->bus_info, pci_name(vptr->pdev));
+}
+
+static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+       wol->supported = WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP;
+       wol->wolopts |= WAKE_MAGIC;
+       /*
+          if (vptr->wol_opts & VELOCITY_WOL_PHY)
+                  wol.wolopts|=WAKE_PHY;
+                        */
+       if (vptr->wol_opts & VELOCITY_WOL_UCAST)
+               wol->wolopts |= WAKE_UCAST;
+       if (vptr->wol_opts & VELOCITY_WOL_ARP)
+               wol->wolopts |= WAKE_ARP;
+       memcpy(&wol->sopass, vptr->wol_passwd, 6);
+}
+
+static int velocity_ethtool_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+
+       if (!(wol->wolopts & (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP)))
+               return -EFAULT;
+       vptr->wol_opts = VELOCITY_WOL_MAGIC;
+
+       /*
+          if (wol.wolopts & WAKE_PHY) {
+          vptr->wol_opts|=VELOCITY_WOL_PHY;
+          vptr->flags |=VELOCITY_FLAGS_WOL_ENABLED;
+          }
+        */
+
+       if (wol->wolopts & WAKE_MAGIC) {
+               vptr->wol_opts |= VELOCITY_WOL_MAGIC;
+               vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
+       }
+       if (wol->wolopts & WAKE_UCAST) {
+               vptr->wol_opts |= VELOCITY_WOL_UCAST;
+               vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
+       }
+       if (wol->wolopts & WAKE_ARP) {
+               vptr->wol_opts |= VELOCITY_WOL_ARP;
+               vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
+       }
+       memcpy(vptr->wol_passwd, wol->sopass, 6);
+       return 0;
+}
+
+static u32 velocity_get_msglevel(struct net_device *dev)
+{
+       return msglevel;
+}
+
+static void velocity_set_msglevel(struct net_device *dev, u32 value)
+{
+        msglevel = value;
+}
+
+static int get_pending_timer_val(int val)
+{
+       int mult_bits = val >> 6;
+       int mult = 1;
+
+       switch (mult_bits)
+       {
+       case 1:
+               mult = 4; break;
+       case 2:
+               mult = 16; break;
+       case 3:
+               mult = 64; break;
+       case 0:
+       default:
+               break;
+       }
+
+       return (val & 0x3f) * mult;
+}
+
+static void set_pending_timer_val(int *val, u32 us)
+{
+       u8 mult = 0;
+       u8 shift = 0;
+
+       if (us >= 0x3f) {
+               mult = 1; /* mult with 4 */
+               shift = 2;
+       }
+       if (us >= 0x3f * 4) {
+               mult = 2; /* mult with 16 */
+               shift = 4;
+       }
+       if (us >= 0x3f * 16) {
+               mult = 3; /* mult with 64 */
+               shift = 6;
+       }
+
+       *val = (mult << 6) | ((us >> shift) & 0x3f);
+}
+
+
+static int velocity_get_coalesce(struct net_device *dev,
+               struct ethtool_coalesce *ecmd)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+
+       ecmd->tx_max_coalesced_frames = vptr->options.tx_intsup;
+       ecmd->rx_max_coalesced_frames = vptr->options.rx_intsup;
+
+       ecmd->rx_coalesce_usecs = get_pending_timer_val(vptr->options.rxqueue_timer);
+       ecmd->tx_coalesce_usecs = get_pending_timer_val(vptr->options.txqueue_timer);
+
+       return 0;
+}
+
+static int velocity_set_coalesce(struct net_device *dev,
+               struct ethtool_coalesce *ecmd)
+{
+       struct velocity_info *vptr = netdev_priv(dev);
+       int max_us = 0x3f * 64;
+       unsigned long flags;
+
+       /* 6 bits of  */
+       if (ecmd->tx_coalesce_usecs > max_us)
+               return -EINVAL;
+       if (ecmd->rx_coalesce_usecs > max_us)
+               return -EINVAL;
+
+       if (ecmd->tx_max_coalesced_frames > 0xff)
+               return -EINVAL;
+       if (ecmd->rx_max_coalesced_frames > 0xff)
+               return -EINVAL;
+
+       vptr->options.rx_intsup = ecmd->rx_max_coalesced_frames;
+       vptr->options.tx_intsup = ecmd->tx_max_coalesced_frames;
+
+       set_pending_timer_val(&vptr->options.rxqueue_timer,
+                       ecmd->rx_coalesce_usecs);
+       set_pending_timer_val(&vptr->options.txqueue_timer,
+                       ecmd->tx_coalesce_usecs);
+
+       /* Setup the interrupt suppression and queue timers */
+       spin_lock_irqsave(&vptr->lock, flags);
+       mac_disable_int(vptr->mac_regs);
+       setup_adaptive_interrupts(vptr);
+       setup_queue_timers(vptr);
+
+       mac_write_int_mask(vptr->int_mask, vptr->mac_regs);
+       mac_clear_isr(vptr->mac_regs);
+       mac_enable_int(vptr->mac_regs);
+       spin_unlock_irqrestore(&vptr->lock, flags);
+
+       return 0;
+}
+
+static const char velocity_gstrings[][ETH_GSTRING_LEN] = {
+       "rx_all",
+       "rx_ok",
+       "tx_ok",
+       "rx_error",
+       "rx_runt_ok",
+       "rx_runt_err",
+       "rx_64",
+       "tx_64",
+       "rx_65_to_127",
+       "tx_65_to_127",
+       "rx_128_to_255",
+       "tx_128_to_255",
+       "rx_256_to_511",
+       "tx_256_to_511",
+       "rx_512_to_1023",
+       "tx_512_to_1023",
+       "rx_1024_to_1518",
+       "tx_1024_to_1518",
+       "tx_ether_collisions",
+       "rx_crc_errors",
+       "rx_jumbo",
+       "tx_jumbo",
+       "rx_mac_control_frames",
+       "tx_mac_control_frames",
+       "rx_frame_alignement_errors",
+       "rx_long_ok",
+       "rx_long_err",
+       "tx_sqe_errors",
+       "rx_no_buf",
+       "rx_symbol_errors",
+       "in_range_length_errors",
+       "late_collisions"
+};
+
+static void velocity_get_strings(struct net_device *dev, u32 sset, u8 *data)
+{
+       switch (sset) {
+       case ETH_SS_STATS:
+               memcpy(data, *velocity_gstrings, sizeof(velocity_gstrings));
+               break;
+       }
+}
+
+static int velocity_get_sset_count(struct net_device *dev, int sset)
+{
+       switch (sset) {
+       case ETH_SS_STATS:
+               return ARRAY_SIZE(velocity_gstrings);
+       default:
+               return -EOPNOTSUPP;
+       }
+}
+
+static void velocity_get_ethtool_stats(struct net_device *dev,
+                                      struct ethtool_stats *stats, u64 *data)
+{
+       if (netif_running(dev)) {
+               struct velocity_info *vptr = netdev_priv(dev);
+               u32 *p = vptr->mib_counter;
+               int i;
+
+               spin_lock_irq(&vptr->lock);
+               velocity_update_hw_mibs(vptr);
+               spin_unlock_irq(&vptr->lock);
+
+               for (i = 0; i < ARRAY_SIZE(velocity_gstrings); i++)
+                       *data++ = *p++;
+       }
+}
+
+static const struct ethtool_ops velocity_ethtool_ops = {
+       .get_settings           = velocity_get_settings,
+       .set_settings           = velocity_set_settings,
+       .get_drvinfo            = velocity_get_drvinfo,
+       .get_wol                = velocity_ethtool_get_wol,
+       .set_wol                = velocity_ethtool_set_wol,
+       .get_msglevel           = velocity_get_msglevel,
+       .set_msglevel           = velocity_set_msglevel,
+       .get_link               = velocity_get_link,
+       .get_strings            = velocity_get_strings,
+       .get_sset_count         = velocity_get_sset_count,
+       .get_ethtool_stats      = velocity_get_ethtool_stats,
+       .get_coalesce           = velocity_get_coalesce,
+       .set_coalesce           = velocity_set_coalesce,
+       .begin                  = velocity_ethtool_up,
+       .complete               = velocity_ethtool_down
+};
+
+#if defined(CONFIG_PM) && defined(CONFIG_INET)
+static int velocity_netdev_event(struct notifier_block *nb, unsigned long notification, void *ptr)
+{
+       struct in_ifaddr *ifa = ptr;
+       struct net_device *dev = ifa->ifa_dev->dev;
+
+       if (dev_net(dev) == &init_net &&
+           dev->netdev_ops == &velocity_netdev_ops)
+               velocity_get_ip(netdev_priv(dev));
+
+       return NOTIFY_DONE;
+}
+
+static struct notifier_block velocity_inetaddr_notifier = {
+       .notifier_call  = velocity_netdev_event,
+};
+
+static void velocity_register_notifier(void)
+{
+       register_inetaddr_notifier(&velocity_inetaddr_notifier);
+}
+
+static void velocity_unregister_notifier(void)
+{
+       unregister_inetaddr_notifier(&velocity_inetaddr_notifier);
+}
+
+#else
+
+#define velocity_register_notifier()   do {} while (0)
+#define velocity_unregister_notifier() do {} while (0)
+
+#endif /* defined(CONFIG_PM) && defined(CONFIG_INET) */
+
+/**
+ *     velocity_init_module    -       load time function
+ *
+ *     Called when the velocity module is loaded. The PCI driver
+ *     is registered with the PCI layer, and in turn will call
+ *     the probe functions for each velocity adapter installed
+ *     in the system.
+ */
+static int __init velocity_init_module(void)
+{
+       int ret;
+
+       velocity_register_notifier();
+       ret = pci_register_driver(&velocity_driver);
+       if (ret < 0)
+               velocity_unregister_notifier();
+       return ret;
+}
+
+/**
+ *     velocity_cleanup        -       module unload
+ *
+ *     When the velocity hardware is unloaded this function is called.
+ *     It will clean up the notifiers and the unregister the PCI
+ *     driver interface for this hardware. This in turn cleans up
+ *     all discovered interfaces before returning from the function
+ */
+static void __exit velocity_cleanup_module(void)
+{
+       velocity_unregister_notifier();
+       pci_unregister_driver(&velocity_driver);
+}
+
+module_init(velocity_init_module);
+module_exit(velocity_cleanup_module);
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
new file mode 100644 (file)
index 0000000..4cb9f13
--- /dev/null
@@ -0,0 +1,1579 @@
+/*
+ * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
+ * All rights reserved.
+ *
+ * This software may be redistributed and/or modified under
+ * the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * File: via-velocity.h
+ *
+ * Purpose: Header file to define driver's private structures.
+ *
+ * Author: Chuang Liang-Shing, AJ Jiang
+ *
+ * Date: Jan 24, 2003
+ */
+
+
+#ifndef VELOCITY_H
+#define VELOCITY_H
+
+#define VELOCITY_TX_CSUM_SUPPORT
+
+#define VELOCITY_NAME          "via-velocity"
+#define VELOCITY_FULL_DRV_NAM  "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver"
+#define VELOCITY_VERSION       "1.15"
+
+#define VELOCITY_IO_SIZE       256
+#define VELOCITY_NAPI_WEIGHT   64
+
+#define PKT_BUF_SZ          1540
+
+#define MAX_UNITS           8
+#define OPTION_DEFAULT      { [0 ... MAX_UNITS-1] = -1}
+
+#define REV_ID_VT6110       (0)
+
+#define BYTE_REG_BITS_ON(x,p)       do { writeb(readb((p))|(x),(p));} while (0)
+#define WORD_REG_BITS_ON(x,p)       do { writew(readw((p))|(x),(p));} while (0)
+#define DWORD_REG_BITS_ON(x,p)      do { writel(readl((p))|(x),(p));} while (0)
+
+#define BYTE_REG_BITS_IS_ON(x,p)    (readb((p)) & (x))
+#define WORD_REG_BITS_IS_ON(x,p)    (readw((p)) & (x))
+#define DWORD_REG_BITS_IS_ON(x,p)   (readl((p)) & (x))
+
+#define BYTE_REG_BITS_OFF(x,p)      do { writeb(readb((p)) & (~(x)),(p));} while (0)
+#define WORD_REG_BITS_OFF(x,p)      do { writew(readw((p)) & (~(x)),(p));} while (0)
+#define DWORD_REG_BITS_OFF(x,p)     do { writel(readl((p)) & (~(x)),(p));} while (0)
+
+#define BYTE_REG_BITS_SET(x,m,p)    do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
+#define WORD_REG_BITS_SET(x,m,p)    do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
+#define DWORD_REG_BITS_SET(x,m,p)   do { writel( (readl((p)) & (~(m)))|(x),(p));}  while (0)
+
+#define VAR_USED(p)     do {(p)=(p);} while (0)
+
+/*
+ * Purpose: Structures for MAX RX/TX descriptors.
+ */
+
+
+#define B_OWNED_BY_CHIP     1
+#define B_OWNED_BY_HOST     0
+
+/*
+ * Bits in the RSR0 register
+ */
+
+#define RSR_DETAG      cpu_to_le16(0x0080)
+#define RSR_SNTAG      cpu_to_le16(0x0040)
+#define RSR_RXER       cpu_to_le16(0x0020)
+#define RSR_RL         cpu_to_le16(0x0010)
+#define RSR_CE         cpu_to_le16(0x0008)
+#define RSR_FAE                cpu_to_le16(0x0004)
+#define RSR_CRC                cpu_to_le16(0x0002)
+#define RSR_VIDM       cpu_to_le16(0x0001)
+
+/*
+ * Bits in the RSR1 register
+ */
+
+#define RSR_RXOK       cpu_to_le16(0x8000) // rx OK
+#define RSR_PFT                cpu_to_le16(0x4000) // Perfect filtering address match
+#define RSR_MAR                cpu_to_le16(0x2000) // MAC accept multicast address packet
+#define RSR_BAR                cpu_to_le16(0x1000) // MAC accept broadcast address packet
+#define RSR_PHY                cpu_to_le16(0x0800) // MAC accept physical address packet
+#define RSR_VTAG       cpu_to_le16(0x0400) // 802.1p/1q tagging packet indicator
+#define RSR_STP                cpu_to_le16(0x0200) // start of packet
+#define RSR_EDP                cpu_to_le16(0x0100) // end of packet
+
+/*
+ * Bits in the CSM register
+ */
+
+#define CSM_IPOK            0x40       //IP Checksum validation ok
+#define CSM_TUPOK           0x20       //TCP/UDP Checksum validation ok
+#define CSM_FRAG            0x10       //Fragment IP datagram
+#define CSM_IPKT            0x04       //Received an IP packet
+#define CSM_TCPKT           0x02       //Received a TCP packet
+#define CSM_UDPKT           0x01       //Received a UDP packet
+
+/*
+ * Bits in the TSR0 register
+ */
+
+#define TSR0_ABT       cpu_to_le16(0x0080) // Tx abort because of excessive collision
+#define TSR0_OWT       cpu_to_le16(0x0040) // Jumbo frame Tx abort
+#define TSR0_OWC       cpu_to_le16(0x0020) // Out of window collision
+#define TSR0_COLS      cpu_to_le16(0x0010) // experience collision in this transmit event
+#define TSR0_NCR3      cpu_to_le16(0x0008) // collision retry counter[3]
+#define TSR0_NCR2      cpu_to_le16(0x0004) // collision retry counter[2]
+#define TSR0_NCR1      cpu_to_le16(0x0002) // collision retry counter[1]
+#define TSR0_NCR0      cpu_to_le16(0x0001) // collision retry counter[0]
+#define TSR0_TERR      cpu_to_le16(0x8000) //
+#define TSR0_FDX       cpu_to_le16(0x4000) // current transaction is serviced by full duplex mode
+#define TSR0_GMII      cpu_to_le16(0x2000) // current transaction is serviced by GMII mode
+#define TSR0_LNKFL     cpu_to_le16(0x1000) // packet serviced during link down
+#define TSR0_SHDN      cpu_to_le16(0x0400) // shutdown case
+#define TSR0_CRS       cpu_to_le16(0x0200) // carrier sense lost
+#define TSR0_CDH       cpu_to_le16(0x0100) // AQE test fail (CD heartbeat)
+
+//
+// Bits in the TCR0 register
+//
+#define TCR0_TIC            0x80       // assert interrupt immediately while descriptor has been send complete
+#define TCR0_PIC            0x40       // priority interrupt request, INA# is issued over adaptive interrupt scheme
+#define TCR0_VETAG          0x20       // enable VLAN tag
+#define TCR0_IPCK           0x10       // request IP  checksum calculation.
+#define TCR0_UDPCK          0x08       // request UDP checksum calculation.
+#define TCR0_TCPCK          0x04       // request TCP checksum calculation.
+#define TCR0_JMBO           0x02       // indicate a jumbo packet in GMAC side
+#define TCR0_CRC            0x01       // disable CRC generation
+
+#define TCPLS_NORMAL        3
+#define TCPLS_START         2
+#define TCPLS_END           1
+#define TCPLS_MED           0
+
+
+// max transmit or receive buffer size
+#define CB_RX_BUF_SIZE     2048UL      // max buffer size
+                                       // NOTE: must be multiple of 4
+
+#define CB_MAX_RD_NUM       512        // MAX # of RD
+#define CB_MAX_TD_NUM       256        // MAX # of TD
+
+#define CB_INIT_RD_NUM_3119 128        // init # of RD, for setup VT3119
+#define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119
+
+#define CB_INIT_RD_NUM      128        // init # of RD, for setup default
+#define CB_INIT_TD_NUM      64 // init # of TD, for setup default
+
+// for 3119
+#define CB_TD_RING_NUM      4  // # of TD rings.
+#define CB_MAX_SEG_PER_PKT  7  // max data seg per packet (Tx)
+
+
+/*
+ *     If collisions excess 15 times , tx will abort, and
+ *     if tx fifo underflow, tx will fail
+ *     we should try to resend it
+ */
+
+#define CB_MAX_TX_ABORT_RETRY   3
+
+/*
+ *     Receive descriptor
+ */
+
+struct rdesc0 {
+       __le16 RSR;             /* Receive status */
+       __le16 len;             /* bits 0--13; bit 15 - owner */
+};
+
+struct rdesc1 {
+       __le16 PQTAG;
+       u8 CSM;
+       u8 IPKT;
+};
+
+enum {
+       RX_INTEN = cpu_to_le16(0x8000)
+};
+
+struct rx_desc {
+       struct rdesc0 rdesc0;
+       struct rdesc1 rdesc1;
+       __le32 pa_low;          /* Low 32 bit PCI address */
+       __le16 pa_high;         /* Next 16 bit PCI address (48 total) */
+       __le16 size;            /* bits 0--14 - frame size, bit 15 - enable int. */
+} __packed;
+
+/*
+ *     Transmit descriptor
+ */
+
+struct tdesc0 {
+       __le16 TSR;             /* Transmit status register */
+       __le16 len;             /* bits 0--13 - size of frame, bit 15 - owner */
+};
+
+struct tdesc1 {
+       __le16 vlan;
+       u8 TCR;
+       u8 cmd;                 /* bits 0--1 - TCPLS, bits 4--7 - CMDZ */
+} __packed;
+
+enum {
+       TD_QUEUE = cpu_to_le16(0x8000)
+};
+
+struct td_buf {
+       __le32 pa_low;
+       __le16 pa_high;
+       __le16 size;            /* bits 0--13 - size, bit 15 - queue */
+} __packed;
+
+struct tx_desc {
+       struct tdesc0 tdesc0;
+       struct tdesc1 tdesc1;
+       struct td_buf td_buf[7];
+};
+
+struct velocity_rd_info {
+       struct sk_buff *skb;
+       dma_addr_t skb_dma;
+};
+
+/*
+ *     Used to track transmit side buffers.
+ */
+
+struct velocity_td_info {
+       struct sk_buff *skb;
+       int nskb_dma;
+       dma_addr_t skb_dma[7];
+};
+
+enum  velocity_owner {
+       OWNED_BY_HOST = 0,
+       OWNED_BY_NIC = cpu_to_le16(0x8000)
+};
+
+
+/*
+ *     MAC registers and macros.
+ */
+
+
+#define MCAM_SIZE           64
+#define VCAM_SIZE           64
+#define TX_QUEUE_NO         4
+
+#define MAX_HW_MIB_COUNTER  32
+#define VELOCITY_MIN_MTU    (64)
+#define VELOCITY_MAX_MTU    (9000)
+
+/*
+ *     Registers in the MAC
+ */
+
+#define MAC_REG_PAR         0x00       // physical address
+#define MAC_REG_RCR         0x06
+#define MAC_REG_TCR         0x07
+#define MAC_REG_CR0_SET     0x08
+#define MAC_REG_CR1_SET     0x09
+#define MAC_REG_CR2_SET     0x0A
+#define MAC_REG_CR3_SET     0x0B
+#define MAC_REG_CR0_CLR     0x0C
+#define MAC_REG_CR1_CLR     0x0D
+#define MAC_REG_CR2_CLR     0x0E
+#define MAC_REG_CR3_CLR     0x0F
+#define MAC_REG_MAR         0x10
+#define MAC_REG_CAM         0x10
+#define MAC_REG_DEC_BASE_HI 0x18
+#define MAC_REG_DBF_BASE_HI 0x1C
+#define MAC_REG_ISR_CTL     0x20
+#define MAC_REG_ISR_HOTMR   0x20
+#define MAC_REG_ISR_TSUPTHR 0x20
+#define MAC_REG_ISR_RSUPTHR 0x20
+#define MAC_REG_ISR_CTL1    0x21
+#define MAC_REG_TXE_SR      0x22
+#define MAC_REG_RXE_SR      0x23
+#define MAC_REG_ISR         0x24
+#define MAC_REG_ISR0        0x24
+#define MAC_REG_ISR1        0x25
+#define MAC_REG_ISR2        0x26
+#define MAC_REG_ISR3        0x27
+#define MAC_REG_IMR         0x28
+#define MAC_REG_IMR0        0x28
+#define MAC_REG_IMR1        0x29
+#define MAC_REG_IMR2        0x2A
+#define MAC_REG_IMR3        0x2B
+#define MAC_REG_TDCSR_SET   0x30
+#define MAC_REG_RDCSR_SET   0x32
+#define MAC_REG_TDCSR_CLR   0x34
+#define MAC_REG_RDCSR_CLR   0x36
+#define MAC_REG_RDBASE_LO   0x38
+#define MAC_REG_RDINDX      0x3C
+#define MAC_REG_TDBASE_LO   0x40
+#define MAC_REG_RDCSIZE     0x50
+#define MAC_REG_TDCSIZE     0x52
+#define MAC_REG_TDINDX      0x54
+#define MAC_REG_TDIDX0      0x54
+#define MAC_REG_TDIDX1      0x56
+#define MAC_REG_TDIDX2      0x58
+#define MAC_REG_TDIDX3      0x5A
+#define MAC_REG_PAUSE_TIMER 0x5C
+#define MAC_REG_RBRDU       0x5E
+#define MAC_REG_FIFO_TEST0  0x60
+#define MAC_REG_FIFO_TEST1  0x64
+#define MAC_REG_CAMADDR     0x68
+#define MAC_REG_CAMCR       0x69
+#define MAC_REG_GFTEST      0x6A
+#define MAC_REG_FTSTCMD     0x6B
+#define MAC_REG_MIICFG      0x6C
+#define MAC_REG_MIISR       0x6D
+#define MAC_REG_PHYSR0      0x6E
+#define MAC_REG_PHYSR1      0x6F
+#define MAC_REG_MIICR       0x70
+#define MAC_REG_MIIADR      0x71
+#define MAC_REG_MIIDATA     0x72
+#define MAC_REG_SOFT_TIMER0 0x74
+#define MAC_REG_SOFT_TIMER1 0x76
+#define MAC_REG_CFGA        0x78
+#define MAC_REG_CFGB        0x79
+#define MAC_REG_CFGC        0x7A
+#define MAC_REG_CFGD        0x7B
+#define MAC_REG_DCFG0       0x7C
+#define MAC_REG_DCFG1       0x7D
+#define MAC_REG_MCFG0       0x7E
+#define MAC_REG_MCFG1       0x7F
+
+#define MAC_REG_TBIST       0x80
+#define MAC_REG_RBIST       0x81
+#define MAC_REG_PMCC        0x82
+#define MAC_REG_STICKHW     0x83
+#define MAC_REG_MIBCR       0x84
+#define MAC_REG_EERSV       0x85
+#define MAC_REG_REVID       0x86
+#define MAC_REG_MIBREAD     0x88
+#define MAC_REG_BPMA        0x8C
+#define MAC_REG_EEWR_DATA   0x8C
+#define MAC_REG_BPMD_WR     0x8F
+#define MAC_REG_BPCMD       0x90
+#define MAC_REG_BPMD_RD     0x91
+#define MAC_REG_EECHKSUM    0x92
+#define MAC_REG_EECSR       0x93
+#define MAC_REG_EERD_DATA   0x94
+#define MAC_REG_EADDR       0x96
+#define MAC_REG_EMBCMD      0x97
+#define MAC_REG_JMPSR0      0x98
+#define MAC_REG_JMPSR1      0x99
+#define MAC_REG_JMPSR2      0x9A
+#define MAC_REG_JMPSR3      0x9B
+#define MAC_REG_CHIPGSR     0x9C
+#define MAC_REG_TESTCFG     0x9D
+#define MAC_REG_DEBUG       0x9E
+#define MAC_REG_CHIPGCR     0x9F       /* Chip Operation and Diagnostic Control */
+#define MAC_REG_WOLCR0_SET  0xA0
+#define MAC_REG_WOLCR1_SET  0xA1
+#define MAC_REG_PWCFG_SET   0xA2
+#define MAC_REG_WOLCFG_SET  0xA3
+#define MAC_REG_WOLCR0_CLR  0xA4
+#define MAC_REG_WOLCR1_CLR  0xA5
+#define MAC_REG_PWCFG_CLR   0xA6
+#define MAC_REG_WOLCFG_CLR  0xA7
+#define MAC_REG_WOLSR0_SET  0xA8
+#define MAC_REG_WOLSR1_SET  0xA9
+#define MAC_REG_WOLSR0_CLR  0xAC
+#define MAC_REG_WOLSR1_CLR  0xAD
+#define MAC_REG_PATRN_CRC0  0xB0
+#define MAC_REG_PATRN_CRC1  0xB2
+#define MAC_REG_PATRN_CRC2  0xB4
+#define MAC_REG_PATRN_CRC3  0xB6
+#define MAC_REG_PATRN_CRC4  0xB8
+#define MAC_REG_PATRN_CRC5  0xBA
+#define MAC_REG_PATRN_CRC6  0xBC
+#define MAC_REG_PATRN_CRC7  0xBE
+#define MAC_REG_BYTEMSK0_0  0xC0
+#define MAC_REG_BYTEMSK0_1  0xC4
+#define MAC_REG_BYTEMSK0_2  0xC8
+#define MAC_REG_BYTEMSK0_3  0xCC
+#define MAC_REG_BYTEMSK1_0  0xD0
+#define MAC_REG_BYTEMSK1_1  0xD4
+#define MAC_REG_BYTEMSK1_2  0xD8
+#define MAC_REG_BYTEMSK1_3  0xDC
+#define MAC_REG_BYTEMSK2_0  0xE0
+#define MAC_REG_BYTEMSK2_1  0xE4
+#define MAC_REG_BYTEMSK2_2  0xE8
+#define MAC_REG_BYTEMSK2_3  0xEC
+#define MAC_REG_BYTEMSK3_0  0xF0
+#define MAC_REG_BYTEMSK3_1  0xF4
+#define MAC_REG_BYTEMSK3_2  0xF8
+#define MAC_REG_BYTEMSK3_3  0xFC
+
+/*
+ *     Bits in the RCR register
+ */
+
+#define RCR_AS              0x80
+#define RCR_AP              0x40
+#define RCR_AL              0x20
+#define RCR_PROM            0x10
+#define RCR_AB              0x08
+#define RCR_AM              0x04
+#define RCR_AR              0x02
+#define RCR_SEP             0x01
+
+/*
+ *     Bits in the TCR register
+ */
+
+#define TCR_TB2BDIS         0x80
+#define TCR_COLTMC1         0x08
+#define TCR_COLTMC0         0x04
+#define TCR_LB1             0x02       /* loopback[1] */
+#define TCR_LB0             0x01       /* loopback[0] */
+
+/*
+ *     Bits in the CR0 register
+ */
+
+#define CR0_TXON            0x00000008UL
+#define CR0_RXON            0x00000004UL
+#define CR0_STOP            0x00000002UL       /* stop MAC, default = 1 */
+#define CR0_STRT            0x00000001UL       /* start MAC */
+#define CR0_SFRST           0x00008000UL       /* software reset */
+#define CR0_TM1EN           0x00004000UL
+#define CR0_TM0EN           0x00002000UL
+#define CR0_DPOLL           0x00000800UL       /* disable rx/tx auto polling */
+#define CR0_DISAU           0x00000100UL
+#define CR0_XONEN           0x00800000UL
+#define CR0_FDXTFCEN        0x00400000UL       /* full-duplex TX flow control enable */
+#define CR0_FDXRFCEN        0x00200000UL       /* full-duplex RX flow control enable */
+#define CR0_HDXFCEN         0x00100000UL       /* half-duplex flow control enable */
+#define CR0_XHITH1          0x00080000UL       /* TX XON high threshold 1 */
+#define CR0_XHITH0          0x00040000UL       /* TX XON high threshold 0 */
+#define CR0_XLTH1           0x00020000UL       /* TX pause frame low threshold 1 */
+#define CR0_XLTH0           0x00010000UL       /* TX pause frame low threshold 0 */
+#define CR0_GSPRST          0x80000000UL
+#define CR0_FORSRST         0x40000000UL
+#define CR0_FPHYRST         0x20000000UL
+#define CR0_DIAG            0x10000000UL
+#define CR0_INTPCTL         0x04000000UL
+#define CR0_GINTMSK1        0x02000000UL
+#define CR0_GINTMSK0        0x01000000UL
+
+/*
+ *     Bits in the CR1 register
+ */
+
+#define CR1_SFRST           0x80       /* software reset */
+#define CR1_TM1EN           0x40
+#define CR1_TM0EN           0x20
+#define CR1_DPOLL           0x08       /* disable rx/tx auto polling */
+#define CR1_DISAU           0x01
+
+/*
+ *     Bits in the CR2 register
+ */
+
+#define CR2_XONEN           0x80
+#define CR2_FDXTFCEN        0x40       /* full-duplex TX flow control enable */
+#define CR2_FDXRFCEN        0x20       /* full-duplex RX flow control enable */
+#define CR2_HDXFCEN         0x10       /* half-duplex flow control enable */
+#define CR2_XHITH1          0x08       /* TX XON high threshold 1 */
+#define CR2_XHITH0          0x04       /* TX XON high threshold 0 */
+#define CR2_XLTH1           0x02       /* TX pause frame low threshold 1 */
+#define CR2_XLTH0           0x01       /* TX pause frame low threshold 0 */
+
+/*
+ *     Bits in the CR3 register
+ */
+
+#define CR3_GSPRST          0x80
+#define CR3_FORSRST         0x40
+#define CR3_FPHYRST         0x20
+#define CR3_DIAG            0x10
+#define CR3_INTPCTL         0x04
+#define CR3_GINTMSK1        0x02
+#define CR3_GINTMSK0        0x01
+
+#define ISRCTL_UDPINT       0x8000
+#define ISRCTL_TSUPDIS      0x4000
+#define ISRCTL_RSUPDIS      0x2000
+#define ISRCTL_PMSK1        0x1000
+#define ISRCTL_PMSK0        0x0800
+#define ISRCTL_INTPD        0x0400
+#define ISRCTL_HCRLD        0x0200
+#define ISRCTL_SCRLD        0x0100
+
+/*
+ *     Bits in the ISR_CTL1 register
+ */
+
+#define ISRCTL1_UDPINT      0x80
+#define ISRCTL1_TSUPDIS     0x40
+#define ISRCTL1_RSUPDIS     0x20
+#define ISRCTL1_PMSK1       0x10
+#define ISRCTL1_PMSK0       0x08
+#define ISRCTL1_INTPD       0x04
+#define ISRCTL1_HCRLD       0x02
+#define ISRCTL1_SCRLD       0x01
+
+/*
+ *     Bits in the TXE_SR register
+ */
+
+#define TXESR_TFDBS         0x08
+#define TXESR_TDWBS         0x04
+#define TXESR_TDRBS         0x02
+#define TXESR_TDSTR         0x01
+
+/*
+ *     Bits in the RXE_SR register
+ */
+
+#define RXESR_RFDBS         0x08
+#define RXESR_RDWBS         0x04
+#define RXESR_RDRBS         0x02
+#define RXESR_RDSTR         0x01
+
+/*
+ *     Bits in the ISR register
+ */
+
+#define ISR_ISR3            0x80000000UL
+#define ISR_ISR2            0x40000000UL
+#define ISR_ISR1            0x20000000UL
+#define ISR_ISR0            0x10000000UL
+#define ISR_TXSTLI          0x02000000UL
+#define ISR_RXSTLI          0x01000000UL
+#define ISR_HFLD            0x00800000UL
+#define ISR_UDPI            0x00400000UL
+#define ISR_MIBFI           0x00200000UL
+#define ISR_SHDNI           0x00100000UL
+#define ISR_PHYI            0x00080000UL
+#define ISR_PWEI            0x00040000UL
+#define ISR_TMR1I           0x00020000UL
+#define ISR_TMR0I           0x00010000UL
+#define ISR_SRCI            0x00008000UL
+#define ISR_LSTPEI          0x00004000UL
+#define ISR_LSTEI           0x00002000UL
+#define ISR_OVFI            0x00001000UL
+#define ISR_FLONI           0x00000800UL
+#define ISR_RACEI           0x00000400UL
+#define ISR_TXWB1I          0x00000200UL
+#define ISR_TXWB0I          0x00000100UL
+#define ISR_PTX3I           0x00000080UL
+#define ISR_PTX2I           0x00000040UL
+#define ISR_PTX1I           0x00000020UL
+#define ISR_PTX0I           0x00000010UL
+#define ISR_PTXI            0x00000008UL
+#define ISR_PRXI            0x00000004UL
+#define ISR_PPTXI           0x00000002UL
+#define ISR_PPRXI           0x00000001UL
+
+/*
+ *     Bits in the IMR register
+ */
+
+#define IMR_TXSTLM          0x02000000UL
+#define IMR_UDPIM           0x00400000UL
+#define IMR_MIBFIM          0x00200000UL
+#define IMR_SHDNIM          0x00100000UL
+#define IMR_PHYIM           0x00080000UL
+#define IMR_PWEIM           0x00040000UL
+#define IMR_TMR1IM          0x00020000UL
+#define IMR_TMR0IM          0x00010000UL
+
+#define IMR_SRCIM           0x00008000UL
+#define IMR_LSTPEIM         0x00004000UL
+#define IMR_LSTEIM          0x00002000UL
+#define IMR_OVFIM           0x00001000UL
+#define IMR_FLONIM          0x00000800UL
+#define IMR_RACEIM          0x00000400UL
+#define IMR_TXWB1IM         0x00000200UL
+#define IMR_TXWB0IM         0x00000100UL
+
+#define IMR_PTX3IM          0x00000080UL
+#define IMR_PTX2IM          0x00000040UL
+#define IMR_PTX1IM          0x00000020UL
+#define IMR_PTX0IM          0x00000010UL
+#define IMR_PTXIM           0x00000008UL
+#define IMR_PRXIM           0x00000004UL
+#define IMR_PPTXIM          0x00000002UL
+#define IMR_PPRXIM          0x00000001UL
+
+/* 0x0013FB0FUL  =  initial value of IMR */
+
+#define INT_MASK_DEF        (IMR_PPTXIM|IMR_PPRXIM|IMR_PTXIM|IMR_PRXIM|\
+                            IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM|\
+                            IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\
+                            IMR_SHDNIM|IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM)
+
+/*
+ *     Bits in the TDCSR0/1, RDCSR0 register
+ */
+
+#define TRDCSR_DEAD         0x0008
+#define TRDCSR_WAK          0x0004
+#define TRDCSR_ACT          0x0002
+#define TRDCSR_RUN         0x0001
+
+/*
+ *     Bits in the CAMADDR register
+ */
+
+#define CAMADDR_CAMEN       0x80
+#define CAMADDR_VCAMSL      0x40
+
+/*
+ *     Bits in the CAMCR register
+ */
+
+#define CAMCR_PS1           0x80
+#define CAMCR_PS0           0x40
+#define CAMCR_AITRPKT       0x20
+#define CAMCR_AITR16        0x10
+#define CAMCR_CAMRD         0x08
+#define CAMCR_CAMWR         0x04
+#define CAMCR_PS_CAM_MASK   0x40
+#define CAMCR_PS_CAM_DATA   0x80
+#define CAMCR_PS_MAR        0x00
+
+/*
+ *     Bits in the MIICFG register
+ */
+
+#define MIICFG_MPO1         0x80
+#define MIICFG_MPO0         0x40
+#define MIICFG_MFDC         0x20
+
+/*
+ *     Bits in the MIISR register
+ */
+
+#define MIISR_MIDLE         0x80
+
+/*
+ *      Bits in the PHYSR0 register
+ */
+
+#define PHYSR0_PHYRST       0x80
+#define PHYSR0_LINKGD       0x40
+#define PHYSR0_FDPX         0x10
+#define PHYSR0_SPDG         0x08
+#define PHYSR0_SPD10        0x04
+#define PHYSR0_RXFLC        0x02
+#define PHYSR0_TXFLC        0x01
+
+/*
+ *     Bits in the PHYSR1 register
+ */
+
+#define PHYSR1_PHYTBI       0x01
+
+/*
+ *     Bits in the MIICR register
+ */
+
+#define MIICR_MAUTO         0x80
+#define MIICR_RCMD          0x40
+#define MIICR_WCMD          0x20
+#define MIICR_MDPM          0x10
+#define MIICR_MOUT          0x08
+#define MIICR_MDO           0x04
+#define MIICR_MDI           0x02
+#define MIICR_MDC           0x01
+
+/*
+ *     Bits in the MIIADR register
+ */
+
+#define MIIADR_SWMPL        0x80
+
+/*
+ *     Bits in the CFGA register
+ */
+
+#define CFGA_PMHCTG         0x08
+#define CFGA_GPIO1PD        0x04
+#define CFGA_ABSHDN         0x02
+#define CFGA_PACPI          0x01
+
+/*
+ *     Bits in the CFGB register
+ */
+
+#define CFGB_GTCKOPT        0x80
+#define CFGB_MIIOPT         0x40
+#define CFGB_CRSEOPT        0x20
+#define CFGB_OFSET          0x10
+#define CFGB_CRANDOM        0x08
+#define CFGB_CAP            0x04
+#define CFGB_MBA            0x02
+#define CFGB_BAKOPT         0x01
+
+/*
+ *     Bits in the CFGC register
+ */
+
+#define CFGC_EELOAD         0x80
+#define CFGC_BROPT          0x40
+#define CFGC_DLYEN          0x20
+#define CFGC_DTSEL          0x10
+#define CFGC_BTSEL          0x08
+#define CFGC_BPS2           0x04       /* bootrom select[2] */
+#define CFGC_BPS1           0x02       /* bootrom select[1] */
+#define CFGC_BPS0           0x01       /* bootrom select[0] */
+
+/*
+ * Bits in the CFGD register
+ */
+
+#define CFGD_IODIS          0x80
+#define CFGD_MSLVDACEN      0x40
+#define CFGD_CFGDACEN       0x20
+#define CFGD_PCI64EN        0x10
+#define CFGD_HTMRL4         0x08
+
+/*
+ *     Bits in the DCFG1 register
+ */
+
+#define DCFG_XMWI           0x8000
+#define DCFG_XMRM           0x4000
+#define DCFG_XMRL           0x2000
+#define DCFG_PERDIS         0x1000
+#define DCFG_MRWAIT         0x0400
+#define DCFG_MWWAIT         0x0200
+#define DCFG_LATMEN         0x0100
+
+/*
+ *     Bits in the MCFG0 register
+ */
+
+#define MCFG_RXARB          0x0080
+#define MCFG_RFT1           0x0020
+#define MCFG_RFT0           0x0010
+#define MCFG_LOWTHOPT       0x0008
+#define MCFG_PQEN           0x0004
+#define MCFG_RTGOPT         0x0002
+#define MCFG_VIDFR          0x0001
+
+/*
+ *     Bits in the MCFG1 register
+ */
+
+#define MCFG_TXARB          0x8000
+#define MCFG_TXQBK1         0x0800
+#define MCFG_TXQBK0         0x0400
+#define MCFG_TXQNOBK        0x0200
+#define MCFG_SNAPOPT        0x0100
+
+/*
+ *     Bits in the PMCC  register
+ */
+
+#define PMCC_DSI            0x80
+#define PMCC_D2_DIS         0x40
+#define PMCC_D1_DIS         0x20
+#define PMCC_D3C_EN         0x10
+#define PMCC_D3H_EN         0x08
+#define PMCC_D2_EN          0x04
+#define PMCC_D1_EN          0x02
+#define PMCC_D0_EN          0x01
+
+/*
+ *     Bits in STICKHW
+ */
+
+#define STICKHW_SWPTAG      0x10
+#define STICKHW_WOLSR       0x08
+#define STICKHW_WOLEN       0x04
+#define STICKHW_DS1         0x02       /* R/W by software/cfg cycle */
+#define STICKHW_DS0         0x01       /* suspend well DS write port */
+
+/*
+ *     Bits in the MIBCR register
+ */
+
+#define MIBCR_MIBISTOK      0x80
+#define MIBCR_MIBISTGO      0x40
+#define MIBCR_MIBINC        0x20
+#define MIBCR_MIBHI         0x10
+#define MIBCR_MIBFRZ        0x08
+#define MIBCR_MIBFLSH       0x04
+#define MIBCR_MPTRINI       0x02
+#define MIBCR_MIBCLR        0x01
+
+/*
+ *     Bits in the EERSV register
+ */
+
+#define EERSV_BOOT_RPL      ((u8) 0x01)         /* Boot method selection for VT6110 */
+
+#define EERSV_BOOT_MASK     ((u8) 0x06)
+#define EERSV_BOOT_INT19    ((u8) 0x00)
+#define EERSV_BOOT_INT18    ((u8) 0x02)
+#define EERSV_BOOT_LOCAL    ((u8) 0x04)
+#define EERSV_BOOT_BEV      ((u8) 0x06)
+
+
+/*
+ *     Bits in BPCMD
+ */
+
+#define BPCMD_BPDNE         0x80
+#define BPCMD_EBPWR         0x02
+#define BPCMD_EBPRD         0x01
+
+/*
+ *     Bits in the EECSR register
+ */
+
+#define EECSR_EMBP          0x40       /* eeprom embedded programming */
+#define EECSR_RELOAD        0x20       /* eeprom content reload */
+#define EECSR_DPM           0x10       /* eeprom direct programming */
+#define EECSR_ECS           0x08       /* eeprom CS pin */
+#define EECSR_ECK           0x04       /* eeprom CK pin */
+#define EECSR_EDI           0x02       /* eeprom DI pin */
+#define EECSR_EDO           0x01       /* eeprom DO pin */
+
+/*
+ *     Bits in the EMBCMD register
+ */
+
+#define EMBCMD_EDONE        0x80
+#define EMBCMD_EWDIS        0x08
+#define EMBCMD_EWEN         0x04
+#define EMBCMD_EWR          0x02
+#define EMBCMD_ERD          0x01
+
+/*
+ *     Bits in TESTCFG register
+ */
+
+#define TESTCFG_HBDIS       0x80
+
+/*
+ *     Bits in CHIPGCR register
+ */
+
+#define CHIPGCR_FCGMII      0x80       /* force GMII (else MII only) */
+#define CHIPGCR_FCFDX       0x40       /* force full duplex */
+#define CHIPGCR_FCRESV      0x20
+#define CHIPGCR_FCMODE      0x10       /* enable MAC forced mode */
+#define CHIPGCR_LPSOPT      0x08
+#define CHIPGCR_TM1US       0x04
+#define CHIPGCR_TM0US       0x02
+#define CHIPGCR_PHYINTEN    0x01
+
+/*
+ *     Bits in WOLCR0
+ */
+
+#define WOLCR_MSWOLEN7      0x0080     /* enable pattern match filtering */
+#define WOLCR_MSWOLEN6      0x0040
+#define WOLCR_MSWOLEN5      0x0020
+#define WOLCR_MSWOLEN4      0x0010
+#define WOLCR_MSWOLEN3      0x0008
+#define WOLCR_MSWOLEN2      0x0004
+#define WOLCR_MSWOLEN1      0x0002
+#define WOLCR_MSWOLEN0      0x0001
+#define WOLCR_ARP_EN        0x0001
+
+/*
+ *     Bits in WOLCR1
+ */
+
+#define WOLCR_LINKOFF_EN      0x0800   /* link off detected enable */
+#define WOLCR_LINKON_EN       0x0400   /* link on detected enable */
+#define WOLCR_MAGIC_EN        0x0200   /* magic packet filter enable */
+#define WOLCR_UNICAST_EN      0x0100   /* unicast filter enable */
+
+
+/*
+ *     Bits in PWCFG
+ */
+
+#define PWCFG_PHYPWOPT          0x80   /* internal MII I/F timing */
+#define PWCFG_PCISTICK          0x40   /* PCI sticky R/W enable */
+#define PWCFG_WOLTYPE           0x20   /* pulse(1) or button (0) */
+#define PWCFG_LEGCY_WOL         0x10
+#define PWCFG_PMCSR_PME_SR      0x08
+#define PWCFG_PMCSR_PME_EN      0x04   /* control by PCISTICK */
+#define PWCFG_LEGACY_WOLSR      0x02   /* Legacy WOL_SR shadow */
+#define PWCFG_LEGACY_WOLEN      0x01   /* Legacy WOL_EN shadow */
+
+/*
+ *     Bits in WOLCFG
+ */
+
+#define WOLCFG_PMEOVR           0x80   /* for legacy use, force PMEEN always */
+#define WOLCFG_SAM              0x20   /* accept multicast case reset, default=0 */
+#define WOLCFG_SAB              0x10   /* accept broadcast case reset, default=0 */
+#define WOLCFG_SMIIACC          0x08   /* ?? */
+#define WOLCFG_SGENWH           0x02
+#define WOLCFG_PHYINTEN         0x01   /* 0:PHYINT trigger enable, 1:use internal MII
+                                         to report status change */
+/*
+ *     Bits in WOLSR1
+ */
+
+#define WOLSR_LINKOFF_INT      0x0800
+#define WOLSR_LINKON_INT       0x0400
+#define WOLSR_MAGIC_INT        0x0200
+#define WOLSR_UNICAST_INT      0x0100
+
+/*
+ *     Ethernet address filter type
+ */
+
+#define PKT_TYPE_NONE               0x0000     /* Turn off receiver */
+#define PKT_TYPE_DIRECTED           0x0001     /* obselete, directed address is always accepted */
+#define PKT_TYPE_MULTICAST          0x0002
+#define PKT_TYPE_ALL_MULTICAST      0x0004
+#define PKT_TYPE_BROADCAST          0x0008
+#define PKT_TYPE_PROMISCUOUS        0x0020
+#define PKT_TYPE_LONG               0x2000     /* NOTE.... the definition of LONG is >2048 bytes in our chip */
+#define PKT_TYPE_RUNT               0x4000
+#define PKT_TYPE_ERROR              0x8000     /* Accept error packets, e.g. CRC error */
+
+/*
+ *     Loopback mode
+ */
+
+#define MAC_LB_NONE         0x00
+#define MAC_LB_INTERNAL     0x01
+#define MAC_LB_EXTERNAL     0x02
+
+/*
+ *     Enabled mask value of irq
+ */
+
+#if defined(_SIM)
+#define IMR_MASK_VALUE      0x0033FF0FUL       /* initial value of IMR
+                                                  set IMR0 to 0x0F according to spec */
+
+#else
+#define IMR_MASK_VALUE      0x0013FB0FUL       /* initial value of IMR
+                                                  ignore MIBFI,RACEI to
+                                                  reduce intr. frequency
+                                                  NOTE.... do not enable NoBuf int mask at driver driver
+                                                     when (1) NoBuf -> RxThreshold = SF
+                                                          (2) OK    -> RxThreshold = original value
+                                                */
+#endif
+
+/*
+ *     Revision id
+ */
+
+#define REV_ID_VT3119_A0       0x00
+#define REV_ID_VT3119_A1       0x01
+#define REV_ID_VT3216_A0       0x10
+
+/*
+ *     Max time out delay time
+ */
+
+#define W_MAX_TIMEOUT       0x0FFFU
+
+
+/*
+ *     MAC registers as a structure. Cannot be directly accessed this
+ *     way but generates offsets for readl/writel() calls
+ */
+
+struct mac_regs {
+       volatile u8 PAR[6];             /* 0x00 */
+       volatile u8 RCR;
+       volatile u8 TCR;
+
+       volatile __le32 CR0Set;         /* 0x08 */
+       volatile __le32 CR0Clr;         /* 0x0C */
+
+       volatile u8 MARCAM[8];          /* 0x10 */
+
+       volatile __le32 DecBaseHi;      /* 0x18 */
+       volatile __le16 DbfBaseHi;      /* 0x1C */
+       volatile __le16 reserved_1E;
+
+       volatile __le16 ISRCTL;         /* 0x20 */
+       volatile u8 TXESR;
+       volatile u8 RXESR;
+
+       volatile __le32 ISR;            /* 0x24 */
+       volatile __le32 IMR;
+
+       volatile __le32 TDStatusPort;   /* 0x2C */
+
+       volatile __le16 TDCSRSet;       /* 0x30 */
+       volatile u8 RDCSRSet;
+       volatile u8 reserved_33;
+       volatile __le16 TDCSRClr;
+       volatile u8 RDCSRClr;
+       volatile u8 reserved_37;
+
+       volatile __le32 RDBaseLo;       /* 0x38 */
+       volatile __le16 RDIdx;          /* 0x3C */
+       volatile u8 TQETMR;             /* 0x3E, VT3216 and above only */
+       volatile u8 RQETMR;             /* 0x3F, VT3216 and above only */
+
+       volatile __le32 TDBaseLo[4];    /* 0x40 */
+
+       volatile __le16 RDCSize;        /* 0x50 */
+       volatile __le16 TDCSize;        /* 0x52 */
+       volatile __le16 TDIdx[4];       /* 0x54 */
+       volatile __le16 tx_pause_timer; /* 0x5C */
+       volatile __le16 RBRDU;          /* 0x5E */
+
+       volatile __le32 FIFOTest0;      /* 0x60 */
+       volatile __le32 FIFOTest1;      /* 0x64 */
+
+       volatile u8 CAMADDR;            /* 0x68 */
+       volatile u8 CAMCR;              /* 0x69 */
+       volatile u8 GFTEST;             /* 0x6A */
+       volatile u8 FTSTCMD;            /* 0x6B */
+
+       volatile u8 MIICFG;             /* 0x6C */
+       volatile u8 MIISR;
+       volatile u8 PHYSR0;
+       volatile u8 PHYSR1;
+       volatile u8 MIICR;
+       volatile u8 MIIADR;
+       volatile __le16 MIIDATA;
+
+       volatile __le16 SoftTimer0;     /* 0x74 */
+       volatile __le16 SoftTimer1;
+
+       volatile u8 CFGA;               /* 0x78 */
+       volatile u8 CFGB;
+       volatile u8 CFGC;
+       volatile u8 CFGD;
+
+       volatile __le16 DCFG;           /* 0x7C */
+       volatile __le16 MCFG;
+
+       volatile u8 TBIST;              /* 0x80 */
+       volatile u8 RBIST;
+       volatile u8 PMCPORT;
+       volatile u8 STICKHW;
+
+       volatile u8 MIBCR;              /* 0x84 */
+       volatile u8 reserved_85;
+       volatile u8 rev_id;
+       volatile u8 PORSTS;
+
+       volatile __le32 MIBData;        /* 0x88 */
+
+       volatile __le16 EEWrData;
+
+       volatile u8 reserved_8E;
+       volatile u8 BPMDWr;
+       volatile u8 BPCMD;
+       volatile u8 BPMDRd;
+
+       volatile u8 EECHKSUM;           /* 0x92 */
+       volatile u8 EECSR;
+
+       volatile __le16 EERdData;       /* 0x94 */
+       volatile u8 EADDR;
+       volatile u8 EMBCMD;
+
+
+       volatile u8 JMPSR0;             /* 0x98 */
+       volatile u8 JMPSR1;
+       volatile u8 JMPSR2;
+       volatile u8 JMPSR3;
+       volatile u8 CHIPGSR;            /* 0x9C */
+       volatile u8 TESTCFG;
+       volatile u8 DEBUG;
+       volatile u8 CHIPGCR;
+
+       volatile __le16 WOLCRSet;       /* 0xA0 */
+       volatile u8 PWCFGSet;
+       volatile u8 WOLCFGSet;
+
+       volatile __le16 WOLCRClr;       /* 0xA4 */
+       volatile u8 PWCFGCLR;
+       volatile u8 WOLCFGClr;
+
+       volatile __le16 WOLSRSet;       /* 0xA8 */
+       volatile __le16 reserved_AA;
+
+       volatile __le16 WOLSRClr;       /* 0xAC */
+       volatile __le16 reserved_AE;
+
+       volatile __le16 PatternCRC[8];  /* 0xB0 */
+       volatile __le32 ByteMask[4][4]; /* 0xC0 */
+};
+
+
+enum hw_mib {
+       HW_MIB_ifRxAllPkts = 0,
+       HW_MIB_ifRxOkPkts,
+       HW_MIB_ifTxOkPkts,
+       HW_MIB_ifRxErrorPkts,
+       HW_MIB_ifRxRuntOkPkt,
+       HW_MIB_ifRxRuntErrPkt,
+       HW_MIB_ifRx64Pkts,
+       HW_MIB_ifTx64Pkts,
+       HW_MIB_ifRx65To127Pkts,
+       HW_MIB_ifTx65To127Pkts,
+       HW_MIB_ifRx128To255Pkts,
+       HW_MIB_ifTx128To255Pkts,
+       HW_MIB_ifRx256To511Pkts,
+       HW_MIB_ifTx256To511Pkts,
+       HW_MIB_ifRx512To1023Pkts,
+       HW_MIB_ifTx512To1023Pkts,
+       HW_MIB_ifRx1024To1518Pkts,
+       HW_MIB_ifTx1024To1518Pkts,
+       HW_MIB_ifTxEtherCollisions,
+       HW_MIB_ifRxPktCRCE,
+       HW_MIB_ifRxJumboPkts,
+       HW_MIB_ifTxJumboPkts,
+       HW_MIB_ifRxMacControlFrames,
+       HW_MIB_ifTxMacControlFrames,
+       HW_MIB_ifRxPktFAE,
+       HW_MIB_ifRxLongOkPkt,
+       HW_MIB_ifRxLongPktErrPkt,
+       HW_MIB_ifTXSQEErrors,
+       HW_MIB_ifRxNobuf,
+       HW_MIB_ifRxSymbolErrors,
+       HW_MIB_ifInRangeLengthErrors,
+       HW_MIB_ifLateCollisions,
+       HW_MIB_SIZE
+};
+
+enum chip_type {
+       CHIP_TYPE_VT6110 = 1,
+};
+
+struct velocity_info_tbl {
+       enum chip_type chip_id;
+       const char *name;
+       int txqueue;
+       u32 flags;
+};
+
+#define mac_hw_mibs_init(regs) {\
+       BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\
+       BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\
+       do {}\
+               while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\
+       BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\
+}
+
+#define mac_read_isr(regs)             readl(&((regs)->ISR))
+#define mac_write_isr(regs, x)         writel((x),&((regs)->ISR))
+#define mac_clear_isr(regs)            writel(0xffffffffL,&((regs)->ISR))
+
+#define mac_write_int_mask(mask, regs)         writel((mask),&((regs)->IMR));
+#define mac_disable_int(regs)          writel(CR0_GINTMSK1,&((regs)->CR0Clr))
+#define mac_enable_int(regs)           writel(CR0_GINTMSK1,&((regs)->CR0Set))
+
+#define mac_set_dma_length(regs, n) {\
+       BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\
+}
+
+#define mac_set_rx_thresh(regs, n) {\
+       BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\
+}
+
+#define mac_rx_queue_run(regs) {\
+       writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\
+}
+
+#define mac_rx_queue_wake(regs) {\
+       writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\
+}
+
+#define mac_tx_queue_run(regs, n) {\
+       writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\
+}
+
+#define mac_tx_queue_wake(regs, n) {\
+       writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\
+}
+
+static inline void mac_eeprom_reload(struct mac_regs __iomem * regs) {
+       int i=0;
+
+       BYTE_REG_BITS_ON(EECSR_RELOAD,&(regs->EECSR));
+       do {
+               udelay(10);
+               if (i++>0x1000)
+                       break;
+       } while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&(regs->EECSR)));
+}
+
+/*
+ * Header for WOL definitions. Used to compute hashes
+ */
+
+typedef u8 MCAM_ADDR[ETH_ALEN];
+
+struct arp_packet {
+       u8 dest_mac[ETH_ALEN];
+       u8 src_mac[ETH_ALEN];
+       __be16 type;
+       __be16 ar_hrd;
+       __be16 ar_pro;
+       u8 ar_hln;
+       u8 ar_pln;
+       __be16 ar_op;
+       u8 ar_sha[ETH_ALEN];
+       u8 ar_sip[4];
+       u8 ar_tha[ETH_ALEN];
+       u8 ar_tip[4];
+} __packed;
+
+struct _magic_packet {
+       u8 dest_mac[6];
+       u8 src_mac[6];
+       __be16 type;
+       u8 MAC[16][6];
+       u8 password[6];
+} __packed;
+
+/*
+ *     Store for chip context when saving and restoring status. Not
+ *     all fields are saved/restored currently.
+ */
+
+struct velocity_context {
+       u8 mac_reg[256];
+       MCAM_ADDR cam_addr[MCAM_SIZE];
+       u16 vcam[VCAM_SIZE];
+       u32 cammask[2];
+       u32 patcrc[2];
+       u32 pattern[8];
+};
+
+/*
+ *     Registers in the MII (offset unit is WORD)
+ */
+
+// Marvell 88E1000/88E1000S
+#define MII_REG_PSCR        0x10       // PHY specific control register
+
+//
+// Bits in the Silicon revision register
+//
+
+#define TCSR_ECHODIS        0x2000     //
+#define AUXCR_MDPPS         0x0004     //
+
+// Bits in the PLED register
+#define PLED_LALBE                     0x0004  //
+
+// Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h)
+#define PSCR_ACRSTX         0x0800     // Assert CRS on Transmit
+
+#define PHYID_CICADA_CS8201 0x000FC410UL
+#define PHYID_VT3216_32BIT  0x000FC610UL
+#define PHYID_VT3216_64BIT  0x000FC600UL
+#define PHYID_MARVELL_1000  0x01410C50UL
+#define PHYID_MARVELL_1000S 0x01410C40UL
+
+#define PHYID_REV_ID_MASK   0x0000000FUL
+
+#define PHYID_GET_PHY_ID(i)         ((i) & ~PHYID_REV_ID_MASK)
+
+#define MII_REG_BITS_ON(x,i,p) do {\
+    u16 w;\
+    velocity_mii_read((p),(i),&(w));\
+    (w)|=(x);\
+    velocity_mii_write((p),(i),(w));\
+} while (0)
+
+#define MII_REG_BITS_OFF(x,i,p) do {\
+    u16 w;\
+    velocity_mii_read((p),(i),&(w));\
+    (w)&=(~(x));\
+    velocity_mii_write((p),(i),(w));\
+} while (0)
+
+#define MII_REG_BITS_IS_ON(x,i,p) ({\
+    u16 w;\
+    velocity_mii_read((p),(i),&(w));\
+    ((int) ((w) & (x)));})
+
+#define MII_GET_PHY_ID(p) ({\
+    u32 id;\
+    velocity_mii_read((p),MII_PHYSID2,(u16 *) &id);\
+    velocity_mii_read((p),MII_PHYSID1,((u16 *) &id)+1);\
+    (id);})
+
+/*
+ * Inline debug routine
+ */
+
+
+enum velocity_msg_level {
+       MSG_LEVEL_ERR = 0,      //Errors that will cause abnormal operation.
+       MSG_LEVEL_NOTICE = 1,   //Some errors need users to be notified.
+       MSG_LEVEL_INFO = 2,     //Normal message.
+       MSG_LEVEL_VERBOSE = 3,  //Will report all trival errors.
+       MSG_LEVEL_DEBUG = 4     //Only for debug purpose.
+};
+
+#ifdef VELOCITY_DEBUG
+#define ASSERT(x) { \
+       if (!(x)) { \
+               printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x,\
+                       __func__, __LINE__);\
+               BUG(); \
+       }\
+}
+#define VELOCITY_DBG(p,args...) printk(p, ##args)
+#else
+#define ASSERT(x)
+#define VELOCITY_DBG(x)
+#endif
+
+#define VELOCITY_PRT(l, p, args...) do {if (l<=msglevel) printk( p ,##args);} while (0)
+
+#define VELOCITY_PRT_CAMMASK(p,t) {\
+       int i;\
+       if ((t)==VELOCITY_MULTICAST_CAM) {\
+               for (i=0;i<(MCAM_SIZE/8);i++)\
+                       printk("%02X",(p)->mCAMmask[i]);\
+       }\
+       else {\
+               for (i=0;i<(VCAM_SIZE/8);i++)\
+                       printk("%02X",(p)->vCAMmask[i]);\
+       }\
+       printk("\n");\
+}
+
+
+
+#define     VELOCITY_WOL_MAGIC             0x00000000UL
+#define     VELOCITY_WOL_PHY               0x00000001UL
+#define     VELOCITY_WOL_ARP               0x00000002UL
+#define     VELOCITY_WOL_UCAST             0x00000004UL
+#define     VELOCITY_WOL_BCAST             0x00000010UL
+#define     VELOCITY_WOL_MCAST             0x00000020UL
+#define     VELOCITY_WOL_MAGIC_SEC         0x00000040UL
+
+/*
+ *     Flags for options
+ */
+
+#define     VELOCITY_FLAGS_TAGGING         0x00000001UL
+#define     VELOCITY_FLAGS_RX_CSUM         0x00000004UL
+#define     VELOCITY_FLAGS_IP_ALIGN        0x00000008UL
+#define     VELOCITY_FLAGS_VAL_PKT_LEN     0x00000010UL
+
+#define     VELOCITY_FLAGS_FLOW_CTRL       0x01000000UL
+
+/*
+ *     Flags for driver status
+ */
+
+#define     VELOCITY_FLAGS_OPENED          0x00010000UL
+#define     VELOCITY_FLAGS_VMNS_CONNECTED  0x00020000UL
+#define     VELOCITY_FLAGS_VMNS_COMMITTED  0x00040000UL
+#define     VELOCITY_FLAGS_WOL_ENABLED     0x00080000UL
+
+/*
+ *     Flags for MII status
+ */
+
+#define     VELOCITY_LINK_FAIL             0x00000001UL
+#define     VELOCITY_SPEED_10              0x00000002UL
+#define     VELOCITY_SPEED_100             0x00000004UL
+#define     VELOCITY_SPEED_1000            0x00000008UL
+#define     VELOCITY_DUPLEX_FULL           0x00000010UL
+#define     VELOCITY_AUTONEG_ENABLE        0x00000020UL
+#define     VELOCITY_FORCED_BY_EEPROM      0x00000040UL
+
+/*
+ *     For velocity_set_media_duplex
+ */
+
+#define     VELOCITY_LINK_CHANGE           0x00000001UL
+
+enum speed_opt {
+       SPD_DPX_AUTO = 0,
+       SPD_DPX_100_HALF = 1,
+       SPD_DPX_100_FULL = 2,
+       SPD_DPX_10_HALF = 3,
+       SPD_DPX_10_FULL = 4,
+       SPD_DPX_1000_FULL = 5
+};
+
+enum velocity_init_type {
+       VELOCITY_INIT_COLD = 0,
+       VELOCITY_INIT_RESET,
+       VELOCITY_INIT_WOL
+};
+
+enum velocity_flow_cntl_type {
+       FLOW_CNTL_DEFAULT = 1,
+       FLOW_CNTL_TX,
+       FLOW_CNTL_RX,
+       FLOW_CNTL_TX_RX,
+       FLOW_CNTL_DISABLE,
+};
+
+struct velocity_opt {
+       int numrx;                      /* Number of RX descriptors */
+       int numtx;                      /* Number of TX descriptors */
+       enum speed_opt spd_dpx;         /* Media link mode */
+
+       int DMA_length;                 /* DMA length */
+       int rx_thresh;                  /* RX_THRESH */
+       int flow_cntl;
+       int wol_opts;                   /* Wake on lan options */
+       int td_int_count;
+       int int_works;
+       int rx_bandwidth_hi;
+       int rx_bandwidth_lo;
+       int rx_bandwidth_en;
+       int rxqueue_timer;
+       int txqueue_timer;
+       int tx_intsup;
+       int rx_intsup;
+       u32 flags;
+};
+
+#define AVAIL_TD(p,q)   ((p)->options.numtx-((p)->tx.used[(q)]))
+
+#define GET_RD_BY_IDX(vptr, idx)   (vptr->rd_ring[idx])
+
+struct velocity_info {
+       struct pci_dev *pdev;
+       struct net_device *dev;
+
+       unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
+       u8 ip_addr[4];
+       enum chip_type chip_id;
+
+       struct mac_regs __iomem * mac_regs;
+       unsigned long memaddr;
+       unsigned long ioaddr;
+
+       struct tx_info {
+               int numq;
+
+               /* FIXME: the locality of the data seems rather poor. */
+               int used[TX_QUEUE_NO];
+               int curr[TX_QUEUE_NO];
+               int tail[TX_QUEUE_NO];
+               struct tx_desc *rings[TX_QUEUE_NO];
+               struct velocity_td_info *infos[TX_QUEUE_NO];
+               dma_addr_t pool_dma[TX_QUEUE_NO];
+       } tx;
+
+       struct rx_info {
+               int buf_sz;
+
+               int dirty;
+               int curr;
+               u32 filled;
+               struct rx_desc *ring;
+               struct velocity_rd_info *info;  /* It's an array */
+               dma_addr_t pool_dma;
+       } rx;
+
+       u32 mib_counter[MAX_HW_MIB_COUNTER];
+       struct velocity_opt options;
+
+       u32 int_mask;
+
+       u32 flags;
+
+       u32 mii_status;
+       u32 phy_id;
+       int multicast_limit;
+
+       u8 vCAMmask[(VCAM_SIZE / 8)];
+       u8 mCAMmask[(MCAM_SIZE / 8)];
+
+       spinlock_t lock;
+
+       int wol_opts;
+       u8 wol_passwd[6];
+
+       struct velocity_context context;
+
+       u32 ticks;
+
+       u8 rev_id;
+
+       struct napi_struct napi;
+};
+
+/**
+ *     velocity_get_ip         -       find an IP address for the device
+ *     @vptr: Velocity to query
+ *
+ *     Dig out an IP address for this interface so that we can
+ *     configure wakeup with WOL for ARP. If there are multiple IP
+ *     addresses on this chain then we use the first - multi-IP WOL is not
+ *     supported.
+ *
+ */
+
+static inline int velocity_get_ip(struct velocity_info *vptr)
+{
+       struct in_device *in_dev;
+       struct in_ifaddr *ifa;
+       int res = -ENOENT;
+
+       rcu_read_lock();
+       in_dev = __in_dev_get_rcu(vptr->dev);
+       if (in_dev != NULL) {
+               ifa = (struct in_ifaddr *) in_dev->ifa_list;
+               if (ifa != NULL) {
+                       memcpy(vptr->ip_addr, &ifa->ifa_address, 4);
+                       res = 0;
+               }
+       }
+       rcu_read_unlock();
+       return res;
+}
+
+/**
+ *     velocity_update_hw_mibs -       fetch MIB counters from chip
+ *     @vptr: velocity to update
+ *
+ *     The velocity hardware keeps certain counters in the hardware
+ *     side. We need to read these when the user asks for statistics
+ *     or when they overflow (causing an interrupt). The read of the
+ *     statistic clears it, so we keep running master counters in user
+ *     space.
+ */
+
+static inline void velocity_update_hw_mibs(struct velocity_info *vptr)
+{
+       u32 tmp;
+       int i;
+       BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR));
+
+       while (BYTE_REG_BITS_IS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)));
+
+       BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR));
+       for (i = 0; i < HW_MIB_SIZE; i++) {
+               tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL;
+               vptr->mib_counter[i] += tmp;
+       }
+}
+
+/**
+ *     init_flow_control_register      -       set up flow control
+ *     @vptr: velocity to configure
+ *
+ *     Configure the flow control registers for this velocity device.
+ */
+
+static inline void init_flow_control_register(struct velocity_info *vptr)
+{
+       struct mac_regs __iomem * regs = vptr->mac_regs;
+
+       /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1}
+          depend on RD=64, and Turn on XNOEN in FlowCR1 */
+       writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), &regs->CR0Set);
+       writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), &regs->CR0Clr);
+
+       /* Set TxPauseTimer to 0xFFFF */
+       writew(0xFFFF, &regs->tx_pause_timer);
+
+       /* Initialize RBRDU to Rx buffer count. */
+       writew(vptr->options.numrx, &regs->RBRDU);
+}
+
+
+#endif
diff --git a/drivers/net/via-rhine.c b/drivers/net/via-rhine.c
deleted file mode 100644 (file)
index 7f23ab9..0000000
+++ /dev/null
@@ -1,2340 +0,0 @@
-/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
-/*
-       Written 1998-2001 by Donald Becker.
-
-       Current Maintainer: Roger Luethi <rl@hellgate.ch>
-
-       This software may be used and distributed according to the terms of
-       the GNU General Public License (GPL), incorporated herein by reference.
-       Drivers based on or derived from this code fall under the GPL and must
-       retain the authorship, copyright and license notice.  This file is not
-       a complete program and may only be used when the entire operating
-       system is licensed under the GPL.
-
-       This driver is designed for the VIA VT86C100A Rhine-I.
-       It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
-       and management NIC 6105M).
-
-       The author may be reached as becker@scyld.com, or C/O
-       Scyld Computing Corporation
-       410 Severn Ave., Suite 210
-       Annapolis MD 21403
-
-
-       This driver contains some changes from the original Donald Becker
-       version. He may or may not be interested in bug reports on this
-       code. You can find his versions at:
-       http://www.scyld.com/network/via-rhine.html
-       [link no longer provides useful info -jgarzik]
-
-*/
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#define DRV_NAME       "via-rhine"
-#define DRV_VERSION    "1.5.0"
-#define DRV_RELDATE    "2010-10-09"
-
-
-/* A few user-configurable values.
-   These may be modified when a driver module is loaded. */
-
-#define DEBUG
-static int debug = 1;  /* 1 normal messages, 0 quiet .. 7 verbose. */
-static int max_interrupt_work = 20;
-
-/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
-   Setting to > 1518 effectively disables this feature. */
-#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
-       defined(CONFIG_SPARC) || defined(__ia64__) ||              \
-       defined(__sh__) || defined(__mips__)
-static int rx_copybreak = 1518;
-#else
-static int rx_copybreak;
-#endif
-
-/* Work-around for broken BIOSes: they are unable to get the chip back out of
-   power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
-static int avoid_D3;
-
-/*
- * In case you are looking for 'options[]' or 'full_duplex[]', they
- * are gone. Use ethtool(8) instead.
- */
-
-/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
-   The Rhine has a 64 element 8390-like hash table. */
-static const int multicast_filter_limit = 32;
-
-
-/* Operational parameters that are set at compile time. */
-
-/* Keep the ring sizes a power of two for compile efficiency.
-   The compiler will convert <unsigned>'%'<2^N> into a bit mask.
-   Making the Tx ring too large decreases the effectiveness of channel
-   bonding and packet priority.
-   There are no ill effects from too-large receive rings. */
-#define TX_RING_SIZE   16
-#define TX_QUEUE_LEN   10      /* Limit ring entries actually used. */
-#define RX_RING_SIZE   64
-
-/* Operational parameters that usually are not changed. */
-
-/* Time in jiffies before concluding the transmitter is hung. */
-#define TX_TIMEOUT     (2*HZ)
-
-#define PKT_BUF_SZ     1536    /* Size of each temporary Rx buffer.*/
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/timer.h>
-#include <linux/errno.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/pci.h>
-#include <linux/dma-mapping.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/mii.h>
-#include <linux/ethtool.h>
-#include <linux/crc32.h>
-#include <linux/if_vlan.h>
-#include <linux/bitops.h>
-#include <linux/workqueue.h>
-#include <asm/processor.h>     /* Processor type for cache alignment. */
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-#include <linux/dmi.h>
-
-/* These identify the driver base version and may not be removed. */
-static const char version[] __devinitconst =
-       "v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker";
-
-/* This driver was written to use PCI memory space. Some early versions
-   of the Rhine may only work correctly with I/O space accesses. */
-#ifdef CONFIG_VIA_RHINE_MMIO
-#define USE_MMIO
-#else
-#endif
-
-MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
-MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
-MODULE_LICENSE("GPL");
-
-module_param(max_interrupt_work, int, 0);
-module_param(debug, int, 0);
-module_param(rx_copybreak, int, 0);
-module_param(avoid_D3, bool, 0);
-MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
-MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
-MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
-MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
-
-#define MCAM_SIZE      32
-#define VCAM_SIZE      32
-
-/*
-               Theory of Operation
-
-I. Board Compatibility
-
-This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
-controller.
-
-II. Board-specific settings
-
-Boards with this chip are functional only in a bus-master PCI slot.
-
-Many operational settings are loaded from the EEPROM to the Config word at
-offset 0x78. For most of these settings, this driver assumes that they are
-correct.
-If this driver is compiled to use PCI memory space operations the EEPROM
-must be configured to enable memory ops.
-
-III. Driver operation
-
-IIIa. Ring buffers
-
-This driver uses two statically allocated fixed-size descriptor lists
-formed into rings by a branch from the final descriptor to the beginning of
-the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
-
-IIIb/c. Transmit/Receive Structure
-
-This driver attempts to use a zero-copy receive and transmit scheme.
-
-Alas, all data buffers are required to start on a 32 bit boundary, so
-the driver must often copy transmit packets into bounce buffers.
-
-The driver allocates full frame size skbuffs for the Rx ring buffers at
-open() time and passes the skb->data field to the chip as receive data
-buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
-a fresh skbuff is allocated and the frame is copied to the new skbuff.
-When the incoming frame is larger, the skbuff is passed directly up the
-protocol stack. Buffers consumed this way are replaced by newly allocated
-skbuffs in the last phase of rhine_rx().
-
-The RX_COPYBREAK value is chosen to trade-off the memory wasted by
-using a full-sized skbuff for small frames vs. the copying costs of larger
-frames. New boards are typically used in generously configured machines
-and the underfilled buffers have negligible impact compared to the benefit of
-a single allocation size, so the default value of zero results in never
-copying packets. When copying is done, the cost is usually mitigated by using
-a combined copy/checksum routine. Copying also preloads the cache, which is
-most useful with small frames.
-
-Since the VIA chips are only able to transfer data to buffers on 32 bit
-boundaries, the IP header at offset 14 in an ethernet frame isn't
-longword aligned for further processing. Copying these unaligned buffers
-has the beneficial effect of 16-byte aligning the IP header.
-
-IIId. Synchronization
-
-The driver runs as two independent, single-threaded flows of control. One
-is the send-packet routine, which enforces single-threaded use by the
-netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,
-which is single threaded by the hardware and interrupt handling software.
-
-The send packet thread has partial control over the Tx ring. It locks the
-netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in
-the ring is not available it stops the transmit queue by
-calling netif_stop_queue.
-
-The interrupt handler has exclusive control over the Rx ring and records stats
-from the Tx ring. After reaping the stats, it marks the Tx queue entry as
-empty by incrementing the dirty_tx mark. If at least half of the entries in
-the Rx ring are available the transmit queue is woken up if it was stopped.
-
-IV. Notes
-
-IVb. References
-
-Preliminary VT86C100A manual from http://www.via.com.tw/
-http://www.scyld.com/expert/100mbps.html
-http://www.scyld.com/expert/NWay.html
-ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
-ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
-
-
-IVc. Errata
-
-The VT86C100A manual is not reliable information.
-The 3043 chip does not handle unaligned transmit or receive buffers, resulting
-in significant performance degradation for bounce buffer copies on transmit
-and unaligned IP headers on receive.
-The chip does not pad to minimum transmit length.
-
-*/
-
-
-/* This table drives the PCI probe routines. It's mostly boilerplate in all
-   of the drivers, and will likely be provided by some future kernel.
-   Note the matching code -- the first table entry matchs all 56** cards but
-   second only the 1234 card.
-*/
-
-enum rhine_revs {
-       VT86C100A       = 0x00,
-       VTunknown0      = 0x20,
-       VT6102          = 0x40,
-       VT8231          = 0x50, /* Integrated MAC */
-       VT8233          = 0x60, /* Integrated MAC */
-       VT8235          = 0x74, /* Integrated MAC */
-       VT8237          = 0x78, /* Integrated MAC */
-       VTunknown1      = 0x7C,
-       VT6105          = 0x80,
-       VT6105_B0       = 0x83,
-       VT6105L         = 0x8A,
-       VT6107          = 0x8C,
-       VTunknown2      = 0x8E,
-       VT6105M         = 0x90, /* Management adapter */
-};
-
-enum rhine_quirks {
-       rqWOL           = 0x0001,       /* Wake-On-LAN support */
-       rqForceReset    = 0x0002,
-       rq6patterns     = 0x0040,       /* 6 instead of 4 patterns for WOL */
-       rqStatusWBRace  = 0x0080,       /* Tx Status Writeback Error possible */
-       rqRhineI        = 0x0100,       /* See comment below */
-};
-/*
- * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
- * MMIO as well as for the collision counter and the Tx FIFO underflow
- * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
- */
-
-/* Beware of PCI posted writes */
-#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
-
-static DEFINE_PCI_DEVICE_TABLE(rhine_pci_tbl) = {
-       { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, },    /* VT86C100A */
-       { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, },    /* VT6102 */
-       { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, },    /* 6105{,L,LOM} */
-       { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, },    /* VT6105M */
-       { }     /* terminate list */
-};
-MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
-
-
-/* Offsets to the device registers. */
-enum register_offsets {
-       StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
-       ChipCmd1=0x09, TQWake=0x0A,
-       IntrStatus=0x0C, IntrEnable=0x0E,
-       MulticastFilter0=0x10, MulticastFilter1=0x14,
-       RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
-       MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F,
-       MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
-       ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
-       RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
-       StickyHW=0x83, IntrStatus2=0x84,
-       CamMask=0x88, CamCon=0x92, CamAddr=0x93,
-       WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
-       WOLcrClr1=0xA6, WOLcgClr=0xA7,
-       PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
-};
-
-/* Bits in ConfigD */
-enum backoff_bits {
-       BackOptional=0x01, BackModify=0x02,
-       BackCaptureEffect=0x04, BackRandom=0x08
-};
-
-/* Bits in the TxConfig (TCR) register */
-enum tcr_bits {
-       TCR_PQEN=0x01,
-       TCR_LB0=0x02,           /* loopback[0] */
-       TCR_LB1=0x04,           /* loopback[1] */
-       TCR_OFSET=0x08,
-       TCR_RTGOPT=0x10,
-       TCR_RTFT0=0x20,
-       TCR_RTFT1=0x40,
-       TCR_RTSF=0x80,
-};
-
-/* Bits in the CamCon (CAMC) register */
-enum camcon_bits {
-       CAMC_CAMEN=0x01,
-       CAMC_VCAMSL=0x02,
-       CAMC_CAMWR=0x04,
-       CAMC_CAMRD=0x08,
-};
-
-/* Bits in the PCIBusConfig1 (BCR1) register */
-enum bcr1_bits {
-       BCR1_POT0=0x01,
-       BCR1_POT1=0x02,
-       BCR1_POT2=0x04,
-       BCR1_CTFT0=0x08,
-       BCR1_CTFT1=0x10,
-       BCR1_CTSF=0x20,
-       BCR1_TXQNOBK=0x40,      /* for VT6105 */
-       BCR1_VIDFR=0x80,        /* for VT6105 */
-       BCR1_MED0=0x40,         /* for VT6102 */
-       BCR1_MED1=0x80,         /* for VT6102 */
-};
-
-#ifdef USE_MMIO
-/* Registers we check that mmio and reg are the same. */
-static const int mmio_verify_registers[] = {
-       RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
-       0
-};
-#endif
-
-/* Bits in the interrupt status/mask registers. */
-enum intr_status_bits {
-       IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
-       IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
-       IntrPCIErr=0x0040,
-       IntrStatsMax=0x0080, IntrRxEarly=0x0100,
-       IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
-       IntrTxAborted=0x2000, IntrLinkChange=0x4000,
-       IntrRxWakeUp=0x8000,
-       IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
-       IntrTxDescRace=0x080000,        /* mapped from IntrStatus2 */
-       IntrTxErrSummary=0x082218,
-};
-
-/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
-enum wol_bits {
-       WOLucast        = 0x10,
-       WOLmagic        = 0x20,
-       WOLbmcast       = 0x30,
-       WOLlnkon        = 0x40,
-       WOLlnkoff       = 0x80,
-};
-
-/* The Rx and Tx buffer descriptors. */
-struct rx_desc {
-       __le32 rx_status;
-       __le32 desc_length; /* Chain flag, Buffer/frame length */
-       __le32 addr;
-       __le32 next_desc;
-};
-struct tx_desc {
-       __le32 tx_status;
-       __le32 desc_length; /* Chain flag, Tx Config, Frame length */
-       __le32 addr;
-       __le32 next_desc;
-};
-
-/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
-#define TXDESC         0x00e08000
-
-enum rx_status_bits {
-       RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
-};
-
-/* Bits in *_desc.*_status */
-enum desc_status_bits {
-       DescOwn=0x80000000
-};
-
-/* Bits in *_desc.*_length */
-enum desc_length_bits {
-       DescTag=0x00010000
-};
-
-/* Bits in ChipCmd. */
-enum chip_cmd_bits {
-       CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
-       CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
-       Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
-       Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
-};
-
-struct rhine_private {
-       /* Bit mask for configured VLAN ids */
-       unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
-
-       /* Descriptor rings */
-       struct rx_desc *rx_ring;
-       struct tx_desc *tx_ring;
-       dma_addr_t rx_ring_dma;
-       dma_addr_t tx_ring_dma;
-
-       /* The addresses of receive-in-place skbuffs. */
-       struct sk_buff *rx_skbuff[RX_RING_SIZE];
-       dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
-
-       /* The saved address of a sent-in-place packet/buffer, for later free(). */
-       struct sk_buff *tx_skbuff[TX_RING_SIZE];
-       dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
-
-       /* Tx bounce buffers (Rhine-I only) */
-       unsigned char *tx_buf[TX_RING_SIZE];
-       unsigned char *tx_bufs;
-       dma_addr_t tx_bufs_dma;
-
-       struct pci_dev *pdev;
-       long pioaddr;
-       struct net_device *dev;
-       struct napi_struct napi;
-       spinlock_t lock;
-       struct work_struct reset_task;
-
-       /* Frequently used values: keep some adjacent for cache effect. */
-       u32 quirks;
-       struct rx_desc *rx_head_desc;
-       unsigned int cur_rx, dirty_rx;  /* Producer/consumer ring indices */
-       unsigned int cur_tx, dirty_tx;
-       unsigned int rx_buf_sz;         /* Based on MTU+slack. */
-       u8 wolopts;
-
-       u8 tx_thresh, rx_thresh;
-
-       struct mii_if_info mii_if;
-       void __iomem *base;
-};
-
-#define BYTE_REG_BITS_ON(x, p)      do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
-#define WORD_REG_BITS_ON(x, p)      do { iowrite16((ioread16((p))|(x)), (p)); } while (0)
-#define DWORD_REG_BITS_ON(x, p)     do { iowrite32((ioread32((p))|(x)), (p)); } while (0)
-
-#define BYTE_REG_BITS_IS_ON(x, p)   (ioread8((p)) & (x))
-#define WORD_REG_BITS_IS_ON(x, p)   (ioread16((p)) & (x))
-#define DWORD_REG_BITS_IS_ON(x, p)  (ioread32((p)) & (x))
-
-#define BYTE_REG_BITS_OFF(x, p)     do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
-#define WORD_REG_BITS_OFF(x, p)     do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)
-#define DWORD_REG_BITS_OFF(x, p)    do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)
-
-#define BYTE_REG_BITS_SET(x, m, p)   do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
-#define WORD_REG_BITS_SET(x, m, p)   do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0)
-#define DWORD_REG_BITS_SET(x, m, p)  do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0)
-
-
-static int  mdio_read(struct net_device *dev, int phy_id, int location);
-static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
-static int  rhine_open(struct net_device *dev);
-static void rhine_reset_task(struct work_struct *work);
-static void rhine_tx_timeout(struct net_device *dev);
-static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
-                                 struct net_device *dev);
-static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
-static void rhine_tx(struct net_device *dev);
-static int rhine_rx(struct net_device *dev, int limit);
-static void rhine_error(struct net_device *dev, int intr_status);
-static void rhine_set_rx_mode(struct net_device *dev);
-static struct net_device_stats *rhine_get_stats(struct net_device *dev);
-static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
-static const struct ethtool_ops netdev_ethtool_ops;
-static int  rhine_close(struct net_device *dev);
-static void rhine_shutdown (struct pci_dev *pdev);
-static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid);
-static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid);
-static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr);
-static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr);
-static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask);
-static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask);
-static void rhine_init_cam_filter(struct net_device *dev);
-static void rhine_update_vcam(struct net_device *dev);
-
-#define RHINE_WAIT_FOR(condition)                              \
-do {                                                           \
-       int i = 1024;                                           \
-       while (!(condition) && --i)                             \
-               ;                                               \
-       if (debug > 1 && i < 512)                               \
-               pr_info("%4d cycles used @ %s:%d\n",            \
-                       1024 - i, __func__, __LINE__);          \
-} while (0)
-
-static inline u32 get_intr_status(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-       u32 intr_status;
-
-       intr_status = ioread16(ioaddr + IntrStatus);
-       /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
-       if (rp->quirks & rqStatusWBRace)
-               intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
-       return intr_status;
-}
-
-/*
- * Get power related registers into sane state.
- * Notify user about past WOL event.
- */
-static void rhine_power_init(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-       u16 wolstat;
-
-       if (rp->quirks & rqWOL) {
-               /* Make sure chip is in power state D0 */
-               iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
-
-               /* Disable "force PME-enable" */
-               iowrite8(0x80, ioaddr + WOLcgClr);
-
-               /* Clear power-event config bits (WOL) */
-               iowrite8(0xFF, ioaddr + WOLcrClr);
-               /* More recent cards can manage two additional patterns */
-               if (rp->quirks & rq6patterns)
-                       iowrite8(0x03, ioaddr + WOLcrClr1);
-
-               /* Save power-event status bits */
-               wolstat = ioread8(ioaddr + PwrcsrSet);
-               if (rp->quirks & rq6patterns)
-                       wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
-
-               /* Clear power-event status bits */
-               iowrite8(0xFF, ioaddr + PwrcsrClr);
-               if (rp->quirks & rq6patterns)
-                       iowrite8(0x03, ioaddr + PwrcsrClr1);
-
-               if (wolstat) {
-                       char *reason;
-                       switch (wolstat) {
-                       case WOLmagic:
-                               reason = "Magic packet";
-                               break;
-                       case WOLlnkon:
-                               reason = "Link went up";
-                               break;
-                       case WOLlnkoff:
-                               reason = "Link went down";
-                               break;
-                       case WOLucast:
-                               reason = "Unicast packet";
-                               break;
-                       case WOLbmcast:
-                               reason = "Multicast/broadcast packet";
-                               break;
-                       default:
-                               reason = "Unknown";
-                       }
-                       netdev_info(dev, "Woke system up. Reason: %s\n",
-                                   reason);
-               }
-       }
-}
-
-static void rhine_chip_reset(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-
-       iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
-       IOSYNC;
-
-       if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
-               netdev_info(dev, "Reset not complete yet. Trying harder.\n");
-
-               /* Force reset */
-               if (rp->quirks & rqForceReset)
-                       iowrite8(0x40, ioaddr + MiscCmd);
-
-               /* Reset can take somewhat longer (rare) */
-               RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
-       }
-
-       if (debug > 1)
-               netdev_info(dev, "Reset %s\n",
-                           (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
-                           "failed" : "succeeded");
-}
-
-#ifdef USE_MMIO
-static void enable_mmio(long pioaddr, u32 quirks)
-{
-       int n;
-       if (quirks & rqRhineI) {
-               /* More recent docs say that this bit is reserved ... */
-               n = inb(pioaddr + ConfigA) | 0x20;
-               outb(n, pioaddr + ConfigA);
-       } else {
-               n = inb(pioaddr + ConfigD) | 0x80;
-               outb(n, pioaddr + ConfigD);
-       }
-}
-#endif
-
-/*
- * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
- * (plus 0x6C for Rhine-I/II)
- */
-static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-
-       outb(0x20, pioaddr + MACRegEEcsr);
-       RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
-
-#ifdef USE_MMIO
-       /*
-        * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
-        * MMIO. If reloading EEPROM was done first this could be avoided, but
-        * it is not known if that still works with the "win98-reboot" problem.
-        */
-       enable_mmio(pioaddr, rp->quirks);
-#endif
-
-       /* Turn off EEPROM-controlled wake-up (magic packet) */
-       if (rp->quirks & rqWOL)
-               iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
-
-}
-
-#ifdef CONFIG_NET_POLL_CONTROLLER
-static void rhine_poll(struct net_device *dev)
-{
-       disable_irq(dev->irq);
-       rhine_interrupt(dev->irq, (void *)dev);
-       enable_irq(dev->irq);
-}
-#endif
-
-static int rhine_napipoll(struct napi_struct *napi, int budget)
-{
-       struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
-       struct net_device *dev = rp->dev;
-       void __iomem *ioaddr = rp->base;
-       int work_done;
-
-       work_done = rhine_rx(dev, budget);
-
-       if (work_done < budget) {
-               napi_complete(napi);
-
-               iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
-                         IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
-                         IntrTxDone | IntrTxError | IntrTxUnderrun |
-                         IntrPCIErr | IntrStatsMax | IntrLinkChange,
-                         ioaddr + IntrEnable);
-       }
-       return work_done;
-}
-
-static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-
-       /* Reset the chip to erase previous misconfiguration. */
-       rhine_chip_reset(dev);
-
-       /* Rhine-I needs extra time to recuperate before EEPROM reload */
-       if (rp->quirks & rqRhineI)
-               msleep(5);
-
-       /* Reload EEPROM controlled bytes cleared by soft reset */
-       rhine_reload_eeprom(pioaddr, dev);
-}
-
-static const struct net_device_ops rhine_netdev_ops = {
-       .ndo_open                = rhine_open,
-       .ndo_stop                = rhine_close,
-       .ndo_start_xmit          = rhine_start_tx,
-       .ndo_get_stats           = rhine_get_stats,
-       .ndo_set_multicast_list  = rhine_set_rx_mode,
-       .ndo_change_mtu          = eth_change_mtu,
-       .ndo_validate_addr       = eth_validate_addr,
-       .ndo_set_mac_address     = eth_mac_addr,
-       .ndo_do_ioctl            = netdev_ioctl,
-       .ndo_tx_timeout          = rhine_tx_timeout,
-       .ndo_vlan_rx_add_vid     = rhine_vlan_rx_add_vid,
-       .ndo_vlan_rx_kill_vid    = rhine_vlan_rx_kill_vid,
-#ifdef CONFIG_NET_POLL_CONTROLLER
-       .ndo_poll_controller     = rhine_poll,
-#endif
-};
-
-static int __devinit rhine_init_one(struct pci_dev *pdev,
-                                   const struct pci_device_id *ent)
-{
-       struct net_device *dev;
-       struct rhine_private *rp;
-       int i, rc;
-       u32 quirks;
-       long pioaddr;
-       long memaddr;
-       void __iomem *ioaddr;
-       int io_size, phy_id;
-       const char *name;
-#ifdef USE_MMIO
-       int bar = 1;
-#else
-       int bar = 0;
-#endif
-
-/* when built into the kernel, we only print version if device is found */
-#ifndef MODULE
-       pr_info_once("%s\n", version);
-#endif
-
-       io_size = 256;
-       phy_id = 0;
-       quirks = 0;
-       name = "Rhine";
-       if (pdev->revision < VTunknown0) {
-               quirks = rqRhineI;
-               io_size = 128;
-       }
-       else if (pdev->revision >= VT6102) {
-               quirks = rqWOL | rqForceReset;
-               if (pdev->revision < VT6105) {
-                       name = "Rhine II";
-                       quirks |= rqStatusWBRace;       /* Rhine-II exclusive */
-               }
-               else {
-                       phy_id = 1;     /* Integrated PHY, phy_id fixed to 1 */
-                       if (pdev->revision >= VT6105_B0)
-                               quirks |= rq6patterns;
-                       if (pdev->revision < VT6105M)
-                               name = "Rhine III";
-                       else
-                               name = "Rhine III (Management Adapter)";
-               }
-       }
-
-       rc = pci_enable_device(pdev);
-       if (rc)
-               goto err_out;
-
-       /* this should always be supported */
-       rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
-       if (rc) {
-               dev_err(&pdev->dev,
-                       "32-bit PCI DMA addresses not supported by the card!?\n");
-               goto err_out;
-       }
-
-       /* sanity check */
-       if ((pci_resource_len(pdev, 0) < io_size) ||
-           (pci_resource_len(pdev, 1) < io_size)) {
-               rc = -EIO;
-               dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
-               goto err_out;
-       }
-
-       pioaddr = pci_resource_start(pdev, 0);
-       memaddr = pci_resource_start(pdev, 1);
-
-       pci_set_master(pdev);
-
-       dev = alloc_etherdev(sizeof(struct rhine_private));
-       if (!dev) {
-               rc = -ENOMEM;
-               dev_err(&pdev->dev, "alloc_etherdev failed\n");
-               goto err_out;
-       }
-       SET_NETDEV_DEV(dev, &pdev->dev);
-
-       rp = netdev_priv(dev);
-       rp->dev = dev;
-       rp->quirks = quirks;
-       rp->pioaddr = pioaddr;
-       rp->pdev = pdev;
-
-       rc = pci_request_regions(pdev, DRV_NAME);
-       if (rc)
-               goto err_out_free_netdev;
-
-       ioaddr = pci_iomap(pdev, bar, io_size);
-       if (!ioaddr) {
-               rc = -EIO;
-               dev_err(&pdev->dev,
-                       "ioremap failed for device %s, region 0x%X @ 0x%lX\n",
-                       pci_name(pdev), io_size, memaddr);
-               goto err_out_free_res;
-       }
-
-#ifdef USE_MMIO
-       enable_mmio(pioaddr, quirks);
-
-       /* Check that selected MMIO registers match the PIO ones */
-       i = 0;
-       while (mmio_verify_registers[i]) {
-               int reg = mmio_verify_registers[i++];
-               unsigned char a = inb(pioaddr+reg);
-               unsigned char b = readb(ioaddr+reg);
-               if (a != b) {
-                       rc = -EIO;
-                       dev_err(&pdev->dev,
-                               "MMIO do not match PIO [%02x] (%02x != %02x)\n",
-                               reg, a, b);
-                       goto err_out_unmap;
-               }
-       }
-#endif /* USE_MMIO */
-
-       dev->base_addr = (unsigned long)ioaddr;
-       rp->base = ioaddr;
-
-       /* Get chip registers into a sane state */
-       rhine_power_init(dev);
-       rhine_hw_init(dev, pioaddr);
-
-       for (i = 0; i < 6; i++)
-               dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
-
-       if (!is_valid_ether_addr(dev->dev_addr)) {
-               /* Report it and use a random ethernet address instead */
-               netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr);
-               random_ether_addr(dev->dev_addr);
-               netdev_info(dev, "Using random MAC address: %pM\n",
-                           dev->dev_addr);
-       }
-       memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
-
-       /* For Rhine-I/II, phy_id is loaded from EEPROM */
-       if (!phy_id)
-               phy_id = ioread8(ioaddr + 0x6C);
-
-       dev->irq = pdev->irq;
-
-       spin_lock_init(&rp->lock);
-       INIT_WORK(&rp->reset_task, rhine_reset_task);
-
-       rp->mii_if.dev = dev;
-       rp->mii_if.mdio_read = mdio_read;
-       rp->mii_if.mdio_write = mdio_write;
-       rp->mii_if.phy_id_mask = 0x1f;
-       rp->mii_if.reg_num_mask = 0x1f;
-
-       /* The chip-specific entries in the device structure. */
-       dev->netdev_ops = &rhine_netdev_ops;
-       dev->ethtool_ops = &netdev_ethtool_ops,
-       dev->watchdog_timeo = TX_TIMEOUT;
-
-       netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
-
-       if (rp->quirks & rqRhineI)
-               dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
-
-       if (pdev->revision >= VT6105M)
-               dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
-               NETIF_F_HW_VLAN_FILTER;
-
-       /* dev->name not defined before register_netdev()! */
-       rc = register_netdev(dev);
-       if (rc)
-               goto err_out_unmap;
-
-       netdev_info(dev, "VIA %s at 0x%lx, %pM, IRQ %d\n",
-                   name,
-#ifdef USE_MMIO
-                   memaddr,
-#else
-                   (long)ioaddr,
-#endif
-                   dev->dev_addr, pdev->irq);
-
-       pci_set_drvdata(pdev, dev);
-
-       {
-               u16 mii_cmd;
-               int mii_status = mdio_read(dev, phy_id, 1);
-               mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
-               mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
-               if (mii_status != 0xffff && mii_status != 0x0000) {
-                       rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
-                       netdev_info(dev,
-                                   "MII PHY found at address %d, status 0x%04x advertising %04x Link %04x\n",
-                                   phy_id,
-                                   mii_status, rp->mii_if.advertising,
-                                   mdio_read(dev, phy_id, 5));
-
-                       /* set IFF_RUNNING */
-                       if (mii_status & BMSR_LSTATUS)
-                               netif_carrier_on(dev);
-                       else
-                               netif_carrier_off(dev);
-
-               }
-       }
-       rp->mii_if.phy_id = phy_id;
-       if (debug > 1 && avoid_D3)
-               netdev_info(dev, "No D3 power state at shutdown\n");
-
-       return 0;
-
-err_out_unmap:
-       pci_iounmap(pdev, ioaddr);
-err_out_free_res:
-       pci_release_regions(pdev);
-err_out_free_netdev:
-       free_netdev(dev);
-err_out:
-       return rc;
-}
-
-static int alloc_ring(struct net_device* dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void *ring;
-       dma_addr_t ring_dma;
-
-       ring = pci_alloc_consistent(rp->pdev,
-                                   RX_RING_SIZE * sizeof(struct rx_desc) +
-                                   TX_RING_SIZE * sizeof(struct tx_desc),
-                                   &ring_dma);
-       if (!ring) {
-               netdev_err(dev, "Could not allocate DMA memory\n");
-               return -ENOMEM;
-       }
-       if (rp->quirks & rqRhineI) {
-               rp->tx_bufs = pci_alloc_consistent(rp->pdev,
-                                                  PKT_BUF_SZ * TX_RING_SIZE,
-                                                  &rp->tx_bufs_dma);
-               if (rp->tx_bufs == NULL) {
-                       pci_free_consistent(rp->pdev,
-                                   RX_RING_SIZE * sizeof(struct rx_desc) +
-                                   TX_RING_SIZE * sizeof(struct tx_desc),
-                                   ring, ring_dma);
-                       return -ENOMEM;
-               }
-       }
-
-       rp->rx_ring = ring;
-       rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
-       rp->rx_ring_dma = ring_dma;
-       rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
-
-       return 0;
-}
-
-static void free_ring(struct net_device* dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-
-       pci_free_consistent(rp->pdev,
-                           RX_RING_SIZE * sizeof(struct rx_desc) +
-                           TX_RING_SIZE * sizeof(struct tx_desc),
-                           rp->rx_ring, rp->rx_ring_dma);
-       rp->tx_ring = NULL;
-
-       if (rp->tx_bufs)
-               pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
-                                   rp->tx_bufs, rp->tx_bufs_dma);
-
-       rp->tx_bufs = NULL;
-
-}
-
-static void alloc_rbufs(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       dma_addr_t next;
-       int i;
-
-       rp->dirty_rx = rp->cur_rx = 0;
-
-       rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
-       rp->rx_head_desc = &rp->rx_ring[0];
-       next = rp->rx_ring_dma;
-
-       /* Init the ring entries */
-       for (i = 0; i < RX_RING_SIZE; i++) {
-               rp->rx_ring[i].rx_status = 0;
-               rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
-               next += sizeof(struct rx_desc);
-               rp->rx_ring[i].next_desc = cpu_to_le32(next);
-               rp->rx_skbuff[i] = NULL;
-       }
-       /* Mark the last entry as wrapping the ring. */
-       rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
-
-       /* Fill in the Rx buffers.  Handle allocation failure gracefully. */
-       for (i = 0; i < RX_RING_SIZE; i++) {
-               struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
-               rp->rx_skbuff[i] = skb;
-               if (skb == NULL)
-                       break;
-               skb->dev = dev;                 /* Mark as being used by this device. */
-
-               rp->rx_skbuff_dma[i] =
-                       pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
-                                      PCI_DMA_FROMDEVICE);
-
-               rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
-               rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
-       }
-       rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
-}
-
-static void free_rbufs(struct net_device* dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       int i;
-
-       /* Free all the skbuffs in the Rx queue. */
-       for (i = 0; i < RX_RING_SIZE; i++) {
-               rp->rx_ring[i].rx_status = 0;
-               rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
-               if (rp->rx_skbuff[i]) {
-                       pci_unmap_single(rp->pdev,
-                                        rp->rx_skbuff_dma[i],
-                                        rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
-                       dev_kfree_skb(rp->rx_skbuff[i]);
-               }
-               rp->rx_skbuff[i] = NULL;
-       }
-}
-
-static void alloc_tbufs(struct net_device* dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       dma_addr_t next;
-       int i;
-
-       rp->dirty_tx = rp->cur_tx = 0;
-       next = rp->tx_ring_dma;
-       for (i = 0; i < TX_RING_SIZE; i++) {
-               rp->tx_skbuff[i] = NULL;
-               rp->tx_ring[i].tx_status = 0;
-               rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
-               next += sizeof(struct tx_desc);
-               rp->tx_ring[i].next_desc = cpu_to_le32(next);
-               if (rp->quirks & rqRhineI)
-                       rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
-       }
-       rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
-
-}
-
-static void free_tbufs(struct net_device* dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       int i;
-
-       for (i = 0; i < TX_RING_SIZE; i++) {
-               rp->tx_ring[i].tx_status = 0;
-               rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
-               rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
-               if (rp->tx_skbuff[i]) {
-                       if (rp->tx_skbuff_dma[i]) {
-                               pci_unmap_single(rp->pdev,
-                                                rp->tx_skbuff_dma[i],
-                                                rp->tx_skbuff[i]->len,
-                                                PCI_DMA_TODEVICE);
-                       }
-                       dev_kfree_skb(rp->tx_skbuff[i]);
-               }
-               rp->tx_skbuff[i] = NULL;
-               rp->tx_buf[i] = NULL;
-       }
-}
-
-static void rhine_check_media(struct net_device *dev, unsigned int init_media)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-
-       mii_check_media(&rp->mii_if, debug, init_media);
-
-       if (rp->mii_if.full_duplex)
-           iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
-                  ioaddr + ChipCmd1);
-       else
-           iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
-                  ioaddr + ChipCmd1);
-       if (debug > 1)
-               netdev_info(dev, "force_media %d, carrier %d\n",
-                           rp->mii_if.force_media, netif_carrier_ok(dev));
-}
-
-/* Called after status of force_media possibly changed */
-static void rhine_set_carrier(struct mii_if_info *mii)
-{
-       if (mii->force_media) {
-               /* autoneg is off: Link is always assumed to be up */
-               if (!netif_carrier_ok(mii->dev))
-                       netif_carrier_on(mii->dev);
-       }
-       else    /* Let MMI library update carrier status */
-               rhine_check_media(mii->dev, 0);
-       if (debug > 1)
-               netdev_info(mii->dev, "force_media %d, carrier %d\n",
-                           mii->force_media, netif_carrier_ok(mii->dev));
-}
-
-/**
- * rhine_set_cam - set CAM multicast filters
- * @ioaddr: register block of this Rhine
- * @idx: multicast CAM index [0..MCAM_SIZE-1]
- * @addr: multicast address (6 bytes)
- *
- * Load addresses into multicast filters.
- */
-static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr)
-{
-       int i;
-
-       iowrite8(CAMC_CAMEN, ioaddr + CamCon);
-       wmb();
-
-       /* Paranoid -- idx out of range should never happen */
-       idx &= (MCAM_SIZE - 1);
-
-       iowrite8((u8) idx, ioaddr + CamAddr);
-
-       for (i = 0; i < 6; i++, addr++)
-               iowrite8(*addr, ioaddr + MulticastFilter0 + i);
-       udelay(10);
-       wmb();
-
-       iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
-       udelay(10);
-
-       iowrite8(0, ioaddr + CamCon);
-}
-
-/**
- * rhine_set_vlan_cam - set CAM VLAN filters
- * @ioaddr: register block of this Rhine
- * @idx: VLAN CAM index [0..VCAM_SIZE-1]
- * @addr: VLAN ID (2 bytes)
- *
- * Load addresses into VLAN filters.
- */
-static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr)
-{
-       iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
-       wmb();
-
-       /* Paranoid -- idx out of range should never happen */
-       idx &= (VCAM_SIZE - 1);
-
-       iowrite8((u8) idx, ioaddr + CamAddr);
-
-       iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6);
-       udelay(10);
-       wmb();
-
-       iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
-       udelay(10);
-
-       iowrite8(0, ioaddr + CamCon);
-}
-
-/**
- * rhine_set_cam_mask - set multicast CAM mask
- * @ioaddr: register block of this Rhine
- * @mask: multicast CAM mask
- *
- * Mask sets multicast filters active/inactive.
- */
-static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask)
-{
-       iowrite8(CAMC_CAMEN, ioaddr + CamCon);
-       wmb();
-
-       /* write mask */
-       iowrite32(mask, ioaddr + CamMask);
-
-       /* disable CAMEN */
-       iowrite8(0, ioaddr + CamCon);
-}
-
-/**
- * rhine_set_vlan_cam_mask - set VLAN CAM mask
- * @ioaddr: register block of this Rhine
- * @mask: VLAN CAM mask
- *
- * Mask sets VLAN filters active/inactive.
- */
-static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask)
-{
-       iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
-       wmb();
-
-       /* write mask */
-       iowrite32(mask, ioaddr + CamMask);
-
-       /* disable CAMEN */
-       iowrite8(0, ioaddr + CamCon);
-}
-
-/**
- * rhine_init_cam_filter - initialize CAM filters
- * @dev: network device
- *
- * Initialize (disable) hardware VLAN and multicast support on this
- * Rhine.
- */
-static void rhine_init_cam_filter(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-
-       /* Disable all CAMs */
-       rhine_set_vlan_cam_mask(ioaddr, 0);
-       rhine_set_cam_mask(ioaddr, 0);
-
-       /* disable hardware VLAN support */
-       BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig);
-       BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
-}
-
-/**
- * rhine_update_vcam - update VLAN CAM filters
- * @rp: rhine_private data of this Rhine
- *
- * Update VLAN CAM filters to match configuration change.
- */
-static void rhine_update_vcam(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-       u16 vid;
-       u32 vCAMmask = 0;       /* 32 vCAMs (6105M and better) */
-       unsigned int i = 0;
-
-       for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) {
-               rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid);
-               vCAMmask |= 1 << i;
-               if (++i >= VCAM_SIZE)
-                       break;
-       }
-       rhine_set_vlan_cam_mask(ioaddr, vCAMmask);
-}
-
-static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-
-       spin_lock_irq(&rp->lock);
-       set_bit(vid, rp->active_vlans);
-       rhine_update_vcam(dev);
-       spin_unlock_irq(&rp->lock);
-}
-
-static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-
-       spin_lock_irq(&rp->lock);
-       clear_bit(vid, rp->active_vlans);
-       rhine_update_vcam(dev);
-       spin_unlock_irq(&rp->lock);
-}
-
-static void init_registers(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-       int i;
-
-       for (i = 0; i < 6; i++)
-               iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
-
-       /* Initialize other registers. */
-       iowrite16(0x0006, ioaddr + PCIBusConfig);       /* Tune configuration??? */
-       /* Configure initial FIFO thresholds. */
-       iowrite8(0x20, ioaddr + TxConfig);
-       rp->tx_thresh = 0x20;
-       rp->rx_thresh = 0x60;           /* Written in rhine_set_rx_mode(). */
-
-       iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
-       iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
-
-       rhine_set_rx_mode(dev);
-
-       if (rp->pdev->revision >= VT6105M)
-               rhine_init_cam_filter(dev);
-
-       napi_enable(&rp->napi);
-
-       /* Enable interrupts by setting the interrupt mask. */
-       iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
-              IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
-              IntrTxDone | IntrTxError | IntrTxUnderrun |
-              IntrPCIErr | IntrStatsMax | IntrLinkChange,
-              ioaddr + IntrEnable);
-
-       iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
-              ioaddr + ChipCmd);
-       rhine_check_media(dev, 1);
-}
-
-/* Enable MII link status auto-polling (required for IntrLinkChange) */
-static void rhine_enable_linkmon(void __iomem *ioaddr)
-{
-       iowrite8(0, ioaddr + MIICmd);
-       iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
-       iowrite8(0x80, ioaddr + MIICmd);
-
-       RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
-
-       iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
-}
-
-/* Disable MII link status auto-polling (required for MDIO access) */
-static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
-{
-       iowrite8(0, ioaddr + MIICmd);
-
-       if (quirks & rqRhineI) {
-               iowrite8(0x01, ioaddr + MIIRegAddr);    // MII_BMSR
-
-               /* Can be called from ISR. Evil. */
-               mdelay(1);
-
-               /* 0x80 must be set immediately before turning it off */
-               iowrite8(0x80, ioaddr + MIICmd);
-
-               RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
-
-               /* Heh. Now clear 0x80 again. */
-               iowrite8(0, ioaddr + MIICmd);
-       }
-       else
-               RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
-}
-
-/* Read and write over the MII Management Data I/O (MDIO) interface. */
-
-static int mdio_read(struct net_device *dev, int phy_id, int regnum)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-       int result;
-
-       rhine_disable_linkmon(ioaddr, rp->quirks);
-
-       /* rhine_disable_linkmon already cleared MIICmd */
-       iowrite8(phy_id, ioaddr + MIIPhyAddr);
-       iowrite8(regnum, ioaddr + MIIRegAddr);
-       iowrite8(0x40, ioaddr + MIICmd);                /* Trigger read */
-       RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
-       result = ioread16(ioaddr + MIIData);
-
-       rhine_enable_linkmon(ioaddr);
-       return result;
-}
-
-static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-
-       rhine_disable_linkmon(ioaddr, rp->quirks);
-
-       /* rhine_disable_linkmon already cleared MIICmd */
-       iowrite8(phy_id, ioaddr + MIIPhyAddr);
-       iowrite8(regnum, ioaddr + MIIRegAddr);
-       iowrite16(value, ioaddr + MIIData);
-       iowrite8(0x20, ioaddr + MIICmd);                /* Trigger write */
-       RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
-
-       rhine_enable_linkmon(ioaddr);
-}
-
-static int rhine_open(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-       int rc;
-
-       rc = request_irq(rp->pdev->irq, rhine_interrupt, IRQF_SHARED, dev->name,
-                       dev);
-       if (rc)
-               return rc;
-
-       if (debug > 1)
-               netdev_dbg(dev, "%s() irq %d\n", __func__, rp->pdev->irq);
-
-       rc = alloc_ring(dev);
-       if (rc) {
-               free_irq(rp->pdev->irq, dev);
-               return rc;
-       }
-       alloc_rbufs(dev);
-       alloc_tbufs(dev);
-       rhine_chip_reset(dev);
-       init_registers(dev);
-       if (debug > 2)
-               netdev_dbg(dev, "%s() Done - status %04x MII status: %04x\n",
-                          __func__, ioread16(ioaddr + ChipCmd),
-                          mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
-
-       netif_start_queue(dev);
-
-       return 0;
-}
-
-static void rhine_reset_task(struct work_struct *work)
-{
-       struct rhine_private *rp = container_of(work, struct rhine_private,
-                                               reset_task);
-       struct net_device *dev = rp->dev;
-
-       /* protect against concurrent rx interrupts */
-       disable_irq(rp->pdev->irq);
-
-       napi_disable(&rp->napi);
-
-       spin_lock_bh(&rp->lock);
-
-       /* clear all descriptors */
-       free_tbufs(dev);
-       free_rbufs(dev);
-       alloc_tbufs(dev);
-       alloc_rbufs(dev);
-
-       /* Reinitialize the hardware. */
-       rhine_chip_reset(dev);
-       init_registers(dev);
-
-       spin_unlock_bh(&rp->lock);
-       enable_irq(rp->pdev->irq);
-
-       dev->trans_start = jiffies; /* prevent tx timeout */
-       dev->stats.tx_errors++;
-       netif_wake_queue(dev);
-}
-
-static void rhine_tx_timeout(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-
-       netdev_warn(dev, "Transmit timed out, status %04x, PHY status %04x, resetting...\n",
-                   ioread16(ioaddr + IntrStatus),
-                   mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
-
-       schedule_work(&rp->reset_task);
-}
-
-static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
-                                 struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-       unsigned entry;
-       unsigned long flags;
-
-       /* Caution: the write order is important here, set the field
-          with the "ownership" bits last. */
-
-       /* Calculate the next Tx descriptor entry. */
-       entry = rp->cur_tx % TX_RING_SIZE;
-
-       if (skb_padto(skb, ETH_ZLEN))
-               return NETDEV_TX_OK;
-
-       rp->tx_skbuff[entry] = skb;
-
-       if ((rp->quirks & rqRhineI) &&
-           (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
-               /* Must use alignment buffer. */
-               if (skb->len > PKT_BUF_SZ) {
-                       /* packet too long, drop it */
-                       dev_kfree_skb(skb);
-                       rp->tx_skbuff[entry] = NULL;
-                       dev->stats.tx_dropped++;
-                       return NETDEV_TX_OK;
-               }
-
-               /* Padding is not copied and so must be redone. */
-               skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
-               if (skb->len < ETH_ZLEN)
-                       memset(rp->tx_buf[entry] + skb->len, 0,
-                              ETH_ZLEN - skb->len);
-               rp->tx_skbuff_dma[entry] = 0;
-               rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
-                                                     (rp->tx_buf[entry] -
-                                                      rp->tx_bufs));
-       } else {
-               rp->tx_skbuff_dma[entry] =
-                       pci_map_single(rp->pdev, skb->data, skb->len,
-                                      PCI_DMA_TODEVICE);
-               rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
-       }
-
-       rp->tx_ring[entry].desc_length =
-               cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
-
-       if (unlikely(vlan_tx_tag_present(skb))) {
-               rp->tx_ring[entry].tx_status = cpu_to_le32((vlan_tx_tag_get(skb)) << 16);
-               /* request tagging */
-               rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);
-       }
-       else
-               rp->tx_ring[entry].tx_status = 0;
-
-       /* lock eth irq */
-       spin_lock_irqsave(&rp->lock, flags);
-       wmb();
-       rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn);
-       wmb();
-
-       rp->cur_tx++;
-
-       /* Non-x86 Todo: explicitly flush cache lines here. */
-
-       if (vlan_tx_tag_present(skb))
-               /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
-               BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
-
-       /* Wake the potentially-idle transmit channel */
-       iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
-              ioaddr + ChipCmd1);
-       IOSYNC;
-
-       if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
-               netif_stop_queue(dev);
-
-       spin_unlock_irqrestore(&rp->lock, flags);
-
-       if (debug > 4) {
-               netdev_dbg(dev, "Transmit frame #%d queued in slot %d\n",
-                          rp->cur_tx-1, entry);
-       }
-       return NETDEV_TX_OK;
-}
-
-/* The interrupt handler does all of the Rx thread work and cleans up
-   after the Tx thread. */
-static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
-{
-       struct net_device *dev = dev_instance;
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-       u32 intr_status;
-       int boguscnt = max_interrupt_work;
-       int handled = 0;
-
-       while ((intr_status = get_intr_status(dev))) {
-               handled = 1;
-
-               /* Acknowledge all of the current interrupt sources ASAP. */
-               if (intr_status & IntrTxDescRace)
-                       iowrite8(0x08, ioaddr + IntrStatus2);
-               iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
-               IOSYNC;
-
-               if (debug > 4)
-                       netdev_dbg(dev, "Interrupt, status %08x\n",
-                                  intr_status);
-
-               if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
-                                  IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {
-                       iowrite16(IntrTxAborted |
-                                 IntrTxDone | IntrTxError | IntrTxUnderrun |
-                                 IntrPCIErr | IntrStatsMax | IntrLinkChange,
-                                 ioaddr + IntrEnable);
-
-                       napi_schedule(&rp->napi);
-               }
-
-               if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
-                       if (intr_status & IntrTxErrSummary) {
-                               /* Avoid scavenging before Tx engine turned off */
-                               RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
-                               if (debug > 2 &&
-                                   ioread8(ioaddr+ChipCmd) & CmdTxOn)
-                                       netdev_warn(dev,
-                                                   "%s: Tx engine still on\n",
-                                                   __func__);
-                       }
-                       rhine_tx(dev);
-               }
-
-               /* Abnormal error summary/uncommon events handlers. */
-               if (intr_status & (IntrPCIErr | IntrLinkChange |
-                                  IntrStatsMax | IntrTxError | IntrTxAborted |
-                                  IntrTxUnderrun | IntrTxDescRace))
-                       rhine_error(dev, intr_status);
-
-               if (--boguscnt < 0) {
-                       netdev_warn(dev, "Too much work at interrupt, status=%#08x\n",
-                                   intr_status);
-                       break;
-               }
-       }
-
-       if (debug > 3)
-               netdev_dbg(dev, "exiting interrupt, status=%08x\n",
-                          ioread16(ioaddr + IntrStatus));
-       return IRQ_RETVAL(handled);
-}
-
-/* This routine is logically part of the interrupt handler, but isolated
-   for clarity. */
-static void rhine_tx(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
-
-       spin_lock(&rp->lock);
-
-       /* find and cleanup dirty tx descriptors */
-       while (rp->dirty_tx != rp->cur_tx) {
-               txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
-               if (debug > 6)
-                       netdev_dbg(dev, "Tx scavenge %d status %08x\n",
-                                  entry, txstatus);
-               if (txstatus & DescOwn)
-                       break;
-               if (txstatus & 0x8000) {
-                       if (debug > 1)
-                               netdev_dbg(dev, "Transmit error, Tx status %08x\n",
-                                          txstatus);
-                       dev->stats.tx_errors++;
-                       if (txstatus & 0x0400)
-                               dev->stats.tx_carrier_errors++;
-                       if (txstatus & 0x0200)
-                               dev->stats.tx_window_errors++;
-                       if (txstatus & 0x0100)
-                               dev->stats.tx_aborted_errors++;
-                       if (txstatus & 0x0080)
-                               dev->stats.tx_heartbeat_errors++;
-                       if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
-                           (txstatus & 0x0800) || (txstatus & 0x1000)) {
-                               dev->stats.tx_fifo_errors++;
-                               rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
-                               break; /* Keep the skb - we try again */
-                       }
-                       /* Transmitter restarted in 'abnormal' handler. */
-               } else {
-                       if (rp->quirks & rqRhineI)
-                               dev->stats.collisions += (txstatus >> 3) & 0x0F;
-                       else
-                               dev->stats.collisions += txstatus & 0x0F;
-                       if (debug > 6)
-                               netdev_dbg(dev, "collisions: %1.1x:%1.1x\n",
-                                          (txstatus >> 3) & 0xF,
-                                          txstatus & 0xF);
-                       dev->stats.tx_bytes += rp->tx_skbuff[entry]->len;
-                       dev->stats.tx_packets++;
-               }
-               /* Free the original skb. */
-               if (rp->tx_skbuff_dma[entry]) {
-                       pci_unmap_single(rp->pdev,
-                                        rp->tx_skbuff_dma[entry],
-                                        rp->tx_skbuff[entry]->len,
-                                        PCI_DMA_TODEVICE);
-               }
-               dev_kfree_skb_irq(rp->tx_skbuff[entry]);
-               rp->tx_skbuff[entry] = NULL;
-               entry = (++rp->dirty_tx) % TX_RING_SIZE;
-       }
-       if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
-               netif_wake_queue(dev);
-
-       spin_unlock(&rp->lock);
-}
-
-/**
- * rhine_get_vlan_tci - extract TCI from Rx data buffer
- * @skb: pointer to sk_buff
- * @data_size: used data area of the buffer including CRC
- *
- * If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q
- * packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte
- * aligned following the CRC.
- */
-static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size)
-{
-       u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2;
-       return be16_to_cpup((__be16 *)trailer);
-}
-
-/* Process up to limit frames from receive ring */
-static int rhine_rx(struct net_device *dev, int limit)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       int count;
-       int entry = rp->cur_rx % RX_RING_SIZE;
-
-       if (debug > 4) {
-               netdev_dbg(dev, "%s(), entry %d status %08x\n",
-                          __func__, entry,
-                          le32_to_cpu(rp->rx_head_desc->rx_status));
-       }
-
-       /* If EOP is set on the next entry, it's a new packet. Send it up. */
-       for (count = 0; count < limit; ++count) {
-               struct rx_desc *desc = rp->rx_head_desc;
-               u32 desc_status = le32_to_cpu(desc->rx_status);
-               u32 desc_length = le32_to_cpu(desc->desc_length);
-               int data_size = desc_status >> 16;
-
-               if (desc_status & DescOwn)
-                       break;
-
-               if (debug > 4)
-                       netdev_dbg(dev, "%s() status is %08x\n",
-                                  __func__, desc_status);
-
-               if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
-                       if ((desc_status & RxWholePkt) != RxWholePkt) {
-                               netdev_warn(dev,
-       "Oversized Ethernet frame spanned multiple buffers, "
-       "entry %#x length %d status %08x!\n",
-                                           entry, data_size,
-                                           desc_status);
-                               netdev_warn(dev,
-                                           "Oversized Ethernet frame %p vs %p\n",
-                                           rp->rx_head_desc,
-                                           &rp->rx_ring[entry]);
-                               dev->stats.rx_length_errors++;
-                       } else if (desc_status & RxErr) {
-                               /* There was a error. */
-                               if (debug > 2)
-                                       netdev_dbg(dev, "%s() Rx error was %08x\n",
-                                                  __func__, desc_status);
-                               dev->stats.rx_errors++;
-                               if (desc_status & 0x0030)
-                                       dev->stats.rx_length_errors++;
-                               if (desc_status & 0x0048)
-                                       dev->stats.rx_fifo_errors++;
-                               if (desc_status & 0x0004)
-                                       dev->stats.rx_frame_errors++;
-                               if (desc_status & 0x0002) {
-                                       /* this can also be updated outside the interrupt handler */
-                                       spin_lock(&rp->lock);
-                                       dev->stats.rx_crc_errors++;
-                                       spin_unlock(&rp->lock);
-                               }
-                       }
-               } else {
-                       struct sk_buff *skb = NULL;
-                       /* Length should omit the CRC */
-                       int pkt_len = data_size - 4;
-                       u16 vlan_tci = 0;
-
-                       /* Check if the packet is long enough to accept without
-                          copying to a minimally-sized skbuff. */
-                       if (pkt_len < rx_copybreak)
-                               skb = netdev_alloc_skb_ip_align(dev, pkt_len);
-                       if (skb) {
-                               pci_dma_sync_single_for_cpu(rp->pdev,
-                                                           rp->rx_skbuff_dma[entry],
-                                                           rp->rx_buf_sz,
-                                                           PCI_DMA_FROMDEVICE);
-
-                               skb_copy_to_linear_data(skb,
-                                                rp->rx_skbuff[entry]->data,
-                                                pkt_len);
-                               skb_put(skb, pkt_len);
-                               pci_dma_sync_single_for_device(rp->pdev,
-                                                              rp->rx_skbuff_dma[entry],
-                                                              rp->rx_buf_sz,
-                                                              PCI_DMA_FROMDEVICE);
-                       } else {
-                               skb = rp->rx_skbuff[entry];
-                               if (skb == NULL) {
-                                       netdev_err(dev, "Inconsistent Rx descriptor chain\n");
-                                       break;
-                               }
-                               rp->rx_skbuff[entry] = NULL;
-                               skb_put(skb, pkt_len);
-                               pci_unmap_single(rp->pdev,
-                                                rp->rx_skbuff_dma[entry],
-                                                rp->rx_buf_sz,
-                                                PCI_DMA_FROMDEVICE);
-                       }
-
-                       if (unlikely(desc_length & DescTag))
-                               vlan_tci = rhine_get_vlan_tci(skb, data_size);
-
-                       skb->protocol = eth_type_trans(skb, dev);
-
-                       if (unlikely(desc_length & DescTag))
-                               __vlan_hwaccel_put_tag(skb, vlan_tci);
-                       netif_receive_skb(skb);
-                       dev->stats.rx_bytes += pkt_len;
-                       dev->stats.rx_packets++;
-               }
-               entry = (++rp->cur_rx) % RX_RING_SIZE;
-               rp->rx_head_desc = &rp->rx_ring[entry];
-       }
-
-       /* Refill the Rx ring buffers. */
-       for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
-               struct sk_buff *skb;
-               entry = rp->dirty_rx % RX_RING_SIZE;
-               if (rp->rx_skbuff[entry] == NULL) {
-                       skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
-                       rp->rx_skbuff[entry] = skb;
-                       if (skb == NULL)
-                               break;  /* Better luck next round. */
-                       skb->dev = dev; /* Mark as being used by this device. */
-                       rp->rx_skbuff_dma[entry] =
-                               pci_map_single(rp->pdev, skb->data,
-                                              rp->rx_buf_sz,
-                                              PCI_DMA_FROMDEVICE);
-                       rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
-               }
-               rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
-       }
-
-       return count;
-}
-
-/*
- * Clears the "tally counters" for CRC errors and missed frames(?).
- * It has been reported that some chips need a write of 0 to clear
- * these, for others the counters are set to 1 when written to and
- * instead cleared when read. So we clear them both ways ...
- */
-static inline void clear_tally_counters(void __iomem *ioaddr)
-{
-       iowrite32(0, ioaddr + RxMissed);
-       ioread16(ioaddr + RxCRCErrs);
-       ioread16(ioaddr + RxMissed);
-}
-
-static void rhine_restart_tx(struct net_device *dev) {
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-       int entry = rp->dirty_tx % TX_RING_SIZE;
-       u32 intr_status;
-
-       /*
-        * If new errors occurred, we need to sort them out before doing Tx.
-        * In that case the ISR will be back here RSN anyway.
-        */
-       intr_status = get_intr_status(dev);
-
-       if ((intr_status & IntrTxErrSummary) == 0) {
-
-               /* We know better than the chip where it should continue. */
-               iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
-                      ioaddr + TxRingPtr);
-
-               iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
-                      ioaddr + ChipCmd);
-
-               if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))
-                       /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
-                       BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
-
-               iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
-                      ioaddr + ChipCmd1);
-               IOSYNC;
-       }
-       else {
-               /* This should never happen */
-               if (debug > 1)
-                       netdev_warn(dev, "%s() Another error occurred %08x\n",
-                                  __func__, intr_status);
-       }
-
-}
-
-static void rhine_error(struct net_device *dev, int intr_status)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-
-       spin_lock(&rp->lock);
-
-       if (intr_status & IntrLinkChange)
-               rhine_check_media(dev, 0);
-       if (intr_status & IntrStatsMax) {
-               dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
-               dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
-               clear_tally_counters(ioaddr);
-       }
-       if (intr_status & IntrTxAborted) {
-               if (debug > 1)
-                       netdev_info(dev, "Abort %08x, frame dropped\n",
-                                   intr_status);
-       }
-       if (intr_status & IntrTxUnderrun) {
-               if (rp->tx_thresh < 0xE0)
-                       BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);
-               if (debug > 1)
-                       netdev_info(dev, "Transmitter underrun, Tx threshold now %02x\n",
-                                   rp->tx_thresh);
-       }
-       if (intr_status & IntrTxDescRace) {
-               if (debug > 2)
-                       netdev_info(dev, "Tx descriptor write-back race\n");
-       }
-       if ((intr_status & IntrTxError) &&
-           (intr_status & (IntrTxAborted |
-            IntrTxUnderrun | IntrTxDescRace)) == 0) {
-               if (rp->tx_thresh < 0xE0) {
-                       BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);
-               }
-               if (debug > 1)
-                       netdev_info(dev, "Unspecified error. Tx threshold now %02x\n",
-                                   rp->tx_thresh);
-       }
-       if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
-                          IntrTxError))
-               rhine_restart_tx(dev);
-
-       if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
-                           IntrTxError | IntrTxAborted | IntrNormalSummary |
-                           IntrTxDescRace)) {
-               if (debug > 1)
-                       netdev_err(dev, "Something Wicked happened! %08x\n",
-                                  intr_status);
-       }
-
-       spin_unlock(&rp->lock);
-}
-
-static struct net_device_stats *rhine_get_stats(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-       unsigned long flags;
-
-       spin_lock_irqsave(&rp->lock, flags);
-       dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
-       dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
-       clear_tally_counters(ioaddr);
-       spin_unlock_irqrestore(&rp->lock, flags);
-
-       return &dev->stats;
-}
-
-static void rhine_set_rx_mode(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-       u32 mc_filter[2];       /* Multicast hash filter */
-       u8 rx_mode = 0x0C;      /* Note: 0x02=accept runt, 0x01=accept errs */
-       struct netdev_hw_addr *ha;
-
-       if (dev->flags & IFF_PROMISC) {         /* Set promiscuous. */
-               rx_mode = 0x1C;
-               iowrite32(0xffffffff, ioaddr + MulticastFilter0);
-               iowrite32(0xffffffff, ioaddr + MulticastFilter1);
-       } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
-                  (dev->flags & IFF_ALLMULTI)) {
-               /* Too many to match, or accept all multicasts. */
-               iowrite32(0xffffffff, ioaddr + MulticastFilter0);
-               iowrite32(0xffffffff, ioaddr + MulticastFilter1);
-       } else if (rp->pdev->revision >= VT6105M) {
-               int i = 0;
-               u32 mCAMmask = 0;       /* 32 mCAMs (6105M and better) */
-               netdev_for_each_mc_addr(ha, dev) {
-                       if (i == MCAM_SIZE)
-                               break;
-                       rhine_set_cam(ioaddr, i, ha->addr);
-                       mCAMmask |= 1 << i;
-                       i++;
-               }
-               rhine_set_cam_mask(ioaddr, mCAMmask);
-       } else {
-               memset(mc_filter, 0, sizeof(mc_filter));
-               netdev_for_each_mc_addr(ha, dev) {
-                       int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
-
-                       mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
-               }
-               iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
-               iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
-       }
-       /* enable/disable VLAN receive filtering */
-       if (rp->pdev->revision >= VT6105M) {
-               if (dev->flags & IFF_PROMISC)
-                       BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
-               else
-                       BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1);
-       }
-       BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig);
-}
-
-static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-
-       strcpy(info->driver, DRV_NAME);
-       strcpy(info->version, DRV_VERSION);
-       strcpy(info->bus_info, pci_name(rp->pdev));
-}
-
-static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       int rc;
-
-       spin_lock_irq(&rp->lock);
-       rc = mii_ethtool_gset(&rp->mii_if, cmd);
-       spin_unlock_irq(&rp->lock);
-
-       return rc;
-}
-
-static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       int rc;
-
-       spin_lock_irq(&rp->lock);
-       rc = mii_ethtool_sset(&rp->mii_if, cmd);
-       spin_unlock_irq(&rp->lock);
-       rhine_set_carrier(&rp->mii_if);
-
-       return rc;
-}
-
-static int netdev_nway_reset(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-
-       return mii_nway_restart(&rp->mii_if);
-}
-
-static u32 netdev_get_link(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-
-       return mii_link_ok(&rp->mii_if);
-}
-
-static u32 netdev_get_msglevel(struct net_device *dev)
-{
-       return debug;
-}
-
-static void netdev_set_msglevel(struct net_device *dev, u32 value)
-{
-       debug = value;
-}
-
-static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-
-       if (!(rp->quirks & rqWOL))
-               return;
-
-       spin_lock_irq(&rp->lock);
-       wol->supported = WAKE_PHY | WAKE_MAGIC |
-                        WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;  /* Untested */
-       wol->wolopts = rp->wolopts;
-       spin_unlock_irq(&rp->lock);
-}
-
-static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       u32 support = WAKE_PHY | WAKE_MAGIC |
-                     WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;     /* Untested */
-
-       if (!(rp->quirks & rqWOL))
-               return -EINVAL;
-
-       if (wol->wolopts & ~support)
-               return -EINVAL;
-
-       spin_lock_irq(&rp->lock);
-       rp->wolopts = wol->wolopts;
-       spin_unlock_irq(&rp->lock);
-
-       return 0;
-}
-
-static const struct ethtool_ops netdev_ethtool_ops = {
-       .get_drvinfo            = netdev_get_drvinfo,
-       .get_settings           = netdev_get_settings,
-       .set_settings           = netdev_set_settings,
-       .nway_reset             = netdev_nway_reset,
-       .get_link               = netdev_get_link,
-       .get_msglevel           = netdev_get_msglevel,
-       .set_msglevel           = netdev_set_msglevel,
-       .get_wol                = rhine_get_wol,
-       .set_wol                = rhine_set_wol,
-};
-
-static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       int rc;
-
-       if (!netif_running(dev))
-               return -EINVAL;
-
-       spin_lock_irq(&rp->lock);
-       rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
-       spin_unlock_irq(&rp->lock);
-       rhine_set_carrier(&rp->mii_if);
-
-       return rc;
-}
-
-static int rhine_close(struct net_device *dev)
-{
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-
-       napi_disable(&rp->napi);
-       cancel_work_sync(&rp->reset_task);
-       netif_stop_queue(dev);
-
-       spin_lock_irq(&rp->lock);
-
-       if (debug > 1)
-               netdev_dbg(dev, "Shutting down ethercard, status was %04x\n",
-                          ioread16(ioaddr + ChipCmd));
-
-       /* Switch to loopback mode to avoid hardware races. */
-       iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
-
-       /* Disable interrupts by clearing the interrupt mask. */
-       iowrite16(0x0000, ioaddr + IntrEnable);
-
-       /* Stop the chip's Tx and Rx processes. */
-       iowrite16(CmdStop, ioaddr + ChipCmd);
-
-       spin_unlock_irq(&rp->lock);
-
-       free_irq(rp->pdev->irq, dev);
-       free_rbufs(dev);
-       free_tbufs(dev);
-       free_ring(dev);
-
-       return 0;
-}
-
-
-static void __devexit rhine_remove_one(struct pci_dev *pdev)
-{
-       struct net_device *dev = pci_get_drvdata(pdev);
-       struct rhine_private *rp = netdev_priv(dev);
-
-       unregister_netdev(dev);
-
-       pci_iounmap(pdev, rp->base);
-       pci_release_regions(pdev);
-
-       free_netdev(dev);
-       pci_disable_device(pdev);
-       pci_set_drvdata(pdev, NULL);
-}
-
-static void rhine_shutdown (struct pci_dev *pdev)
-{
-       struct net_device *dev = pci_get_drvdata(pdev);
-       struct rhine_private *rp = netdev_priv(dev);
-       void __iomem *ioaddr = rp->base;
-
-       if (!(rp->quirks & rqWOL))
-               return; /* Nothing to do for non-WOL adapters */
-
-       rhine_power_init(dev);
-
-       /* Make sure we use pattern 0, 1 and not 4, 5 */
-       if (rp->quirks & rq6patterns)
-               iowrite8(0x04, ioaddr + WOLcgClr);
-
-       if (rp->wolopts & WAKE_MAGIC) {
-               iowrite8(WOLmagic, ioaddr + WOLcrSet);
-               /*
-                * Turn EEPROM-controlled wake-up back on -- some hardware may
-                * not cooperate otherwise.
-                */
-               iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
-       }
-
-       if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
-               iowrite8(WOLbmcast, ioaddr + WOLcgSet);
-
-       if (rp->wolopts & WAKE_PHY)
-               iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
-
-       if (rp->wolopts & WAKE_UCAST)
-               iowrite8(WOLucast, ioaddr + WOLcrSet);
-
-       if (rp->wolopts) {
-               /* Enable legacy WOL (for old motherboards) */
-               iowrite8(0x01, ioaddr + PwcfgSet);
-               iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
-       }
-
-       /* Hit power state D3 (sleep) */
-       if (!avoid_D3)
-               iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
-
-       /* TODO: Check use of pci_enable_wake() */
-
-}
-
-#ifdef CONFIG_PM
-static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
-{
-       struct net_device *dev = pci_get_drvdata(pdev);
-       struct rhine_private *rp = netdev_priv(dev);
-       unsigned long flags;
-
-       if (!netif_running(dev))
-               return 0;
-
-       napi_disable(&rp->napi);
-
-       netif_device_detach(dev);
-       pci_save_state(pdev);
-
-       spin_lock_irqsave(&rp->lock, flags);
-       rhine_shutdown(pdev);
-       spin_unlock_irqrestore(&rp->lock, flags);
-
-       free_irq(dev->irq, dev);
-       return 0;
-}
-
-static int rhine_resume(struct pci_dev *pdev)
-{
-       struct net_device *dev = pci_get_drvdata(pdev);
-       struct rhine_private *rp = netdev_priv(dev);
-       unsigned long flags;
-       int ret;
-
-       if (!netif_running(dev))
-               return 0;
-
-       if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
-               netdev_err(dev, "request_irq failed\n");
-
-       ret = pci_set_power_state(pdev, PCI_D0);
-       if (debug > 1)
-               netdev_info(dev, "Entering power state D0 %s (%d)\n",
-                           ret ? "failed" : "succeeded", ret);
-
-       pci_restore_state(pdev);
-
-       spin_lock_irqsave(&rp->lock, flags);
-#ifdef USE_MMIO
-       enable_mmio(rp->pioaddr, rp->quirks);
-#endif
-       rhine_power_init(dev);
-       free_tbufs(dev);
-       free_rbufs(dev);
-       alloc_tbufs(dev);
-       alloc_rbufs(dev);
-       init_registers(dev);
-       spin_unlock_irqrestore(&rp->lock, flags);
-
-       netif_device_attach(dev);
-
-       return 0;
-}
-#endif /* CONFIG_PM */
-
-static struct pci_driver rhine_driver = {
-       .name           = DRV_NAME,
-       .id_table       = rhine_pci_tbl,
-       .probe          = rhine_init_one,
-       .remove         = __devexit_p(rhine_remove_one),
-#ifdef CONFIG_PM
-       .suspend        = rhine_suspend,
-       .resume         = rhine_resume,
-#endif /* CONFIG_PM */
-       .shutdown =     rhine_shutdown,
-};
-
-static struct dmi_system_id __initdata rhine_dmi_table[] = {
-       {
-               .ident = "EPIA-M",
-               .matches = {
-                       DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
-                       DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
-               },
-       },
-       {
-               .ident = "KV7",
-               .matches = {
-                       DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
-                       DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
-               },
-       },
-       { NULL }
-};
-
-static int __init rhine_init(void)
-{
-/* when a module, this is printed whether or not devices are found in probe */
-#ifdef MODULE
-       pr_info("%s\n", version);
-#endif
-       if (dmi_check_system(rhine_dmi_table)) {
-               /* these BIOSes fail at PXE boot if chip is in D3 */
-               avoid_D3 = 1;
-               pr_warn("Broken BIOS detected, avoid_D3 enabled\n");
-       }
-       else if (avoid_D3)
-               pr_info("avoid_D3 set\n");
-
-       return pci_register_driver(&rhine_driver);
-}
-
-
-static void __exit rhine_cleanup(void)
-{
-       pci_unregister_driver(&rhine_driver);
-}
-
-
-module_init(rhine_init);
-module_exit(rhine_cleanup);
diff --git a/drivers/net/via-velocity.c b/drivers/net/via-velocity.c
deleted file mode 100644 (file)
index 490ec5b..0000000
+++ /dev/null
@@ -1,3592 +0,0 @@
-/*
- * This code is derived from the VIA reference driver (copyright message
- * below) provided to Red Hat by VIA Networking Technologies, Inc. for
- * addition to the Linux kernel.
- *
- * The code has been merged into one source file, cleaned up to follow
- * Linux coding style,  ported to the Linux 2.6 kernel tree and cleaned
- * for 64bit hardware platforms.
- *
- * TODO
- *     rx_copybreak/alignment
- *     More testing
- *
- * The changes are (c) Copyright 2004, Red Hat Inc. <alan@lxorguk.ukuu.org.uk>
- * Additional fixes and clean up: Francois Romieu
- *
- * This source has not been verified for use in safety critical systems.
- *
- * Please direct queries about the revamped driver to the linux-kernel
- * list not VIA.
- *
- * Original code:
- *
- * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
- * All rights reserved.
- *
- * This software may be redistributed and/or modified under
- * the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * Author: Chuang Liang-Shing, AJ Jiang
- *
- * Date: Jan 24, 2003
- *
- * MODULE_LICENSE("GPL");
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/bitops.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/errno.h>
-#include <linux/ioport.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/delay.h>
-#include <linux/timer.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/string.h>
-#include <linux/wait.h>
-#include <linux/io.h>
-#include <linux/if.h>
-#include <linux/uaccess.h>
-#include <linux/proc_fs.h>
-#include <linux/inetdevice.h>
-#include <linux/reboot.h>
-#include <linux/ethtool.h>
-#include <linux/mii.h>
-#include <linux/in.h>
-#include <linux/if_arp.h>
-#include <linux/if_vlan.h>
-#include <linux/ip.h>
-#include <linux/tcp.h>
-#include <linux/udp.h>
-#include <linux/crc-ccitt.h>
-#include <linux/crc32.h>
-
-#include "via-velocity.h"
-
-
-static int velocity_nics;
-static int msglevel = MSG_LEVEL_INFO;
-
-/**
- *     mac_get_cam_mask        -       Read a CAM mask
- *     @regs: register block for this velocity
- *     @mask: buffer to store mask
- *
- *     Fetch the mask bits of the selected CAM and store them into the
- *     provided mask buffer.
- */
-static void mac_get_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
-{
-       int i;
-
-       /* Select CAM mask */
-       BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
-
-       writeb(0, &regs->CAMADDR);
-
-       /* read mask */
-       for (i = 0; i < 8; i++)
-               *mask++ = readb(&(regs->MARCAM[i]));
-
-       /* disable CAMEN */
-       writeb(0, &regs->CAMADDR);
-
-       /* Select mar */
-       BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
-}
-
-/**
- *     mac_set_cam_mask        -       Set a CAM mask
- *     @regs: register block for this velocity
- *     @mask: CAM mask to load
- *
- *     Store a new mask into a CAM
- */
-static void mac_set_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
-{
-       int i;
-       /* Select CAM mask */
-       BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
-
-       writeb(CAMADDR_CAMEN, &regs->CAMADDR);
-
-       for (i = 0; i < 8; i++)
-               writeb(*mask++, &(regs->MARCAM[i]));
-
-       /* disable CAMEN */
-       writeb(0, &regs->CAMADDR);
-
-       /* Select mar */
-       BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
-}
-
-static void mac_set_vlan_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
-{
-       int i;
-       /* Select CAM mask */
-       BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
-
-       writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL, &regs->CAMADDR);
-
-       for (i = 0; i < 8; i++)
-               writeb(*mask++, &(regs->MARCAM[i]));
-
-       /* disable CAMEN */
-       writeb(0, &regs->CAMADDR);
-
-       /* Select mar */
-       BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
-}
-
-/**
- *     mac_set_cam     -       set CAM data
- *     @regs: register block of this velocity
- *     @idx: Cam index
- *     @addr: 2 or 6 bytes of CAM data
- *
- *     Load an address or vlan tag into a CAM
- */
-static void mac_set_cam(struct mac_regs __iomem *regs, int idx, const u8 *addr)
-{
-       int i;
-
-       /* Select CAM mask */
-       BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
-
-       idx &= (64 - 1);
-
-       writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
-
-       for (i = 0; i < 6; i++)
-               writeb(*addr++, &(regs->MARCAM[i]));
-
-       BYTE_REG_BITS_ON(CAMCR_CAMWR, &regs->CAMCR);
-
-       udelay(10);
-
-       writeb(0, &regs->CAMADDR);
-
-       /* Select mar */
-       BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
-}
-
-static void mac_set_vlan_cam(struct mac_regs __iomem *regs, int idx,
-                            const u8 *addr)
-{
-
-       /* Select CAM mask */
-       BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
-
-       idx &= (64 - 1);
-
-       writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx, &regs->CAMADDR);
-       writew(*((u16 *) addr), &regs->MARCAM[0]);
-
-       BYTE_REG_BITS_ON(CAMCR_CAMWR, &regs->CAMCR);
-
-       udelay(10);
-
-       writeb(0, &regs->CAMADDR);
-
-       /* Select mar */
-       BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
-}
-
-
-/**
- *     mac_wol_reset   -       reset WOL after exiting low power
- *     @regs: register block of this velocity
- *
- *     Called after we drop out of wake on lan mode in order to
- *     reset the Wake on lan features. This function doesn't restore
- *     the rest of the logic from the result of sleep/wakeup
- */
-static void mac_wol_reset(struct mac_regs __iomem *regs)
-{
-
-       /* Turn off SWPTAG right after leaving power mode */
-       BYTE_REG_BITS_OFF(STICKHW_SWPTAG, &regs->STICKHW);
-       /* clear sticky bits */
-       BYTE_REG_BITS_OFF((STICKHW_DS1 | STICKHW_DS0), &regs->STICKHW);
-
-       BYTE_REG_BITS_OFF(CHIPGCR_FCGMII, &regs->CHIPGCR);
-       BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, &regs->CHIPGCR);
-       /* disable force PME-enable */
-       writeb(WOLCFG_PMEOVR, &regs->WOLCFGClr);
-       /* disable power-event config bit */
-       writew(0xFFFF, &regs->WOLCRClr);
-       /* clear power status */
-       writew(0xFFFF, &regs->WOLSRClr);
-}
-
-static const struct ethtool_ops velocity_ethtool_ops;
-
-/*
-    Define module options
-*/
-
-MODULE_AUTHOR("VIA Networking Technologies, Inc.");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("VIA Networking Velocity Family Gigabit Ethernet Adapter Driver");
-
-#define VELOCITY_PARAM(N, D) \
-       static int N[MAX_UNITS] = OPTION_DEFAULT;\
-       module_param_array(N, int, NULL, 0); \
-       MODULE_PARM_DESC(N, D);
-
-#define RX_DESC_MIN     64
-#define RX_DESC_MAX     255
-#define RX_DESC_DEF     64
-VELOCITY_PARAM(RxDescriptors, "Number of receive descriptors");
-
-#define TX_DESC_MIN     16
-#define TX_DESC_MAX     256
-#define TX_DESC_DEF     64
-VELOCITY_PARAM(TxDescriptors, "Number of transmit descriptors");
-
-#define RX_THRESH_MIN   0
-#define RX_THRESH_MAX   3
-#define RX_THRESH_DEF   0
-/* rx_thresh[] is used for controlling the receive fifo threshold.
-   0: indicate the rxfifo threshold is 128 bytes.
-   1: indicate the rxfifo threshold is 512 bytes.
-   2: indicate the rxfifo threshold is 1024 bytes.
-   3: indicate the rxfifo threshold is store & forward.
-*/
-VELOCITY_PARAM(rx_thresh, "Receive fifo threshold");
-
-#define DMA_LENGTH_MIN  0
-#define DMA_LENGTH_MAX  7
-#define DMA_LENGTH_DEF  6
-
-/* DMA_length[] is used for controlling the DMA length
-   0: 8 DWORDs
-   1: 16 DWORDs
-   2: 32 DWORDs
-   3: 64 DWORDs
-   4: 128 DWORDs
-   5: 256 DWORDs
-   6: SF(flush till emply)
-   7: SF(flush till emply)
-*/
-VELOCITY_PARAM(DMA_length, "DMA length");
-
-#define IP_ALIG_DEF     0
-/* IP_byte_align[] is used for IP header DWORD byte aligned
-   0: indicate the IP header won't be DWORD byte aligned.(Default) .
-   1: indicate the IP header will be DWORD byte aligned.
-      In some environment, the IP header should be DWORD byte aligned,
-      or the packet will be droped when we receive it. (eg: IPVS)
-*/
-VELOCITY_PARAM(IP_byte_align, "Enable IP header dword aligned");
-
-#define FLOW_CNTL_DEF   1
-#define FLOW_CNTL_MIN   1
-#define FLOW_CNTL_MAX   5
-
-/* flow_control[] is used for setting the flow control ability of NIC.
-   1: hardware deafult - AUTO (default). Use Hardware default value in ANAR.
-   2: enable TX flow control.
-   3: enable RX flow control.
-   4: enable RX/TX flow control.
-   5: disable
-*/
-VELOCITY_PARAM(flow_control, "Enable flow control ability");
-
-#define MED_LNK_DEF 0
-#define MED_LNK_MIN 0
-#define MED_LNK_MAX 5
-/* speed_duplex[] is used for setting the speed and duplex mode of NIC.
-   0: indicate autonegotiation for both speed and duplex mode
-   1: indicate 100Mbps half duplex mode
-   2: indicate 100Mbps full duplex mode
-   3: indicate 10Mbps half duplex mode
-   4: indicate 10Mbps full duplex mode
-   5: indicate 1000Mbps full duplex mode
-
-   Note:
-   if EEPROM have been set to the force mode, this option is ignored
-   by driver.
-*/
-VELOCITY_PARAM(speed_duplex, "Setting the speed and duplex mode");
-
-#define VAL_PKT_LEN_DEF     0
-/* ValPktLen[] is used for setting the checksum offload ability of NIC.
-   0: Receive frame with invalid layer 2 length (Default)
-   1: Drop frame with invalid layer 2 length
-*/
-VELOCITY_PARAM(ValPktLen, "Receiving or Drop invalid 802.3 frame");
-
-#define WOL_OPT_DEF     0
-#define WOL_OPT_MIN     0
-#define WOL_OPT_MAX     7
-/* wol_opts[] is used for controlling wake on lan behavior.
-   0: Wake up if recevied a magic packet. (Default)
-   1: Wake up if link status is on/off.
-   2: Wake up if recevied an arp packet.
-   4: Wake up if recevied any unicast packet.
-   Those value can be sumed up to support more than one option.
-*/
-VELOCITY_PARAM(wol_opts, "Wake On Lan options");
-
-static int rx_copybreak = 200;
-module_param(rx_copybreak, int, 0644);
-MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
-
-/*
- *     Internal board variants. At the moment we have only one
- */
-static struct velocity_info_tbl chip_info_table[] = {
-       {CHIP_TYPE_VT6110, "VIA Networking Velocity Family Gigabit Ethernet Adapter", 1, 0x00FFFFFFUL},
-       { }
-};
-
-/*
- *     Describe the PCI device identifiers that we support in this
- *     device driver. Used for hotplug autoloading.
- */
-static DEFINE_PCI_DEVICE_TABLE(velocity_id_table) = {
-       { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X) },
-       { }
-};
-
-MODULE_DEVICE_TABLE(pci, velocity_id_table);
-
-/**
- *     get_chip_name   -       identifier to name
- *     @id: chip identifier
- *
- *     Given a chip identifier return a suitable description. Returns
- *     a pointer a static string valid while the driver is loaded.
- */
-static const char __devinit *get_chip_name(enum chip_type chip_id)
-{
-       int i;
-       for (i = 0; chip_info_table[i].name != NULL; i++)
-               if (chip_info_table[i].chip_id == chip_id)
-                       break;
-       return chip_info_table[i].name;
-}
-
-/**
- *     velocity_remove1        -       device unplug
- *     @pdev: PCI device being removed
- *
- *     Device unload callback. Called on an unplug or on module
- *     unload for each active device that is present. Disconnects
- *     the device from the network layer and frees all the resources
- */
-static void __devexit velocity_remove1(struct pci_dev *pdev)
-{
-       struct net_device *dev = pci_get_drvdata(pdev);
-       struct velocity_info *vptr = netdev_priv(dev);
-
-       unregister_netdev(dev);
-       iounmap(vptr->mac_regs);
-       pci_release_regions(pdev);
-       pci_disable_device(pdev);
-       pci_set_drvdata(pdev, NULL);
-       free_netdev(dev);
-
-       velocity_nics--;
-}
-
-/**
- *     velocity_set_int_opt    -       parser for integer options
- *     @opt: pointer to option value
- *     @val: value the user requested (or -1 for default)
- *     @min: lowest value allowed
- *     @max: highest value allowed
- *     @def: default value
- *     @name: property name
- *     @dev: device name
- *
- *     Set an integer property in the module options. This function does
- *     all the verification and checking as well as reporting so that
- *     we don't duplicate code for each option.
- */
-static void __devinit velocity_set_int_opt(int *opt, int val, int min, int max, int def, char *name, const char *devname)
-{
-       if (val == -1)
-               *opt = def;
-       else if (val < min || val > max) {
-               VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (%d-%d)\n",
-                                       devname, name, min, max);
-               *opt = def;
-       } else {
-               VELOCITY_PRT(MSG_LEVEL_INFO, KERN_INFO "%s: set value of parameter %s to %d\n",
-                                       devname, name, val);
-               *opt = val;
-       }
-}
-
-/**
- *     velocity_set_bool_opt   -       parser for boolean options
- *     @opt: pointer to option value
- *     @val: value the user requested (or -1 for default)
- *     @def: default value (yes/no)
- *     @flag: numeric value to set for true.
- *     @name: property name
- *     @dev: device name
- *
- *     Set a boolean property in the module options. This function does
- *     all the verification and checking as well as reporting so that
- *     we don't duplicate code for each option.
- */
-static void __devinit velocity_set_bool_opt(u32 *opt, int val, int def, u32 flag, char *name, const char *devname)
-{
-       (*opt) &= (~flag);
-       if (val == -1)
-               *opt |= (def ? flag : 0);
-       else if (val < 0 || val > 1) {
-               printk(KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (0-1)\n",
-                       devname, name);
-               *opt |= (def ? flag : 0);
-       } else {
-               printk(KERN_INFO "%s: set parameter %s to %s\n",
-                       devname, name, val ? "TRUE" : "FALSE");
-               *opt |= (val ? flag : 0);
-       }
-}
-
-/**
- *     velocity_get_options    -       set options on device
- *     @opts: option structure for the device
- *     @index: index of option to use in module options array
- *     @devname: device name
- *
- *     Turn the module and command options into a single structure
- *     for the current device
- */
-static void __devinit velocity_get_options(struct velocity_opt *opts, int index, const char *devname)
-{
-
-       velocity_set_int_opt(&opts->rx_thresh, rx_thresh[index], RX_THRESH_MIN, RX_THRESH_MAX, RX_THRESH_DEF, "rx_thresh", devname);
-       velocity_set_int_opt(&opts->DMA_length, DMA_length[index], DMA_LENGTH_MIN, DMA_LENGTH_MAX, DMA_LENGTH_DEF, "DMA_length", devname);
-       velocity_set_int_opt(&opts->numrx, RxDescriptors[index], RX_DESC_MIN, RX_DESC_MAX, RX_DESC_DEF, "RxDescriptors", devname);
-       velocity_set_int_opt(&opts->numtx, TxDescriptors[index], TX_DESC_MIN, TX_DESC_MAX, TX_DESC_DEF, "TxDescriptors", devname);
-
-       velocity_set_int_opt(&opts->flow_cntl, flow_control[index], FLOW_CNTL_MIN, FLOW_CNTL_MAX, FLOW_CNTL_DEF, "flow_control", devname);
-       velocity_set_bool_opt(&opts->flags, IP_byte_align[index], IP_ALIG_DEF, VELOCITY_FLAGS_IP_ALIGN, "IP_byte_align", devname);
-       velocity_set_bool_opt(&opts->flags, ValPktLen[index], VAL_PKT_LEN_DEF, VELOCITY_FLAGS_VAL_PKT_LEN, "ValPktLen", devname);
-       velocity_set_int_opt((int *) &opts->spd_dpx, speed_duplex[index], MED_LNK_MIN, MED_LNK_MAX, MED_LNK_DEF, "Media link mode", devname);
-       velocity_set_int_opt((int *) &opts->wol_opts, wol_opts[index], WOL_OPT_MIN, WOL_OPT_MAX, WOL_OPT_DEF, "Wake On Lan options", devname);
-       opts->numrx = (opts->numrx & ~3);
-}
-
-/**
- *     velocity_init_cam_filter        -       initialise CAM
- *     @vptr: velocity to program
- *
- *     Initialize the content addressable memory used for filters. Load
- *     appropriately according to the presence of VLAN
- */
-static void velocity_init_cam_filter(struct velocity_info *vptr)
-{
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-       unsigned int vid, i = 0;
-
-       /* Turn on MCFG_PQEN, turn off MCFG_RTGOPT */
-       WORD_REG_BITS_SET(MCFG_PQEN, MCFG_RTGOPT, &regs->MCFG);
-       WORD_REG_BITS_ON(MCFG_VIDFR, &regs->MCFG);
-
-       /* Disable all CAMs */
-       memset(vptr->vCAMmask, 0, sizeof(u8) * 8);
-       memset(vptr->mCAMmask, 0, sizeof(u8) * 8);
-       mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
-       mac_set_cam_mask(regs, vptr->mCAMmask);
-
-       /* Enable VCAMs */
-
-       if (test_bit(0, vptr->active_vlans))
-               WORD_REG_BITS_ON(MCFG_RTGOPT, &regs->MCFG);
-
-       for_each_set_bit(vid, vptr->active_vlans, VLAN_N_VID) {
-               mac_set_vlan_cam(regs, i, (u8 *) &vid);
-               vptr->vCAMmask[i / 8] |= 0x1 << (i % 8);
-               if (++i >= VCAM_SIZE)
-                       break;
-       }
-       mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
-}
-
-static void velocity_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-
-       spin_lock_irq(&vptr->lock);
-       set_bit(vid, vptr->active_vlans);
-       velocity_init_cam_filter(vptr);
-       spin_unlock_irq(&vptr->lock);
-}
-
-static void velocity_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-
-       spin_lock_irq(&vptr->lock);
-       clear_bit(vid, vptr->active_vlans);
-       velocity_init_cam_filter(vptr);
-       spin_unlock_irq(&vptr->lock);
-}
-
-static void velocity_init_rx_ring_indexes(struct velocity_info *vptr)
-{
-       vptr->rx.dirty = vptr->rx.filled = vptr->rx.curr = 0;
-}
-
-/**
- *     velocity_rx_reset       -       handle a receive reset
- *     @vptr: velocity we are resetting
- *
- *     Reset the ownership and status for the receive ring side.
- *     Hand all the receive queue to the NIC.
- */
-static void velocity_rx_reset(struct velocity_info *vptr)
-{
-
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-       int i;
-
-       velocity_init_rx_ring_indexes(vptr);
-
-       /*
-        *      Init state, all RD entries belong to the NIC
-        */
-       for (i = 0; i < vptr->options.numrx; ++i)
-               vptr->rx.ring[i].rdesc0.len |= OWNED_BY_NIC;
-
-       writew(vptr->options.numrx, &regs->RBRDU);
-       writel(vptr->rx.pool_dma, &regs->RDBaseLo);
-       writew(0, &regs->RDIdx);
-       writew(vptr->options.numrx - 1, &regs->RDCSize);
-}
-
-/**
- *     velocity_get_opt_media_mode     -       get media selection
- *     @vptr: velocity adapter
- *
- *     Get the media mode stored in EEPROM or module options and load
- *     mii_status accordingly. The requested link state information
- *     is also returned.
- */
-static u32 velocity_get_opt_media_mode(struct velocity_info *vptr)
-{
-       u32 status = 0;
-
-       switch (vptr->options.spd_dpx) {
-       case SPD_DPX_AUTO:
-               status = VELOCITY_AUTONEG_ENABLE;
-               break;
-       case SPD_DPX_100_FULL:
-               status = VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL;
-               break;
-       case SPD_DPX_10_FULL:
-               status = VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL;
-               break;
-       case SPD_DPX_100_HALF:
-               status = VELOCITY_SPEED_100;
-               break;
-       case SPD_DPX_10_HALF:
-               status = VELOCITY_SPEED_10;
-               break;
-       case SPD_DPX_1000_FULL:
-               status = VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
-               break;
-       }
-       vptr->mii_status = status;
-       return status;
-}
-
-/**
- *     safe_disable_mii_autopoll       -       autopoll off
- *     @regs: velocity registers
- *
- *     Turn off the autopoll and wait for it to disable on the chip
- */
-static void safe_disable_mii_autopoll(struct mac_regs __iomem *regs)
-{
-       u16 ww;
-
-       /*  turn off MAUTO */
-       writeb(0, &regs->MIICR);
-       for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
-               udelay(1);
-               if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, &regs->MIISR))
-                       break;
-       }
-}
-
-/**
- *     enable_mii_autopoll     -       turn on autopolling
- *     @regs: velocity registers
- *
- *     Enable the MII link status autopoll feature on the Velocity
- *     hardware. Wait for it to enable.
- */
-static void enable_mii_autopoll(struct mac_regs __iomem *regs)
-{
-       int ii;
-
-       writeb(0, &(regs->MIICR));
-       writeb(MIIADR_SWMPL, &regs->MIIADR);
-
-       for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
-               udelay(1);
-               if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, &regs->MIISR))
-                       break;
-       }
-
-       writeb(MIICR_MAUTO, &regs->MIICR);
-
-       for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
-               udelay(1);
-               if (!BYTE_REG_BITS_IS_ON(MIISR_MIDLE, &regs->MIISR))
-                       break;
-       }
-
-}
-
-/**
- *     velocity_mii_read       -       read MII data
- *     @regs: velocity registers
- *     @index: MII register index
- *     @data: buffer for received data
- *
- *     Perform a single read of an MII 16bit register. Returns zero
- *     on success or -ETIMEDOUT if the PHY did not respond.
- */
-static int velocity_mii_read(struct mac_regs __iomem *regs, u8 index, u16 *data)
-{
-       u16 ww;
-
-       /*
-        *      Disable MIICR_MAUTO, so that mii addr can be set normally
-        */
-       safe_disable_mii_autopoll(regs);
-
-       writeb(index, &regs->MIIADR);
-
-       BYTE_REG_BITS_ON(MIICR_RCMD, &regs->MIICR);
-
-       for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
-               if (!(readb(&regs->MIICR) & MIICR_RCMD))
-                       break;
-       }
-
-       *data = readw(&regs->MIIDATA);
-
-       enable_mii_autopoll(regs);
-       if (ww == W_MAX_TIMEOUT)
-               return -ETIMEDOUT;
-       return 0;
-}
-
-/**
- *     mii_check_media_mode    -       check media state
- *     @regs: velocity registers
- *
- *     Check the current MII status and determine the link status
- *     accordingly
- */
-static u32 mii_check_media_mode(struct mac_regs __iomem *regs)
-{
-       u32 status = 0;
-       u16 ANAR;
-
-       if (!MII_REG_BITS_IS_ON(BMSR_LSTATUS, MII_BMSR, regs))
-               status |= VELOCITY_LINK_FAIL;
-
-       if (MII_REG_BITS_IS_ON(ADVERTISE_1000FULL, MII_CTRL1000, regs))
-               status |= VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
-       else if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF, MII_CTRL1000, regs))
-               status |= (VELOCITY_SPEED_1000);
-       else {
-               velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
-               if (ANAR & ADVERTISE_100FULL)
-                       status |= (VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL);
-               else if (ANAR & ADVERTISE_100HALF)
-                       status |= VELOCITY_SPEED_100;
-               else if (ANAR & ADVERTISE_10FULL)
-                       status |= (VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL);
-               else
-                       status |= (VELOCITY_SPEED_10);
-       }
-
-       if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) {
-               velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
-               if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF))
-                   == (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) {
-                       if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
-                               status |= VELOCITY_AUTONEG_ENABLE;
-               }
-       }
-
-       return status;
-}
-
-/**
- *     velocity_mii_write      -       write MII data
- *     @regs: velocity registers
- *     @index: MII register index
- *     @data: 16bit data for the MII register
- *
- *     Perform a single write to an MII 16bit register. Returns zero
- *     on success or -ETIMEDOUT if the PHY did not respond.
- */
-static int velocity_mii_write(struct mac_regs __iomem *regs, u8 mii_addr, u16 data)
-{
-       u16 ww;
-
-       /*
-        *      Disable MIICR_MAUTO, so that mii addr can be set normally
-        */
-       safe_disable_mii_autopoll(regs);
-
-       /* MII reg offset */
-       writeb(mii_addr, &regs->MIIADR);
-       /* set MII data */
-       writew(data, &regs->MIIDATA);
-
-       /* turn on MIICR_WCMD */
-       BYTE_REG_BITS_ON(MIICR_WCMD, &regs->MIICR);
-
-       /* W_MAX_TIMEOUT is the timeout period */
-       for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
-               udelay(5);
-               if (!(readb(&regs->MIICR) & MIICR_WCMD))
-                       break;
-       }
-       enable_mii_autopoll(regs);
-
-       if (ww == W_MAX_TIMEOUT)
-               return -ETIMEDOUT;
-       return 0;
-}
-
-/**
- *     set_mii_flow_control    -       flow control setup
- *     @vptr: velocity interface
- *
- *     Set up the flow control on this interface according to
- *     the supplied user/eeprom options.
- */
-static void set_mii_flow_control(struct velocity_info *vptr)
-{
-       /*Enable or Disable PAUSE in ANAR */
-       switch (vptr->options.flow_cntl) {
-       case FLOW_CNTL_TX:
-               MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
-               MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
-               break;
-
-       case FLOW_CNTL_RX:
-               MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
-               MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
-               break;
-
-       case FLOW_CNTL_TX_RX:
-               MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
-               MII_REG_BITS_OFF(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
-               break;
-
-       case FLOW_CNTL_DISABLE:
-               MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
-               MII_REG_BITS_OFF(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
-               break;
-       default:
-               break;
-       }
-}
-
-/**
- *     mii_set_auto_on         -       autonegotiate on
- *     @vptr: velocity
- *
- *     Enable autonegotation on this interface
- */
-static void mii_set_auto_on(struct velocity_info *vptr)
-{
-       if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs))
-               MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
-       else
-               MII_REG_BITS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs);
-}
-
-static u32 check_connection_type(struct mac_regs __iomem *regs)
-{
-       u32 status = 0;
-       u8 PHYSR0;
-       u16 ANAR;
-       PHYSR0 = readb(&regs->PHYSR0);
-
-       /*
-          if (!(PHYSR0 & PHYSR0_LINKGD))
-          status|=VELOCITY_LINK_FAIL;
-        */
-
-       if (PHYSR0 & PHYSR0_FDPX)
-               status |= VELOCITY_DUPLEX_FULL;
-
-       if (PHYSR0 & PHYSR0_SPDG)
-               status |= VELOCITY_SPEED_1000;
-       else if (PHYSR0 & PHYSR0_SPD10)
-               status |= VELOCITY_SPEED_10;
-       else
-               status |= VELOCITY_SPEED_100;
-
-       if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) {
-               velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
-               if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF))
-                   == (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) {
-                       if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
-                               status |= VELOCITY_AUTONEG_ENABLE;
-               }
-       }
-
-       return status;
-}
-
-/**
- *     velocity_set_media_mode         -       set media mode
- *     @mii_status: old MII link state
- *
- *     Check the media link state and configure the flow control
- *     PHY and also velocity hardware setup accordingly. In particular
- *     we need to set up CD polling and frame bursting.
- */
-static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status)
-{
-       u32 curr_status;
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-
-       vptr->mii_status = mii_check_media_mode(vptr->mac_regs);
-       curr_status = vptr->mii_status & (~VELOCITY_LINK_FAIL);
-
-       /* Set mii link status */
-       set_mii_flow_control(vptr);
-
-       /*
-          Check if new status is consistent with current status
-          if (((mii_status & curr_status) & VELOCITY_AUTONEG_ENABLE) ||
-              (mii_status==curr_status)) {
-          vptr->mii_status=mii_check_media_mode(vptr->mac_regs);
-          vptr->mii_status=check_connection_type(vptr->mac_regs);
-          VELOCITY_PRT(MSG_LEVEL_INFO, "Velocity link no change\n");
-          return 0;
-          }
-        */
-
-       if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
-               MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
-
-       /*
-        *      If connection type is AUTO
-        */
-       if (mii_status & VELOCITY_AUTONEG_ENABLE) {
-               VELOCITY_PRT(MSG_LEVEL_INFO, "Velocity is AUTO mode\n");
-               /* clear force MAC mode bit */
-               BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, &regs->CHIPGCR);
-               /* set duplex mode of MAC according to duplex mode of MII */
-               MII_REG_BITS_ON(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF, MII_ADVERTISE, vptr->mac_regs);
-               MII_REG_BITS_ON(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
-               MII_REG_BITS_ON(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs);
-
-               /* enable AUTO-NEGO mode */
-               mii_set_auto_on(vptr);
-       } else {
-               u16 CTRL1000;
-               u16 ANAR;
-               u8 CHIPGCR;
-
-               /*
-                * 1. if it's 3119, disable frame bursting in halfduplex mode
-                *    and enable it in fullduplex mode
-                * 2. set correct MII/GMII and half/full duplex mode in CHIPGCR
-                * 3. only enable CD heart beat counter in 10HD mode
-                */
-
-               /* set force MAC mode bit */
-               BYTE_REG_BITS_ON(CHIPGCR_FCMODE, &regs->CHIPGCR);
-
-               CHIPGCR = readb(&regs->CHIPGCR);
-
-               if (mii_status & VELOCITY_SPEED_1000)
-                       CHIPGCR |= CHIPGCR_FCGMII;
-               else
-                       CHIPGCR &= ~CHIPGCR_FCGMII;
-
-               if (mii_status & VELOCITY_DUPLEX_FULL) {
-                       CHIPGCR |= CHIPGCR_FCFDX;
-                       writeb(CHIPGCR, &regs->CHIPGCR);
-                       VELOCITY_PRT(MSG_LEVEL_INFO, "set Velocity to forced full mode\n");
-                       if (vptr->rev_id < REV_ID_VT3216_A0)
-                               BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR);
-               } else {
-                       CHIPGCR &= ~CHIPGCR_FCFDX;
-                       VELOCITY_PRT(MSG_LEVEL_INFO, "set Velocity to forced half mode\n");
-                       writeb(CHIPGCR, &regs->CHIPGCR);
-                       if (vptr->rev_id < REV_ID_VT3216_A0)
-                               BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR);
-               }
-
-               velocity_mii_read(vptr->mac_regs, MII_CTRL1000, &CTRL1000);
-               CTRL1000 &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
-               if ((mii_status & VELOCITY_SPEED_1000) &&
-                   (mii_status & VELOCITY_DUPLEX_FULL)) {
-                       CTRL1000 |= ADVERTISE_1000FULL;
-               }
-               velocity_mii_write(vptr->mac_regs, MII_CTRL1000, CTRL1000);
-
-               if (!(mii_status & VELOCITY_DUPLEX_FULL) && (mii_status & VELOCITY_SPEED_10))
-                       BYTE_REG_BITS_OFF(TESTCFG_HBDIS, &regs->TESTCFG);
-               else
-                       BYTE_REG_BITS_ON(TESTCFG_HBDIS, &regs->TESTCFG);
-
-               /* MII_REG_BITS_OFF(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs); */
-               velocity_mii_read(vptr->mac_regs, MII_ADVERTISE, &ANAR);
-               ANAR &= (~(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF));
-               if (mii_status & VELOCITY_SPEED_100) {
-                       if (mii_status & VELOCITY_DUPLEX_FULL)
-                               ANAR |= ADVERTISE_100FULL;
-                       else
-                               ANAR |= ADVERTISE_100HALF;
-               } else if (mii_status & VELOCITY_SPEED_10) {
-                       if (mii_status & VELOCITY_DUPLEX_FULL)
-                               ANAR |= ADVERTISE_10FULL;
-                       else
-                               ANAR |= ADVERTISE_10HALF;
-               }
-               velocity_mii_write(vptr->mac_regs, MII_ADVERTISE, ANAR);
-               /* enable AUTO-NEGO mode */
-               mii_set_auto_on(vptr);
-               /* MII_REG_BITS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs); */
-       }
-       /* vptr->mii_status=mii_check_media_mode(vptr->mac_regs); */
-       /* vptr->mii_status=check_connection_type(vptr->mac_regs); */
-       return VELOCITY_LINK_CHANGE;
-}
-
-/**
- *     velocity_print_link_status      -       link status reporting
- *     @vptr: velocity to report on
- *
- *     Turn the link status of the velocity card into a kernel log
- *     description of the new link state, detailing speed and duplex
- *     status
- */
-static void velocity_print_link_status(struct velocity_info *vptr)
-{
-
-       if (vptr->mii_status & VELOCITY_LINK_FAIL) {
-               VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->dev->name);
-       } else if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
-               VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->dev->name);
-
-               if (vptr->mii_status & VELOCITY_SPEED_1000)
-                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps");
-               else if (vptr->mii_status & VELOCITY_SPEED_100)
-                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps");
-               else
-                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps");
-
-               if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
-                       VELOCITY_PRT(MSG_LEVEL_INFO, " full duplex\n");
-               else
-                       VELOCITY_PRT(MSG_LEVEL_INFO, " half duplex\n");
-       } else {
-               VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->dev->name);
-               switch (vptr->options.spd_dpx) {
-               case SPD_DPX_1000_FULL:
-                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps full duplex\n");
-                       break;
-               case SPD_DPX_100_HALF:
-                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps half duplex\n");
-                       break;
-               case SPD_DPX_100_FULL:
-                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps full duplex\n");
-                       break;
-               case SPD_DPX_10_HALF:
-                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps half duplex\n");
-                       break;
-               case SPD_DPX_10_FULL:
-                       VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps full duplex\n");
-                       break;
-               default:
-                       break;
-               }
-       }
-}
-
-/**
- *     enable_flow_control_ability     -       flow control
- *     @vptr: veloity to configure
- *
- *     Set up flow control according to the flow control options
- *     determined by the eeprom/configuration.
- */
-static void enable_flow_control_ability(struct velocity_info *vptr)
-{
-
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-
-       switch (vptr->options.flow_cntl) {
-
-       case FLOW_CNTL_DEFAULT:
-               if (BYTE_REG_BITS_IS_ON(PHYSR0_RXFLC, &regs->PHYSR0))
-                       writel(CR0_FDXRFCEN, &regs->CR0Set);
-               else
-                       writel(CR0_FDXRFCEN, &regs->CR0Clr);
-
-               if (BYTE_REG_BITS_IS_ON(PHYSR0_TXFLC, &regs->PHYSR0))
-                       writel(CR0_FDXTFCEN, &regs->CR0Set);
-               else
-                       writel(CR0_FDXTFCEN, &regs->CR0Clr);
-               break;
-
-       case FLOW_CNTL_TX:
-               writel(CR0_FDXTFCEN, &regs->CR0Set);
-               writel(CR0_FDXRFCEN, &regs->CR0Clr);
-               break;
-
-       case FLOW_CNTL_RX:
-               writel(CR0_FDXRFCEN, &regs->CR0Set);
-               writel(CR0_FDXTFCEN, &regs->CR0Clr);
-               break;
-
-       case FLOW_CNTL_TX_RX:
-               writel(CR0_FDXTFCEN, &regs->CR0Set);
-               writel(CR0_FDXRFCEN, &regs->CR0Set);
-               break;
-
-       case FLOW_CNTL_DISABLE:
-               writel(CR0_FDXRFCEN, &regs->CR0Clr);
-               writel(CR0_FDXTFCEN, &regs->CR0Clr);
-               break;
-
-       default:
-               break;
-       }
-
-}
-
-/**
- *     velocity_soft_reset     -       soft reset
- *     @vptr: velocity to reset
- *
- *     Kick off a soft reset of the velocity adapter and then poll
- *     until the reset sequence has completed before returning.
- */
-static int velocity_soft_reset(struct velocity_info *vptr)
-{
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-       int i = 0;
-
-       writel(CR0_SFRST, &regs->CR0Set);
-
-       for (i = 0; i < W_MAX_TIMEOUT; i++) {
-               udelay(5);
-               if (!DWORD_REG_BITS_IS_ON(CR0_SFRST, &regs->CR0Set))
-                       break;
-       }
-
-       if (i == W_MAX_TIMEOUT) {
-               writel(CR0_FORSRST, &regs->CR0Set);
-               /* FIXME: PCI POSTING */
-               /* delay 2ms */
-               mdelay(2);
-       }
-       return 0;
-}
-
-/**
- *     velocity_set_multi      -       filter list change callback
- *     @dev: network device
- *
- *     Called by the network layer when the filter lists need to change
- *     for a velocity adapter. Reload the CAMs with the new address
- *     filter ruleset.
- */
-static void velocity_set_multi(struct net_device *dev)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-       u8 rx_mode;
-       int i;
-       struct netdev_hw_addr *ha;
-
-       if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
-               writel(0xffffffff, &regs->MARCAM[0]);
-               writel(0xffffffff, &regs->MARCAM[4]);
-               rx_mode = (RCR_AM | RCR_AB | RCR_PROM);
-       } else if ((netdev_mc_count(dev) > vptr->multicast_limit) ||
-                  (dev->flags & IFF_ALLMULTI)) {
-               writel(0xffffffff, &regs->MARCAM[0]);
-               writel(0xffffffff, &regs->MARCAM[4]);
-               rx_mode = (RCR_AM | RCR_AB);
-       } else {
-               int offset = MCAM_SIZE - vptr->multicast_limit;
-               mac_get_cam_mask(regs, vptr->mCAMmask);
-
-               i = 0;
-               netdev_for_each_mc_addr(ha, dev) {
-                       mac_set_cam(regs, i + offset, ha->addr);
-                       vptr->mCAMmask[(offset + i) / 8] |= 1 << ((offset + i) & 7);
-                       i++;
-               }
-
-               mac_set_cam_mask(regs, vptr->mCAMmask);
-               rx_mode = RCR_AM | RCR_AB | RCR_AP;
-       }
-       if (dev->mtu > 1500)
-               rx_mode |= RCR_AL;
-
-       BYTE_REG_BITS_ON(rx_mode, &regs->RCR);
-
-}
-
-/*
- * MII access , media link mode setting functions
- */
-
-/**
- *     mii_init        -       set up MII
- *     @vptr: velocity adapter
- *     @mii_status:  links tatus
- *
- *     Set up the PHY for the current link state.
- */
-static void mii_init(struct velocity_info *vptr, u32 mii_status)
-{
-       u16 BMCR;
-
-       switch (PHYID_GET_PHY_ID(vptr->phy_id)) {
-       case PHYID_CICADA_CS8201:
-               /*
-                *      Reset to hardware default
-                */
-               MII_REG_BITS_OFF((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
-               /*
-                *      Turn on ECHODIS bit in NWay-forced full mode and turn it
-                *      off it in NWay-forced half mode for NWay-forced v.s.
-                *      legacy-forced issue.
-                */
-               if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
-                       MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
-               else
-                       MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
-               /*
-                *      Turn on Link/Activity LED enable bit for CIS8201
-                */
-               MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
-               break;
-       case PHYID_VT3216_32BIT:
-       case PHYID_VT3216_64BIT:
-               /*
-                *      Reset to hardware default
-                */
-               MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
-               /*
-                *      Turn on ECHODIS bit in NWay-forced full mode and turn it
-                *      off it in NWay-forced half mode for NWay-forced v.s.
-                *      legacy-forced issue
-                */
-               if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
-                       MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
-               else
-                       MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
-               break;
-
-       case PHYID_MARVELL_1000:
-       case PHYID_MARVELL_1000S:
-               /*
-                *      Assert CRS on Transmit
-                */
-               MII_REG_BITS_ON(PSCR_ACRSTX, MII_REG_PSCR, vptr->mac_regs);
-               /*
-                *      Reset to hardware default
-                */
-               MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
-               break;
-       default:
-               ;
-       }
-       velocity_mii_read(vptr->mac_regs, MII_BMCR, &BMCR);
-       if (BMCR & BMCR_ISOLATE) {
-               BMCR &= ~BMCR_ISOLATE;
-               velocity_mii_write(vptr->mac_regs, MII_BMCR, BMCR);
-       }
-}
-
-/**
- * setup_queue_timers  -       Setup interrupt timers
- *
- * Setup interrupt frequency during suppression (timeout if the frame
- * count isn't filled).
- */
-static void setup_queue_timers(struct velocity_info *vptr)
-{
-       /* Only for newer revisions */
-       if (vptr->rev_id >= REV_ID_VT3216_A0) {
-               u8 txqueue_timer = 0;
-               u8 rxqueue_timer = 0;
-
-               if (vptr->mii_status & (VELOCITY_SPEED_1000 |
-                               VELOCITY_SPEED_100)) {
-                       txqueue_timer = vptr->options.txqueue_timer;
-                       rxqueue_timer = vptr->options.rxqueue_timer;
-               }
-
-               writeb(txqueue_timer, &vptr->mac_regs->TQETMR);
-               writeb(rxqueue_timer, &vptr->mac_regs->RQETMR);
-       }
-}
-
-/**
- * setup_adaptive_interrupts  -  Setup interrupt suppression
- *
- * @vptr velocity adapter
- *
- * The velocity is able to suppress interrupt during high interrupt load.
- * This function turns on that feature.
- */
-static void setup_adaptive_interrupts(struct velocity_info *vptr)
-{
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-       u16 tx_intsup = vptr->options.tx_intsup;
-       u16 rx_intsup = vptr->options.rx_intsup;
-
-       /* Setup default interrupt mask (will be changed below) */
-       vptr->int_mask = INT_MASK_DEF;
-
-       /* Set Tx Interrupt Suppression Threshold */
-       writeb(CAMCR_PS0, &regs->CAMCR);
-       if (tx_intsup != 0) {
-               vptr->int_mask &= ~(ISR_PTXI | ISR_PTX0I | ISR_PTX1I |
-                               ISR_PTX2I | ISR_PTX3I);
-               writew(tx_intsup, &regs->ISRCTL);
-       } else
-               writew(ISRCTL_TSUPDIS, &regs->ISRCTL);
-
-       /* Set Rx Interrupt Suppression Threshold */
-       writeb(CAMCR_PS1, &regs->CAMCR);
-       if (rx_intsup != 0) {
-               vptr->int_mask &= ~ISR_PRXI;
-               writew(rx_intsup, &regs->ISRCTL);
-       } else
-               writew(ISRCTL_RSUPDIS, &regs->ISRCTL);
-
-       /* Select page to interrupt hold timer */
-       writeb(0, &regs->CAMCR);
-}
-
-/**
- *     velocity_init_registers -       initialise MAC registers
- *     @vptr: velocity to init
- *     @type: type of initialisation (hot or cold)
- *
- *     Initialise the MAC on a reset or on first set up on the
- *     hardware.
- */
-static void velocity_init_registers(struct velocity_info *vptr,
-                                   enum velocity_init_type type)
-{
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-       int i, mii_status;
-
-       mac_wol_reset(regs);
-
-       switch (type) {
-       case VELOCITY_INIT_RESET:
-       case VELOCITY_INIT_WOL:
-
-               netif_stop_queue(vptr->dev);
-
-               /*
-                *      Reset RX to prevent RX pointer not on the 4X location
-                */
-               velocity_rx_reset(vptr);
-               mac_rx_queue_run(regs);
-               mac_rx_queue_wake(regs);
-
-               mii_status = velocity_get_opt_media_mode(vptr);
-               if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
-                       velocity_print_link_status(vptr);
-                       if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
-                               netif_wake_queue(vptr->dev);
-               }
-
-               enable_flow_control_ability(vptr);
-
-               mac_clear_isr(regs);
-               writel(CR0_STOP, &regs->CR0Clr);
-               writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT),
-                                                       &regs->CR0Set);
-
-               break;
-
-       case VELOCITY_INIT_COLD:
-       default:
-               /*
-                *      Do reset
-                */
-               velocity_soft_reset(vptr);
-               mdelay(5);
-
-               mac_eeprom_reload(regs);
-               for (i = 0; i < 6; i++)
-                       writeb(vptr->dev->dev_addr[i], &(regs->PAR[i]));
-
-               /*
-                *      clear Pre_ACPI bit.
-                */
-               BYTE_REG_BITS_OFF(CFGA_PACPI, &(regs->CFGA));
-               mac_set_rx_thresh(regs, vptr->options.rx_thresh);
-               mac_set_dma_length(regs, vptr->options.DMA_length);
-
-               writeb(WOLCFG_SAM | WOLCFG_SAB, &regs->WOLCFGSet);
-               /*
-                *      Back off algorithm use original IEEE standard
-                */
-               BYTE_REG_BITS_SET(CFGB_OFSET, (CFGB_CRANDOM | CFGB_CAP | CFGB_MBA | CFGB_BAKOPT), &regs->CFGB);
-
-               /*
-                *      Init CAM filter
-                */
-               velocity_init_cam_filter(vptr);
-
-               /*
-                *      Set packet filter: Receive directed and broadcast address
-                */
-               velocity_set_multi(vptr->dev);
-
-               /*
-                *      Enable MII auto-polling
-                */
-               enable_mii_autopoll(regs);
-
-               setup_adaptive_interrupts(vptr);
-
-               writel(vptr->rx.pool_dma, &regs->RDBaseLo);
-               writew(vptr->options.numrx - 1, &regs->RDCSize);
-               mac_rx_queue_run(regs);
-               mac_rx_queue_wake(regs);
-
-               writew(vptr->options.numtx - 1, &regs->TDCSize);
-
-               for (i = 0; i < vptr->tx.numq; i++) {
-                       writel(vptr->tx.pool_dma[i], &regs->TDBaseLo[i]);
-                       mac_tx_queue_run(regs, i);
-               }
-
-               init_flow_control_register(vptr);
-
-               writel(CR0_STOP, &regs->CR0Clr);
-               writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT), &regs->CR0Set);
-
-               mii_status = velocity_get_opt_media_mode(vptr);
-               netif_stop_queue(vptr->dev);
-
-               mii_init(vptr, mii_status);
-
-               if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
-                       velocity_print_link_status(vptr);
-                       if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
-                               netif_wake_queue(vptr->dev);
-               }
-
-               enable_flow_control_ability(vptr);
-               mac_hw_mibs_init(regs);
-               mac_write_int_mask(vptr->int_mask, regs);
-               mac_clear_isr(regs);
-
-       }
-}
-
-static void velocity_give_many_rx_descs(struct velocity_info *vptr)
-{
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-       int avail, dirty, unusable;
-
-       /*
-        * RD number must be equal to 4X per hardware spec
-        * (programming guide rev 1.20, p.13)
-        */
-       if (vptr->rx.filled < 4)
-               return;
-
-       wmb();
-
-       unusable = vptr->rx.filled & 0x0003;
-       dirty = vptr->rx.dirty - unusable;
-       for (avail = vptr->rx.filled & 0xfffc; avail; avail--) {
-               dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1;
-               vptr->rx.ring[dirty].rdesc0.len |= OWNED_BY_NIC;
-       }
-
-       writew(vptr->rx.filled & 0xfffc, &regs->RBRDU);
-       vptr->rx.filled = unusable;
-}
-
-/**
- *     velocity_init_dma_rings -       set up DMA rings
- *     @vptr: Velocity to set up
- *
- *     Allocate PCI mapped DMA rings for the receive and transmit layer
- *     to use.
- */
-static int velocity_init_dma_rings(struct velocity_info *vptr)
-{
-       struct velocity_opt *opt = &vptr->options;
-       const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc);
-       const unsigned int tx_ring_size = opt->numtx * sizeof(struct tx_desc);
-       struct pci_dev *pdev = vptr->pdev;
-       dma_addr_t pool_dma;
-       void *pool;
-       unsigned int i;
-
-       /*
-        * Allocate all RD/TD rings a single pool.
-        *
-        * pci_alloc_consistent() fulfills the requirement for 64 bytes
-        * alignment
-        */
-       pool = pci_alloc_consistent(pdev, tx_ring_size * vptr->tx.numq +
-                                   rx_ring_size, &pool_dma);
-       if (!pool) {
-               dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
-                       vptr->dev->name);
-               return -ENOMEM;
-       }
-
-       vptr->rx.ring = pool;
-       vptr->rx.pool_dma = pool_dma;
-
-       pool += rx_ring_size;
-       pool_dma += rx_ring_size;
-
-       for (i = 0; i < vptr->tx.numq; i++) {
-               vptr->tx.rings[i] = pool;
-               vptr->tx.pool_dma[i] = pool_dma;
-               pool += tx_ring_size;
-               pool_dma += tx_ring_size;
-       }
-
-       return 0;
-}
-
-static void velocity_set_rxbufsize(struct velocity_info *vptr, int mtu)
-{
-       vptr->rx.buf_sz = (mtu <= ETH_DATA_LEN) ? PKT_BUF_SZ : mtu + 32;
-}
-
-/**
- *     velocity_alloc_rx_buf   -       allocate aligned receive buffer
- *     @vptr: velocity
- *     @idx: ring index
- *
- *     Allocate a new full sized buffer for the reception of a frame and
- *     map it into PCI space for the hardware to use. The hardware
- *     requires *64* byte alignment of the buffer which makes life
- *     less fun than would be ideal.
- */
-static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
-{
-       struct rx_desc *rd = &(vptr->rx.ring[idx]);
-       struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
-
-       rd_info->skb = dev_alloc_skb(vptr->rx.buf_sz + 64);
-       if (rd_info->skb == NULL)
-               return -ENOMEM;
-
-       /*
-        *      Do the gymnastics to get the buffer head for data at
-        *      64byte alignment.
-        */
-       skb_reserve(rd_info->skb,
-                       64 - ((unsigned long) rd_info->skb->data & 63));
-       rd_info->skb_dma = pci_map_single(vptr->pdev, rd_info->skb->data,
-                                       vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
-
-       /*
-        *      Fill in the descriptor to match
-        */
-
-       *((u32 *) & (rd->rdesc0)) = 0;
-       rd->size = cpu_to_le16(vptr->rx.buf_sz) | RX_INTEN;
-       rd->pa_low = cpu_to_le32(rd_info->skb_dma);
-       rd->pa_high = 0;
-       return 0;
-}
-
-
-static int velocity_rx_refill(struct velocity_info *vptr)
-{
-       int dirty = vptr->rx.dirty, done = 0;
-
-       do {
-               struct rx_desc *rd = vptr->rx.ring + dirty;
-
-               /* Fine for an all zero Rx desc at init time as well */
-               if (rd->rdesc0.len & OWNED_BY_NIC)
-                       break;
-
-               if (!vptr->rx.info[dirty].skb) {
-                       if (velocity_alloc_rx_buf(vptr, dirty) < 0)
-                               break;
-               }
-               done++;
-               dirty = (dirty < vptr->options.numrx - 1) ? dirty + 1 : 0;
-       } while (dirty != vptr->rx.curr);
-
-       if (done) {
-               vptr->rx.dirty = dirty;
-               vptr->rx.filled += done;
-       }
-
-       return done;
-}
-
-/**
- *     velocity_free_rd_ring   -       free receive ring
- *     @vptr: velocity to clean up
- *
- *     Free the receive buffers for each ring slot and any
- *     attached socket buffers that need to go away.
- */
-static void velocity_free_rd_ring(struct velocity_info *vptr)
-{
-       int i;
-
-       if (vptr->rx.info == NULL)
-               return;
-
-       for (i = 0; i < vptr->options.numrx; i++) {
-               struct velocity_rd_info *rd_info = &(vptr->rx.info[i]);
-               struct rx_desc *rd = vptr->rx.ring + i;
-
-               memset(rd, 0, sizeof(*rd));
-
-               if (!rd_info->skb)
-                       continue;
-               pci_unmap_single(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
-                                PCI_DMA_FROMDEVICE);
-               rd_info->skb_dma = 0;
-
-               dev_kfree_skb(rd_info->skb);
-               rd_info->skb = NULL;
-       }
-
-       kfree(vptr->rx.info);
-       vptr->rx.info = NULL;
-}
-
-/**
- *     velocity_init_rd_ring   -       set up receive ring
- *     @vptr: velocity to configure
- *
- *     Allocate and set up the receive buffers for each ring slot and
- *     assign them to the network adapter.
- */
-static int velocity_init_rd_ring(struct velocity_info *vptr)
-{
-       int ret = -ENOMEM;
-
-       vptr->rx.info = kcalloc(vptr->options.numrx,
-                               sizeof(struct velocity_rd_info), GFP_KERNEL);
-       if (!vptr->rx.info)
-               goto out;
-
-       velocity_init_rx_ring_indexes(vptr);
-
-       if (velocity_rx_refill(vptr) != vptr->options.numrx) {
-               VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR
-                       "%s: failed to allocate RX buffer.\n", vptr->dev->name);
-               velocity_free_rd_ring(vptr);
-               goto out;
-       }
-
-       ret = 0;
-out:
-       return ret;
-}
-
-/**
- *     velocity_init_td_ring   -       set up transmit ring
- *     @vptr:  velocity
- *
- *     Set up the transmit ring and chain the ring pointers together.
- *     Returns zero on success or a negative posix errno code for
- *     failure.
- */
-static int velocity_init_td_ring(struct velocity_info *vptr)
-{
-       int j;
-
-       /* Init the TD ring entries */
-       for (j = 0; j < vptr->tx.numq; j++) {
-
-               vptr->tx.infos[j] = kcalloc(vptr->options.numtx,
-                                           sizeof(struct velocity_td_info),
-                                           GFP_KERNEL);
-               if (!vptr->tx.infos[j]) {
-                       while (--j >= 0)
-                               kfree(vptr->tx.infos[j]);
-                       return -ENOMEM;
-               }
-
-               vptr->tx.tail[j] = vptr->tx.curr[j] = vptr->tx.used[j] = 0;
-       }
-       return 0;
-}
-
-/**
- *     velocity_free_dma_rings -       free PCI ring pointers
- *     @vptr: Velocity to free from
- *
- *     Clean up the PCI ring buffers allocated to this velocity.
- */
-static void velocity_free_dma_rings(struct velocity_info *vptr)
-{
-       const int size = vptr->options.numrx * sizeof(struct rx_desc) +
-               vptr->options.numtx * sizeof(struct tx_desc) * vptr->tx.numq;
-
-       pci_free_consistent(vptr->pdev, size, vptr->rx.ring, vptr->rx.pool_dma);
-}
-
-static int velocity_init_rings(struct velocity_info *vptr, int mtu)
-{
-       int ret;
-
-       velocity_set_rxbufsize(vptr, mtu);
-
-       ret = velocity_init_dma_rings(vptr);
-       if (ret < 0)
-               goto out;
-
-       ret = velocity_init_rd_ring(vptr);
-       if (ret < 0)
-               goto err_free_dma_rings_0;
-
-       ret = velocity_init_td_ring(vptr);
-       if (ret < 0)
-               goto err_free_rd_ring_1;
-out:
-       return ret;
-
-err_free_rd_ring_1:
-       velocity_free_rd_ring(vptr);
-err_free_dma_rings_0:
-       velocity_free_dma_rings(vptr);
-       goto out;
-}
-
-/**
- *     velocity_free_tx_buf    -       free transmit buffer
- *     @vptr: velocity
- *     @tdinfo: buffer
- *
- *     Release an transmit buffer. If the buffer was preallocated then
- *     recycle it, if not then unmap the buffer.
- */
-static void velocity_free_tx_buf(struct velocity_info *vptr,
-               struct velocity_td_info *tdinfo, struct tx_desc *td)
-{
-       struct sk_buff *skb = tdinfo->skb;
-
-       /*
-        *      Don't unmap the pre-allocated tx_bufs
-        */
-       if (tdinfo->skb_dma) {
-               int i;
-
-               for (i = 0; i < tdinfo->nskb_dma; i++) {
-                       size_t pktlen = max_t(size_t, skb->len, ETH_ZLEN);
-
-                       /* For scatter-gather */
-                       if (skb_shinfo(skb)->nr_frags > 0)
-                               pktlen = max_t(size_t, pktlen,
-                                               td->td_buf[i].size & ~TD_QUEUE);
-
-                       pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i],
-                                       le16_to_cpu(pktlen), PCI_DMA_TODEVICE);
-               }
-       }
-       dev_kfree_skb_irq(skb);
-       tdinfo->skb = NULL;
-}
-
-/*
- *     FIXME: could we merge this with velocity_free_tx_buf ?
- */
-static void velocity_free_td_ring_entry(struct velocity_info *vptr,
-                                                        int q, int n)
-{
-       struct velocity_td_info *td_info = &(vptr->tx.infos[q][n]);
-       int i;
-
-       if (td_info == NULL)
-               return;
-
-       if (td_info->skb) {
-               for (i = 0; i < td_info->nskb_dma; i++) {
-                       if (td_info->skb_dma[i]) {
-                               pci_unmap_single(vptr->pdev, td_info->skb_dma[i],
-                                       td_info->skb->len, PCI_DMA_TODEVICE);
-                               td_info->skb_dma[i] = 0;
-                       }
-               }
-               dev_kfree_skb(td_info->skb);
-               td_info->skb = NULL;
-       }
-}
-
-/**
- *     velocity_free_td_ring   -       free td ring
- *     @vptr: velocity
- *
- *     Free up the transmit ring for this particular velocity adapter.
- *     We free the ring contents but not the ring itself.
- */
-static void velocity_free_td_ring(struct velocity_info *vptr)
-{
-       int i, j;
-
-       for (j = 0; j < vptr->tx.numq; j++) {
-               if (vptr->tx.infos[j] == NULL)
-                       continue;
-               for (i = 0; i < vptr->options.numtx; i++)
-                       velocity_free_td_ring_entry(vptr, j, i);
-
-               kfree(vptr->tx.infos[j]);
-               vptr->tx.infos[j] = NULL;
-       }
-}
-
-static void velocity_free_rings(struct velocity_info *vptr)
-{
-       velocity_free_td_ring(vptr);
-       velocity_free_rd_ring(vptr);
-       velocity_free_dma_rings(vptr);
-}
-
-/**
- *     velocity_error  -       handle error from controller
- *     @vptr: velocity
- *     @status: card status
- *
- *     Process an error report from the hardware and attempt to recover
- *     the card itself. At the moment we cannot recover from some
- *     theoretically impossible errors but this could be fixed using
- *     the pci_device_failed logic to bounce the hardware
- *
- */
-static void velocity_error(struct velocity_info *vptr, int status)
-{
-
-       if (status & ISR_TXSTLI) {
-               struct mac_regs __iomem *regs = vptr->mac_regs;
-
-               printk(KERN_ERR "TD structure error TDindex=%hx\n", readw(&regs->TDIdx[0]));
-               BYTE_REG_BITS_ON(TXESR_TDSTR, &regs->TXESR);
-               writew(TRDCSR_RUN, &regs->TDCSRClr);
-               netif_stop_queue(vptr->dev);
-
-               /* FIXME: port over the pci_device_failed code and use it
-                  here */
-       }
-
-       if (status & ISR_SRCI) {
-               struct mac_regs __iomem *regs = vptr->mac_regs;
-               int linked;
-
-               if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
-                       vptr->mii_status = check_connection_type(regs);
-
-                       /*
-                        *      If it is a 3119, disable frame bursting in
-                        *      halfduplex mode and enable it in fullduplex
-                        *       mode
-                        */
-                       if (vptr->rev_id < REV_ID_VT3216_A0) {
-                               if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
-                                       BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR);
-                               else
-                                       BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR);
-                       }
-                       /*
-                        *      Only enable CD heart beat counter in 10HD mode
-                        */
-                       if (!(vptr->mii_status & VELOCITY_DUPLEX_FULL) && (vptr->mii_status & VELOCITY_SPEED_10))
-                               BYTE_REG_BITS_OFF(TESTCFG_HBDIS, &regs->TESTCFG);
-                       else
-                               BYTE_REG_BITS_ON(TESTCFG_HBDIS, &regs->TESTCFG);
-
-                       setup_queue_timers(vptr);
-               }
-               /*
-                *      Get link status from PHYSR0
-                */
-               linked = readb(&regs->PHYSR0) & PHYSR0_LINKGD;
-
-               if (linked) {
-                       vptr->mii_status &= ~VELOCITY_LINK_FAIL;
-                       netif_carrier_on(vptr->dev);
-               } else {
-                       vptr->mii_status |= VELOCITY_LINK_FAIL;
-                       netif_carrier_off(vptr->dev);
-               }
-
-               velocity_print_link_status(vptr);
-               enable_flow_control_ability(vptr);
-
-               /*
-                *      Re-enable auto-polling because SRCI will disable
-                *      auto-polling
-                */
-
-               enable_mii_autopoll(regs);
-
-               if (vptr->mii_status & VELOCITY_LINK_FAIL)
-                       netif_stop_queue(vptr->dev);
-               else
-                       netif_wake_queue(vptr->dev);
-
-       }
-       if (status & ISR_MIBFI)
-               velocity_update_hw_mibs(vptr);
-       if (status & ISR_LSTEI)
-               mac_rx_queue_wake(vptr->mac_regs);
-}
-
-/**
- *     tx_srv          -       transmit interrupt service
- *     @vptr; Velocity
- *
- *     Scan the queues looking for transmitted packets that
- *     we can complete and clean up. Update any statistics as
- *     necessary/
- */
-static int velocity_tx_srv(struct velocity_info *vptr)
-{
-       struct tx_desc *td;
-       int qnum;
-       int full = 0;
-       int idx;
-       int works = 0;
-       struct velocity_td_info *tdinfo;
-       struct net_device_stats *stats = &vptr->dev->stats;
-
-       for (qnum = 0; qnum < vptr->tx.numq; qnum++) {
-               for (idx = vptr->tx.tail[qnum]; vptr->tx.used[qnum] > 0;
-                       idx = (idx + 1) % vptr->options.numtx) {
-
-                       /*
-                        *      Get Tx Descriptor
-                        */
-                       td = &(vptr->tx.rings[qnum][idx]);
-                       tdinfo = &(vptr->tx.infos[qnum][idx]);
-
-                       if (td->tdesc0.len & OWNED_BY_NIC)
-                               break;
-
-                       if ((works++ > 15))
-                               break;
-
-                       if (td->tdesc0.TSR & TSR0_TERR) {
-                               stats->tx_errors++;
-                               stats->tx_dropped++;
-                               if (td->tdesc0.TSR & TSR0_CDH)
-                                       stats->tx_heartbeat_errors++;
-                               if (td->tdesc0.TSR & TSR0_CRS)
-                                       stats->tx_carrier_errors++;
-                               if (td->tdesc0.TSR & TSR0_ABT)
-                                       stats->tx_aborted_errors++;
-                               if (td->tdesc0.TSR & TSR0_OWC)
-                                       stats->tx_window_errors++;
-                       } else {
-                               stats->tx_packets++;
-                               stats->tx_bytes += tdinfo->skb->len;
-                       }
-                       velocity_free_tx_buf(vptr, tdinfo, td);
-                       vptr->tx.used[qnum]--;
-               }
-               vptr->tx.tail[qnum] = idx;
-
-               if (AVAIL_TD(vptr, qnum) < 1)
-                       full = 1;
-       }
-       /*
-        *      Look to see if we should kick the transmit network
-        *      layer for more work.
-        */
-       if (netif_queue_stopped(vptr->dev) && (full == 0) &&
-           (!(vptr->mii_status & VELOCITY_LINK_FAIL))) {
-               netif_wake_queue(vptr->dev);
-       }
-       return works;
-}
-
-/**
- *     velocity_rx_csum        -       checksum process
- *     @rd: receive packet descriptor
- *     @skb: network layer packet buffer
- *
- *     Process the status bits for the received packet and determine
- *     if the checksum was computed and verified by the hardware
- */
-static inline void velocity_rx_csum(struct rx_desc *rd, struct sk_buff *skb)
-{
-       skb_checksum_none_assert(skb);
-
-       if (rd->rdesc1.CSM & CSM_IPKT) {
-               if (rd->rdesc1.CSM & CSM_IPOK) {
-                       if ((rd->rdesc1.CSM & CSM_TCPKT) ||
-                                       (rd->rdesc1.CSM & CSM_UDPKT)) {
-                               if (!(rd->rdesc1.CSM & CSM_TUPOK))
-                                       return;
-                       }
-                       skb->ip_summed = CHECKSUM_UNNECESSARY;
-               }
-       }
-}
-
-/**
- *     velocity_rx_copy        -       in place Rx copy for small packets
- *     @rx_skb: network layer packet buffer candidate
- *     @pkt_size: received data size
- *     @rd: receive packet descriptor
- *     @dev: network device
- *
- *     Replace the current skb that is scheduled for Rx processing by a
- *     shorter, immediately allocated skb, if the received packet is small
- *     enough. This function returns a negative value if the received
- *     packet is too big or if memory is exhausted.
- */
-static int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
-                           struct velocity_info *vptr)
-{
-       int ret = -1;
-       if (pkt_size < rx_copybreak) {
-               struct sk_buff *new_skb;
-
-               new_skb = netdev_alloc_skb_ip_align(vptr->dev, pkt_size);
-               if (new_skb) {
-                       new_skb->ip_summed = rx_skb[0]->ip_summed;
-                       skb_copy_from_linear_data(*rx_skb, new_skb->data, pkt_size);
-                       *rx_skb = new_skb;
-                       ret = 0;
-               }
-
-       }
-       return ret;
-}
-
-/**
- *     velocity_iph_realign    -       IP header alignment
- *     @vptr: velocity we are handling
- *     @skb: network layer packet buffer
- *     @pkt_size: received data size
- *
- *     Align IP header on a 2 bytes boundary. This behavior can be
- *     configured by the user.
- */
-static inline void velocity_iph_realign(struct velocity_info *vptr,
-                                       struct sk_buff *skb, int pkt_size)
-{
-       if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN) {
-               memmove(skb->data + 2, skb->data, pkt_size);
-               skb_reserve(skb, 2);
-       }
-}
-
-/**
- *     velocity_receive_frame  -       received packet processor
- *     @vptr: velocity we are handling
- *     @idx: ring index
- *
- *     A packet has arrived. We process the packet and if appropriate
- *     pass the frame up the network stack
- */
-static int velocity_receive_frame(struct velocity_info *vptr, int idx)
-{
-       void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
-       struct net_device_stats *stats = &vptr->dev->stats;
-       struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
-       struct rx_desc *rd = &(vptr->rx.ring[idx]);
-       int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff;
-       struct sk_buff *skb;
-
-       if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
-               VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->dev->name);
-               stats->rx_length_errors++;
-               return -EINVAL;
-       }
-
-       if (rd->rdesc0.RSR & RSR_MAR)
-               stats->multicast++;
-
-       skb = rd_info->skb;
-
-       pci_dma_sync_single_for_cpu(vptr->pdev, rd_info->skb_dma,
-                                   vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
-
-       /*
-        *      Drop frame not meeting IEEE 802.3
-        */
-
-       if (vptr->flags & VELOCITY_FLAGS_VAL_PKT_LEN) {
-               if (rd->rdesc0.RSR & RSR_RL) {
-                       stats->rx_length_errors++;
-                       return -EINVAL;
-               }
-       }
-
-       pci_action = pci_dma_sync_single_for_device;
-
-       velocity_rx_csum(rd, skb);
-
-       if (velocity_rx_copy(&skb, pkt_len, vptr) < 0) {
-               velocity_iph_realign(vptr, skb, pkt_len);
-               pci_action = pci_unmap_single;
-               rd_info->skb = NULL;
-       }
-
-       pci_action(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
-                  PCI_DMA_FROMDEVICE);
-
-       skb_put(skb, pkt_len - 4);
-       skb->protocol = eth_type_trans(skb, vptr->dev);
-
-       if (rd->rdesc0.RSR & RSR_DETAG) {
-               u16 vid = swab16(le16_to_cpu(rd->rdesc1.PQTAG));
-
-               __vlan_hwaccel_put_tag(skb, vid);
-       }
-       netif_rx(skb);
-
-       stats->rx_bytes += pkt_len;
-       stats->rx_packets++;
-
-       return 0;
-}
-
-/**
- *     velocity_rx_srv         -       service RX interrupt
- *     @vptr: velocity
- *
- *     Walk the receive ring of the velocity adapter and remove
- *     any received packets from the receive queue. Hand the ring
- *     slots back to the adapter for reuse.
- */
-static int velocity_rx_srv(struct velocity_info *vptr, int budget_left)
-{
-       struct net_device_stats *stats = &vptr->dev->stats;
-       int rd_curr = vptr->rx.curr;
-       int works = 0;
-
-       while (works < budget_left) {
-               struct rx_desc *rd = vptr->rx.ring + rd_curr;
-
-               if (!vptr->rx.info[rd_curr].skb)
-                       break;
-
-               if (rd->rdesc0.len & OWNED_BY_NIC)
-                       break;
-
-               rmb();
-
-               /*
-                *      Don't drop CE or RL error frame although RXOK is off
-                */
-               if (rd->rdesc0.RSR & (RSR_RXOK | RSR_CE | RSR_RL)) {
-                       if (velocity_receive_frame(vptr, rd_curr) < 0)
-                               stats->rx_dropped++;
-               } else {
-                       if (rd->rdesc0.RSR & RSR_CRC)
-                               stats->rx_crc_errors++;
-                       if (rd->rdesc0.RSR & RSR_FAE)
-                               stats->rx_frame_errors++;
-
-                       stats->rx_dropped++;
-               }
-
-               rd->size |= RX_INTEN;
-
-               rd_curr++;
-               if (rd_curr >= vptr->options.numrx)
-                       rd_curr = 0;
-               works++;
-       }
-
-       vptr->rx.curr = rd_curr;
-
-       if ((works > 0) && (velocity_rx_refill(vptr) > 0))
-               velocity_give_many_rx_descs(vptr);
-
-       VAR_USED(stats);
-       return works;
-}
-
-static int velocity_poll(struct napi_struct *napi, int budget)
-{
-       struct velocity_info *vptr = container_of(napi,
-                       struct velocity_info, napi);
-       unsigned int rx_done;
-       unsigned long flags;
-
-       spin_lock_irqsave(&vptr->lock, flags);
-       /*
-        * Do rx and tx twice for performance (taken from the VIA
-        * out-of-tree driver).
-        */
-       rx_done = velocity_rx_srv(vptr, budget / 2);
-       velocity_tx_srv(vptr);
-       rx_done += velocity_rx_srv(vptr, budget - rx_done);
-       velocity_tx_srv(vptr);
-
-       /* If budget not fully consumed, exit the polling mode */
-       if (rx_done < budget) {
-               napi_complete(napi);
-               mac_enable_int(vptr->mac_regs);
-       }
-       spin_unlock_irqrestore(&vptr->lock, flags);
-
-       return rx_done;
-}
-
-/**
- *     velocity_intr           -       interrupt callback
- *     @irq: interrupt number
- *     @dev_instance: interrupting device
- *
- *     Called whenever an interrupt is generated by the velocity
- *     adapter IRQ line. We may not be the source of the interrupt
- *     and need to identify initially if we are, and if not exit as
- *     efficiently as possible.
- */
-static irqreturn_t velocity_intr(int irq, void *dev_instance)
-{
-       struct net_device *dev = dev_instance;
-       struct velocity_info *vptr = netdev_priv(dev);
-       u32 isr_status;
-
-       spin_lock(&vptr->lock);
-       isr_status = mac_read_isr(vptr->mac_regs);
-
-       /* Not us ? */
-       if (isr_status == 0) {
-               spin_unlock(&vptr->lock);
-               return IRQ_NONE;
-       }
-
-       /* Ack the interrupt */
-       mac_write_isr(vptr->mac_regs, isr_status);
-
-       if (likely(napi_schedule_prep(&vptr->napi))) {
-               mac_disable_int(vptr->mac_regs);
-               __napi_schedule(&vptr->napi);
-       }
-
-       if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI)))
-               velocity_error(vptr, isr_status);
-
-       spin_unlock(&vptr->lock);
-
-       return IRQ_HANDLED;
-}
-
-/**
- *     velocity_open           -       interface activation callback
- *     @dev: network layer device to open
- *
- *     Called when the network layer brings the interface up. Returns
- *     a negative posix error code on failure, or zero on success.
- *
- *     All the ring allocation and set up is done on open for this
- *     adapter to minimise memory usage when inactive
- */
-static int velocity_open(struct net_device *dev)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-       int ret;
-
-       ret = velocity_init_rings(vptr, dev->mtu);
-       if (ret < 0)
-               goto out;
-
-       /* Ensure chip is running */
-       pci_set_power_state(vptr->pdev, PCI_D0);
-
-       velocity_init_registers(vptr, VELOCITY_INIT_COLD);
-
-       ret = request_irq(vptr->pdev->irq, velocity_intr, IRQF_SHARED,
-                         dev->name, dev);
-       if (ret < 0) {
-               /* Power down the chip */
-               pci_set_power_state(vptr->pdev, PCI_D3hot);
-               velocity_free_rings(vptr);
-               goto out;
-       }
-
-       velocity_give_many_rx_descs(vptr);
-
-       mac_enable_int(vptr->mac_regs);
-       netif_start_queue(dev);
-       napi_enable(&vptr->napi);
-       vptr->flags |= VELOCITY_FLAGS_OPENED;
-out:
-       return ret;
-}
-
-/**
- *     velocity_shutdown       -       shut down the chip
- *     @vptr: velocity to deactivate
- *
- *     Shuts down the internal operations of the velocity and
- *     disables interrupts, autopolling, transmit and receive
- */
-static void velocity_shutdown(struct velocity_info *vptr)
-{
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-       mac_disable_int(regs);
-       writel(CR0_STOP, &regs->CR0Set);
-       writew(0xFFFF, &regs->TDCSRClr);
-       writeb(0xFF, &regs->RDCSRClr);
-       safe_disable_mii_autopoll(regs);
-       mac_clear_isr(regs);
-}
-
-/**
- *     velocity_change_mtu     -       MTU change callback
- *     @dev: network device
- *     @new_mtu: desired MTU
- *
- *     Handle requests from the networking layer for MTU change on
- *     this interface. It gets called on a change by the network layer.
- *     Return zero for success or negative posix error code.
- */
-static int velocity_change_mtu(struct net_device *dev, int new_mtu)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-       int ret = 0;
-
-       if ((new_mtu < VELOCITY_MIN_MTU) || new_mtu > (VELOCITY_MAX_MTU)) {
-               VELOCITY_PRT(MSG_LEVEL_ERR, KERN_NOTICE "%s: Invalid MTU.\n",
-                               vptr->dev->name);
-               ret = -EINVAL;
-               goto out_0;
-       }
-
-       if (!netif_running(dev)) {
-               dev->mtu = new_mtu;
-               goto out_0;
-       }
-
-       if (dev->mtu != new_mtu) {
-               struct velocity_info *tmp_vptr;
-               unsigned long flags;
-               struct rx_info rx;
-               struct tx_info tx;
-
-               tmp_vptr = kzalloc(sizeof(*tmp_vptr), GFP_KERNEL);
-               if (!tmp_vptr) {
-                       ret = -ENOMEM;
-                       goto out_0;
-               }
-
-               tmp_vptr->dev = dev;
-               tmp_vptr->pdev = vptr->pdev;
-               tmp_vptr->options = vptr->options;
-               tmp_vptr->tx.numq = vptr->tx.numq;
-
-               ret = velocity_init_rings(tmp_vptr, new_mtu);
-               if (ret < 0)
-                       goto out_free_tmp_vptr_1;
-
-               spin_lock_irqsave(&vptr->lock, flags);
-
-               netif_stop_queue(dev);
-               velocity_shutdown(vptr);
-
-               rx = vptr->rx;
-               tx = vptr->tx;
-
-               vptr->rx = tmp_vptr->rx;
-               vptr->tx = tmp_vptr->tx;
-
-               tmp_vptr->rx = rx;
-               tmp_vptr->tx = tx;
-
-               dev->mtu = new_mtu;
-
-               velocity_init_registers(vptr, VELOCITY_INIT_COLD);
-
-               velocity_give_many_rx_descs(vptr);
-
-               mac_enable_int(vptr->mac_regs);
-               netif_start_queue(dev);
-
-               spin_unlock_irqrestore(&vptr->lock, flags);
-
-               velocity_free_rings(tmp_vptr);
-
-out_free_tmp_vptr_1:
-               kfree(tmp_vptr);
-       }
-out_0:
-       return ret;
-}
-
-/**
- *     velocity_mii_ioctl              -       MII ioctl handler
- *     @dev: network device
- *     @ifr: the ifreq block for the ioctl
- *     @cmd: the command
- *
- *     Process MII requests made via ioctl from the network layer. These
- *     are used by tools like kudzu to interrogate the link state of the
- *     hardware
- */
-static int velocity_mii_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-       unsigned long flags;
-       struct mii_ioctl_data *miidata = if_mii(ifr);
-       int err;
-
-       switch (cmd) {
-       case SIOCGMIIPHY:
-               miidata->phy_id = readb(&regs->MIIADR) & 0x1f;
-               break;
-       case SIOCGMIIREG:
-               if (velocity_mii_read(vptr->mac_regs, miidata->reg_num & 0x1f, &(miidata->val_out)) < 0)
-                       return -ETIMEDOUT;
-               break;
-       case SIOCSMIIREG:
-               spin_lock_irqsave(&vptr->lock, flags);
-               err = velocity_mii_write(vptr->mac_regs, miidata->reg_num & 0x1f, miidata->val_in);
-               spin_unlock_irqrestore(&vptr->lock, flags);
-               check_connection_type(vptr->mac_regs);
-               if (err)
-                       return err;
-               break;
-       default:
-               return -EOPNOTSUPP;
-       }
-       return 0;
-}
-
-/**
- *     velocity_ioctl          -       ioctl entry point
- *     @dev: network device
- *     @rq: interface request ioctl
- *     @cmd: command code
- *
- *     Called when the user issues an ioctl request to the network
- *     device in question. The velocity interface supports MII.
- */
-static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-       int ret;
-
-       /* If we are asked for information and the device is power
-          saving then we need to bring the device back up to talk to it */
-
-       if (!netif_running(dev))
-               pci_set_power_state(vptr->pdev, PCI_D0);
-
-       switch (cmd) {
-       case SIOCGMIIPHY:       /* Get address of MII PHY in use. */
-       case SIOCGMIIREG:       /* Read MII PHY register. */
-       case SIOCSMIIREG:       /* Write to MII PHY register. */
-               ret = velocity_mii_ioctl(dev, rq, cmd);
-               break;
-
-       default:
-               ret = -EOPNOTSUPP;
-       }
-       if (!netif_running(dev))
-               pci_set_power_state(vptr->pdev, PCI_D3hot);
-
-
-       return ret;
-}
-
-/**
- *     velocity_get_status     -       statistics callback
- *     @dev: network device
- *
- *     Callback from the network layer to allow driver statistics
- *     to be resynchronized with hardware collected state. In the
- *     case of the velocity we need to pull the MIB counters from
- *     the hardware into the counters before letting the network
- *     layer display them.
- */
-static struct net_device_stats *velocity_get_stats(struct net_device *dev)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-
-       /* If the hardware is down, don't touch MII */
-       if (!netif_running(dev))
-               return &dev->stats;
-
-       spin_lock_irq(&vptr->lock);
-       velocity_update_hw_mibs(vptr);
-       spin_unlock_irq(&vptr->lock);
-
-       dev->stats.rx_packets = vptr->mib_counter[HW_MIB_ifRxAllPkts];
-       dev->stats.rx_errors = vptr->mib_counter[HW_MIB_ifRxErrorPkts];
-       dev->stats.rx_length_errors = vptr->mib_counter[HW_MIB_ifInRangeLengthErrors];
-
-//  unsigned long   rx_dropped;     /* no space in linux buffers    */
-       dev->stats.collisions = vptr->mib_counter[HW_MIB_ifTxEtherCollisions];
-       /* detailed rx_errors: */
-//  unsigned long   rx_length_errors;
-//  unsigned long   rx_over_errors;     /* receiver ring buff overflow  */
-       dev->stats.rx_crc_errors = vptr->mib_counter[HW_MIB_ifRxPktCRCE];
-//  unsigned long   rx_frame_errors;    /* recv'd frame alignment error */
-//  unsigned long   rx_fifo_errors;     /* recv'r fifo overrun      */
-//  unsigned long   rx_missed_errors;   /* receiver missed packet   */
-
-       /* detailed tx_errors */
-//  unsigned long   tx_fifo_errors;
-
-       return &dev->stats;
-}
-
-/**
- *     velocity_close          -       close adapter callback
- *     @dev: network device
- *
- *     Callback from the network layer when the velocity is being
- *     deactivated by the network layer
- */
-static int velocity_close(struct net_device *dev)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-
-       napi_disable(&vptr->napi);
-       netif_stop_queue(dev);
-       velocity_shutdown(vptr);
-
-       if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED)
-               velocity_get_ip(vptr);
-       if (dev->irq != 0)
-               free_irq(dev->irq, dev);
-
-       /* Power down the chip */
-       pci_set_power_state(vptr->pdev, PCI_D3hot);
-
-       velocity_free_rings(vptr);
-
-       vptr->flags &= (~VELOCITY_FLAGS_OPENED);
-       return 0;
-}
-
-/**
- *     velocity_xmit           -       transmit packet callback
- *     @skb: buffer to transmit
- *     @dev: network device
- *
- *     Called by the networ layer to request a packet is queued to
- *     the velocity. Returns zero on success.
- */
-static netdev_tx_t velocity_xmit(struct sk_buff *skb,
-                                struct net_device *dev)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-       int qnum = 0;
-       struct tx_desc *td_ptr;
-       struct velocity_td_info *tdinfo;
-       unsigned long flags;
-       int pktlen;
-       int index, prev;
-       int i = 0;
-
-       if (skb_padto(skb, ETH_ZLEN))
-               goto out;
-
-       /* The hardware can handle at most 7 memory segments, so merge
-        * the skb if there are more */
-       if (skb_shinfo(skb)->nr_frags > 6 && __skb_linearize(skb)) {
-               kfree_skb(skb);
-               return NETDEV_TX_OK;
-       }
-
-       pktlen = skb_shinfo(skb)->nr_frags == 0 ?
-                       max_t(unsigned int, skb->len, ETH_ZLEN) :
-                               skb_headlen(skb);
-
-       spin_lock_irqsave(&vptr->lock, flags);
-
-       index = vptr->tx.curr[qnum];
-       td_ptr = &(vptr->tx.rings[qnum][index]);
-       tdinfo = &(vptr->tx.infos[qnum][index]);
-
-       td_ptr->tdesc1.TCR = TCR0_TIC;
-       td_ptr->td_buf[0].size &= ~TD_QUEUE;
-
-       /*
-        *      Map the linear network buffer into PCI space and
-        *      add it to the transmit ring.
-        */
-       tdinfo->skb = skb;
-       tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE);
-       td_ptr->tdesc0.len = cpu_to_le16(pktlen);
-       td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
-       td_ptr->td_buf[0].pa_high = 0;
-       td_ptr->td_buf[0].size = cpu_to_le16(pktlen);
-
-       /* Handle fragments */
-       for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
-               skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
-
-               tdinfo->skb_dma[i + 1] = pci_map_page(vptr->pdev, frag->page,
-                               frag->page_offset, frag->size,
-                               PCI_DMA_TODEVICE);
-
-               td_ptr->td_buf[i + 1].pa_low = cpu_to_le32(tdinfo->skb_dma[i + 1]);
-               td_ptr->td_buf[i + 1].pa_high = 0;
-               td_ptr->td_buf[i + 1].size = cpu_to_le16(frag->size);
-       }
-       tdinfo->nskb_dma = i + 1;
-
-       td_ptr->tdesc1.cmd = TCPLS_NORMAL + (tdinfo->nskb_dma + 1) * 16;
-
-       if (vlan_tx_tag_present(skb)) {
-               td_ptr->tdesc1.vlan = cpu_to_le16(vlan_tx_tag_get(skb));
-               td_ptr->tdesc1.TCR |= TCR0_VETAG;
-       }
-
-       /*
-        *      Handle hardware checksum
-        */
-       if (skb->ip_summed == CHECKSUM_PARTIAL) {
-               const struct iphdr *ip = ip_hdr(skb);
-               if (ip->protocol == IPPROTO_TCP)
-                       td_ptr->tdesc1.TCR |= TCR0_TCPCK;
-               else if (ip->protocol == IPPROTO_UDP)
-                       td_ptr->tdesc1.TCR |= (TCR0_UDPCK);
-               td_ptr->tdesc1.TCR |= TCR0_IPCK;
-       }
-
-       prev = index - 1;
-       if (prev < 0)
-               prev = vptr->options.numtx - 1;
-       td_ptr->tdesc0.len |= OWNED_BY_NIC;
-       vptr->tx.used[qnum]++;
-       vptr->tx.curr[qnum] = (index + 1) % vptr->options.numtx;
-
-       if (AVAIL_TD(vptr, qnum) < 1)
-               netif_stop_queue(dev);
-
-       td_ptr = &(vptr->tx.rings[qnum][prev]);
-       td_ptr->td_buf[0].size |= TD_QUEUE;
-       mac_tx_queue_wake(vptr->mac_regs, qnum);
-
-       spin_unlock_irqrestore(&vptr->lock, flags);
-out:
-       return NETDEV_TX_OK;
-}
-
-static const struct net_device_ops velocity_netdev_ops = {
-       .ndo_open               = velocity_open,
-       .ndo_stop               = velocity_close,
-       .ndo_start_xmit         = velocity_xmit,
-       .ndo_get_stats          = velocity_get_stats,
-       .ndo_validate_addr      = eth_validate_addr,
-       .ndo_set_mac_address    = eth_mac_addr,
-       .ndo_set_multicast_list = velocity_set_multi,
-       .ndo_change_mtu         = velocity_change_mtu,
-       .ndo_do_ioctl           = velocity_ioctl,
-       .ndo_vlan_rx_add_vid    = velocity_vlan_rx_add_vid,
-       .ndo_vlan_rx_kill_vid   = velocity_vlan_rx_kill_vid,
-};
-
-/**
- *     velocity_init_info      -       init private data
- *     @pdev: PCI device
- *     @vptr: Velocity info
- *     @info: Board type
- *
- *     Set up the initial velocity_info struct for the device that has been
- *     discovered.
- */
-static void __devinit velocity_init_info(struct pci_dev *pdev,
-                                        struct velocity_info *vptr,
-                                        const struct velocity_info_tbl *info)
-{
-       memset(vptr, 0, sizeof(struct velocity_info));
-
-       vptr->pdev = pdev;
-       vptr->chip_id = info->chip_id;
-       vptr->tx.numq = info->txqueue;
-       vptr->multicast_limit = MCAM_SIZE;
-       spin_lock_init(&vptr->lock);
-}
-
-/**
- *     velocity_get_pci_info   -       retrieve PCI info for device
- *     @vptr: velocity device
- *     @pdev: PCI device it matches
- *
- *     Retrieve the PCI configuration space data that interests us from
- *     the kernel PCI layer
- */
-static int __devinit velocity_get_pci_info(struct velocity_info *vptr, struct pci_dev *pdev)
-{
-       vptr->rev_id = pdev->revision;
-
-       pci_set_master(pdev);
-
-       vptr->ioaddr = pci_resource_start(pdev, 0);
-       vptr->memaddr = pci_resource_start(pdev, 1);
-
-       if (!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
-               dev_err(&pdev->dev,
-                          "region #0 is not an I/O resource, aborting.\n");
-               return -EINVAL;
-       }
-
-       if ((pci_resource_flags(pdev, 1) & IORESOURCE_IO)) {
-               dev_err(&pdev->dev,
-                          "region #1 is an I/O resource, aborting.\n");
-               return -EINVAL;
-       }
-
-       if (pci_resource_len(pdev, 1) < VELOCITY_IO_SIZE) {
-               dev_err(&pdev->dev, "region #1 is too small.\n");
-               return -EINVAL;
-       }
-       vptr->pdev = pdev;
-
-       return 0;
-}
-
-/**
- *     velocity_print_info     -       per driver data
- *     @vptr: velocity
- *
- *     Print per driver data as the kernel driver finds Velocity
- *     hardware
- */
-static void __devinit velocity_print_info(struct velocity_info *vptr)
-{
-       struct net_device *dev = vptr->dev;
-
-       printk(KERN_INFO "%s: %s\n", dev->name, get_chip_name(vptr->chip_id));
-       printk(KERN_INFO "%s: Ethernet Address: %pM\n",
-               dev->name, dev->dev_addr);
-}
-
-static u32 velocity_get_link(struct net_device *dev)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-       return BYTE_REG_BITS_IS_ON(PHYSR0_LINKGD, &regs->PHYSR0) ? 1 : 0;
-}
-
-/**
- *     velocity_found1         -       set up discovered velocity card
- *     @pdev: PCI device
- *     @ent: PCI device table entry that matched
- *
- *     Configure a discovered adapter from scratch. Return a negative
- *     errno error code on failure paths.
- */
-static int __devinit velocity_found1(struct pci_dev *pdev, const struct pci_device_id *ent)
-{
-       static int first = 1;
-       struct net_device *dev;
-       int i;
-       const char *drv_string;
-       const struct velocity_info_tbl *info = &chip_info_table[ent->driver_data];
-       struct velocity_info *vptr;
-       struct mac_regs __iomem *regs;
-       int ret = -ENOMEM;
-
-       /* FIXME: this driver, like almost all other ethernet drivers,
-        * can support more than MAX_UNITS.
-        */
-       if (velocity_nics >= MAX_UNITS) {
-               dev_notice(&pdev->dev, "already found %d NICs.\n",
-                          velocity_nics);
-               return -ENODEV;
-       }
-
-       dev = alloc_etherdev(sizeof(struct velocity_info));
-       if (!dev) {
-               dev_err(&pdev->dev, "allocate net device failed.\n");
-               goto out;
-       }
-
-       /* Chain it all together */
-
-       SET_NETDEV_DEV(dev, &pdev->dev);
-       vptr = netdev_priv(dev);
-
-
-       if (first) {
-               printk(KERN_INFO "%s Ver. %s\n",
-                       VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
-               printk(KERN_INFO "Copyright (c) 2002, 2003 VIA Networking Technologies, Inc.\n");
-               printk(KERN_INFO "Copyright (c) 2004 Red Hat Inc.\n");
-               first = 0;
-       }
-
-       velocity_init_info(pdev, vptr, info);
-
-       vptr->dev = dev;
-
-       ret = pci_enable_device(pdev);
-       if (ret < 0)
-               goto err_free_dev;
-
-       dev->irq = pdev->irq;
-
-       ret = velocity_get_pci_info(vptr, pdev);
-       if (ret < 0) {
-               /* error message already printed */
-               goto err_disable;
-       }
-
-       ret = pci_request_regions(pdev, VELOCITY_NAME);
-       if (ret < 0) {
-               dev_err(&pdev->dev, "No PCI resources.\n");
-               goto err_disable;
-       }
-
-       regs = ioremap(vptr->memaddr, VELOCITY_IO_SIZE);
-       if (regs == NULL) {
-               ret = -EIO;
-               goto err_release_res;
-       }
-
-       vptr->mac_regs = regs;
-
-       mac_wol_reset(regs);
-
-       dev->base_addr = vptr->ioaddr;
-
-       for (i = 0; i < 6; i++)
-               dev->dev_addr[i] = readb(&regs->PAR[i]);
-
-
-       drv_string = dev_driver_string(&pdev->dev);
-
-       velocity_get_options(&vptr->options, velocity_nics, drv_string);
-
-       /*
-        *      Mask out the options cannot be set to the chip
-        */
-
-       vptr->options.flags &= info->flags;
-
-       /*
-        *      Enable the chip specified capbilities
-        */
-
-       vptr->flags = vptr->options.flags | (info->flags & 0xFF000000UL);
-
-       vptr->wol_opts = vptr->options.wol_opts;
-       vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
-
-       vptr->phy_id = MII_GET_PHY_ID(vptr->mac_regs);
-
-       dev->irq = pdev->irq;
-       dev->netdev_ops = &velocity_netdev_ops;
-       dev->ethtool_ops = &velocity_ethtool_ops;
-       netif_napi_add(dev, &vptr->napi, velocity_poll, VELOCITY_NAPI_WEIGHT);
-
-       dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HW_VLAN_TX;
-       dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER |
-               NETIF_F_HW_VLAN_RX | NETIF_F_IP_CSUM;
-
-       ret = register_netdev(dev);
-       if (ret < 0)
-               goto err_iounmap;
-
-       if (!velocity_get_link(dev)) {
-               netif_carrier_off(dev);
-               vptr->mii_status |= VELOCITY_LINK_FAIL;
-       }
-
-       velocity_print_info(vptr);
-       pci_set_drvdata(pdev, dev);
-
-       /* and leave the chip powered down */
-
-       pci_set_power_state(pdev, PCI_D3hot);
-       velocity_nics++;
-out:
-       return ret;
-
-err_iounmap:
-       iounmap(regs);
-err_release_res:
-       pci_release_regions(pdev);
-err_disable:
-       pci_disable_device(pdev);
-err_free_dev:
-       free_netdev(dev);
-       goto out;
-}
-
-#ifdef CONFIG_PM
-/**
- *     wol_calc_crc            -       WOL CRC
- *     @pattern: data pattern
- *     @mask_pattern: mask
- *
- *     Compute the wake on lan crc hashes for the packet header
- *     we are interested in.
- */
-static u16 wol_calc_crc(int size, u8 *pattern, u8 *mask_pattern)
-{
-       u16 crc = 0xFFFF;
-       u8 mask;
-       int i, j;
-
-       for (i = 0; i < size; i++) {
-               mask = mask_pattern[i];
-
-               /* Skip this loop if the mask equals to zero */
-               if (mask == 0x00)
-                       continue;
-
-               for (j = 0; j < 8; j++) {
-                       if ((mask & 0x01) == 0) {
-                               mask >>= 1;
-                               continue;
-                       }
-                       mask >>= 1;
-                       crc = crc_ccitt(crc, &(pattern[i * 8 + j]), 1);
-               }
-       }
-       /*      Finally, invert the result once to get the correct data */
-       crc = ~crc;
-       return bitrev32(crc) >> 16;
-}
-
-/**
- *     velocity_set_wol        -       set up for wake on lan
- *     @vptr: velocity to set WOL status on
- *
- *     Set a card up for wake on lan either by unicast or by
- *     ARP packet.
- *
- *     FIXME: check static buffer is safe here
- */
-static int velocity_set_wol(struct velocity_info *vptr)
-{
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-       enum speed_opt spd_dpx = vptr->options.spd_dpx;
-       static u8 buf[256];
-       int i;
-
-       static u32 mask_pattern[2][4] = {
-               {0x00203000, 0x000003C0, 0x00000000, 0x0000000}, /* ARP */
-               {0xfffff000, 0xffffffff, 0xffffffff, 0x000ffff}  /* Magic Packet */
-       };
-
-       writew(0xFFFF, &regs->WOLCRClr);
-       writeb(WOLCFG_SAB | WOLCFG_SAM, &regs->WOLCFGSet);
-       writew(WOLCR_MAGIC_EN, &regs->WOLCRSet);
-
-       /*
-          if (vptr->wol_opts & VELOCITY_WOL_PHY)
-          writew((WOLCR_LINKON_EN|WOLCR_LINKOFF_EN), &regs->WOLCRSet);
-        */
-
-       if (vptr->wol_opts & VELOCITY_WOL_UCAST)
-               writew(WOLCR_UNICAST_EN, &regs->WOLCRSet);
-
-       if (vptr->wol_opts & VELOCITY_WOL_ARP) {
-               struct arp_packet *arp = (struct arp_packet *) buf;
-               u16 crc;
-               memset(buf, 0, sizeof(struct arp_packet) + 7);
-
-               for (i = 0; i < 4; i++)
-                       writel(mask_pattern[0][i], &regs->ByteMask[0][i]);
-
-               arp->type = htons(ETH_P_ARP);
-               arp->ar_op = htons(1);
-
-               memcpy(arp->ar_tip, vptr->ip_addr, 4);
-
-               crc = wol_calc_crc((sizeof(struct arp_packet) + 7) / 8, buf,
-                               (u8 *) & mask_pattern[0][0]);
-
-               writew(crc, &regs->PatternCRC[0]);
-               writew(WOLCR_ARP_EN, &regs->WOLCRSet);
-       }
-
-       BYTE_REG_BITS_ON(PWCFG_WOLTYPE, &regs->PWCFGSet);
-       BYTE_REG_BITS_ON(PWCFG_LEGACY_WOLEN, &regs->PWCFGSet);
-
-       writew(0x0FFF, &regs->WOLSRClr);
-
-       if (spd_dpx == SPD_DPX_1000_FULL)
-               goto mac_done;
-
-       if (spd_dpx != SPD_DPX_AUTO)
-               goto advertise_done;
-
-       if (vptr->mii_status & VELOCITY_AUTONEG_ENABLE) {
-               if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
-                       MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
-
-               MII_REG_BITS_OFF(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
-       }
-
-       if (vptr->mii_status & VELOCITY_SPEED_1000)
-               MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
-
-advertise_done:
-       BYTE_REG_BITS_ON(CHIPGCR_FCMODE, &regs->CHIPGCR);
-
-       {
-               u8 GCR;
-               GCR = readb(&regs->CHIPGCR);
-               GCR = (GCR & ~CHIPGCR_FCGMII) | CHIPGCR_FCFDX;
-               writeb(GCR, &regs->CHIPGCR);
-       }
-
-mac_done:
-       BYTE_REG_BITS_OFF(ISR_PWEI, &regs->ISR);
-       /* Turn on SWPTAG just before entering power mode */
-       BYTE_REG_BITS_ON(STICKHW_SWPTAG, &regs->STICKHW);
-       /* Go to bed ..... */
-       BYTE_REG_BITS_ON((STICKHW_DS1 | STICKHW_DS0), &regs->STICKHW);
-
-       return 0;
-}
-
-/**
- *     velocity_save_context   -       save registers
- *     @vptr: velocity
- *     @context: buffer for stored context
- *
- *     Retrieve the current configuration from the velocity hardware
- *     and stash it in the context structure, for use by the context
- *     restore functions. This allows us to save things we need across
- *     power down states
- */
-static void velocity_save_context(struct velocity_info *vptr, struct velocity_context *context)
-{
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-       u16 i;
-       u8 __iomem *ptr = (u8 __iomem *)regs;
-
-       for (i = MAC_REG_PAR; i < MAC_REG_CR0_CLR; i += 4)
-               *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
-
-       for (i = MAC_REG_MAR; i < MAC_REG_TDCSR_CLR; i += 4)
-               *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
-
-       for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
-               *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
-
-}
-
-static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
-{
-       struct net_device *dev = pci_get_drvdata(pdev);
-       struct velocity_info *vptr = netdev_priv(dev);
-       unsigned long flags;
-
-       if (!netif_running(vptr->dev))
-               return 0;
-
-       netif_device_detach(vptr->dev);
-
-       spin_lock_irqsave(&vptr->lock, flags);
-       pci_save_state(pdev);
-
-       if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED) {
-               velocity_get_ip(vptr);
-               velocity_save_context(vptr, &vptr->context);
-               velocity_shutdown(vptr);
-               velocity_set_wol(vptr);
-               pci_enable_wake(pdev, PCI_D3hot, 1);
-               pci_set_power_state(pdev, PCI_D3hot);
-       } else {
-               velocity_save_context(vptr, &vptr->context);
-               velocity_shutdown(vptr);
-               pci_disable_device(pdev);
-               pci_set_power_state(pdev, pci_choose_state(pdev, state));
-       }
-
-       spin_unlock_irqrestore(&vptr->lock, flags);
-       return 0;
-}
-
-/**
- *     velocity_restore_context        -       restore registers
- *     @vptr: velocity
- *     @context: buffer for stored context
- *
- *     Reload the register configuration from the velocity context
- *     created by velocity_save_context.
- */
-static void velocity_restore_context(struct velocity_info *vptr, struct velocity_context *context)
-{
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-       int i;
-       u8 __iomem *ptr = (u8 __iomem *)regs;
-
-       for (i = MAC_REG_PAR; i < MAC_REG_CR0_SET; i += 4)
-               writel(*((u32 *) (context->mac_reg + i)), ptr + i);
-
-       /* Just skip cr0 */
-       for (i = MAC_REG_CR1_SET; i < MAC_REG_CR0_CLR; i++) {
-               /* Clear */
-               writeb(~(*((u8 *) (context->mac_reg + i))), ptr + i + 4);
-               /* Set */
-               writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
-       }
-
-       for (i = MAC_REG_MAR; i < MAC_REG_IMR; i += 4)
-               writel(*((u32 *) (context->mac_reg + i)), ptr + i);
-
-       for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
-               writel(*((u32 *) (context->mac_reg + i)), ptr + i);
-
-       for (i = MAC_REG_TDCSR_SET; i <= MAC_REG_RDCSR_SET; i++)
-               writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
-}
-
-static int velocity_resume(struct pci_dev *pdev)
-{
-       struct net_device *dev = pci_get_drvdata(pdev);
-       struct velocity_info *vptr = netdev_priv(dev);
-       unsigned long flags;
-       int i;
-
-       if (!netif_running(vptr->dev))
-               return 0;
-
-       pci_set_power_state(pdev, PCI_D0);
-       pci_enable_wake(pdev, 0, 0);
-       pci_restore_state(pdev);
-
-       mac_wol_reset(vptr->mac_regs);
-
-       spin_lock_irqsave(&vptr->lock, flags);
-       velocity_restore_context(vptr, &vptr->context);
-       velocity_init_registers(vptr, VELOCITY_INIT_WOL);
-       mac_disable_int(vptr->mac_regs);
-
-       velocity_tx_srv(vptr);
-
-       for (i = 0; i < vptr->tx.numq; i++) {
-               if (vptr->tx.used[i])
-                       mac_tx_queue_wake(vptr->mac_regs, i);
-       }
-
-       mac_enable_int(vptr->mac_regs);
-       spin_unlock_irqrestore(&vptr->lock, flags);
-       netif_device_attach(vptr->dev);
-
-       return 0;
-}
-#endif
-
-/*
- *     Definition for our device driver. The PCI layer interface
- *     uses this to handle all our card discover and plugging
- */
-static struct pci_driver velocity_driver = {
-       .name           = VELOCITY_NAME,
-       .id_table       = velocity_id_table,
-       .probe          = velocity_found1,
-       .remove         = __devexit_p(velocity_remove1),
-#ifdef CONFIG_PM
-       .suspend        = velocity_suspend,
-       .resume         = velocity_resume,
-#endif
-};
-
-
-/**
- *     velocity_ethtool_up     -       pre hook for ethtool
- *     @dev: network device
- *
- *     Called before an ethtool operation. We need to make sure the
- *     chip is out of D3 state before we poke at it.
- */
-static int velocity_ethtool_up(struct net_device *dev)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-       if (!netif_running(dev))
-               pci_set_power_state(vptr->pdev, PCI_D0);
-       return 0;
-}
-
-/**
- *     velocity_ethtool_down   -       post hook for ethtool
- *     @dev: network device
- *
- *     Called after an ethtool operation. Restore the chip back to D3
- *     state if it isn't running.
- */
-static void velocity_ethtool_down(struct net_device *dev)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-       if (!netif_running(dev))
-               pci_set_power_state(vptr->pdev, PCI_D3hot);
-}
-
-static int velocity_get_settings(struct net_device *dev,
-                                struct ethtool_cmd *cmd)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-       struct mac_regs __iomem *regs = vptr->mac_regs;
-       u32 status;
-       status = check_connection_type(vptr->mac_regs);
-
-       cmd->supported = SUPPORTED_TP |
-                       SUPPORTED_Autoneg |
-                       SUPPORTED_10baseT_Half |
-                       SUPPORTED_10baseT_Full |
-                       SUPPORTED_100baseT_Half |
-                       SUPPORTED_100baseT_Full |
-                       SUPPORTED_1000baseT_Half |
-                       SUPPORTED_1000baseT_Full;
-
-       cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
-       if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
-               cmd->advertising |=
-                       ADVERTISED_10baseT_Half |
-                       ADVERTISED_10baseT_Full |
-                       ADVERTISED_100baseT_Half |
-                       ADVERTISED_100baseT_Full |
-                       ADVERTISED_1000baseT_Half |
-                       ADVERTISED_1000baseT_Full;
-       } else {
-               switch (vptr->options.spd_dpx) {
-               case SPD_DPX_1000_FULL:
-                       cmd->advertising |= ADVERTISED_1000baseT_Full;
-                       break;
-               case SPD_DPX_100_HALF:
-                       cmd->advertising |= ADVERTISED_100baseT_Half;
-                       break;
-               case SPD_DPX_100_FULL:
-                       cmd->advertising |= ADVERTISED_100baseT_Full;
-                       break;
-               case SPD_DPX_10_HALF:
-                       cmd->advertising |= ADVERTISED_10baseT_Half;
-                       break;
-               case SPD_DPX_10_FULL:
-                       cmd->advertising |= ADVERTISED_10baseT_Full;
-                       break;
-               default:
-                       break;
-               }
-       }
-
-       if (status & VELOCITY_SPEED_1000)
-               ethtool_cmd_speed_set(cmd, SPEED_1000);
-       else if (status & VELOCITY_SPEED_100)
-               ethtool_cmd_speed_set(cmd, SPEED_100);
-       else
-               ethtool_cmd_speed_set(cmd, SPEED_10);
-
-       cmd->autoneg = (status & VELOCITY_AUTONEG_ENABLE) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
-       cmd->port = PORT_TP;
-       cmd->transceiver = XCVR_INTERNAL;
-       cmd->phy_address = readb(&regs->MIIADR) & 0x1F;
-
-       if (status & VELOCITY_DUPLEX_FULL)
-               cmd->duplex = DUPLEX_FULL;
-       else
-               cmd->duplex = DUPLEX_HALF;
-
-       return 0;
-}
-
-static int velocity_set_settings(struct net_device *dev,
-                                struct ethtool_cmd *cmd)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-       u32 speed = ethtool_cmd_speed(cmd);
-       u32 curr_status;
-       u32 new_status = 0;
-       int ret = 0;
-
-       curr_status = check_connection_type(vptr->mac_regs);
-       curr_status &= (~VELOCITY_LINK_FAIL);
-
-       new_status |= ((cmd->autoneg) ? VELOCITY_AUTONEG_ENABLE : 0);
-       new_status |= ((speed == SPEED_1000) ? VELOCITY_SPEED_1000 : 0);
-       new_status |= ((speed == SPEED_100) ? VELOCITY_SPEED_100 : 0);
-       new_status |= ((speed == SPEED_10) ? VELOCITY_SPEED_10 : 0);
-       new_status |= ((cmd->duplex == DUPLEX_FULL) ? VELOCITY_DUPLEX_FULL : 0);
-
-       if ((new_status & VELOCITY_AUTONEG_ENABLE) &&
-           (new_status != (curr_status | VELOCITY_AUTONEG_ENABLE))) {
-               ret = -EINVAL;
-       } else {
-               enum speed_opt spd_dpx;
-
-               if (new_status & VELOCITY_AUTONEG_ENABLE)
-                       spd_dpx = SPD_DPX_AUTO;
-               else if ((new_status & VELOCITY_SPEED_1000) &&
-                        (new_status & VELOCITY_DUPLEX_FULL)) {
-                       spd_dpx = SPD_DPX_1000_FULL;
-               } else if (new_status & VELOCITY_SPEED_100)
-                       spd_dpx = (new_status & VELOCITY_DUPLEX_FULL) ?
-                               SPD_DPX_100_FULL : SPD_DPX_100_HALF;
-               else if (new_status & VELOCITY_SPEED_10)
-                       spd_dpx = (new_status & VELOCITY_DUPLEX_FULL) ?
-                               SPD_DPX_10_FULL : SPD_DPX_10_HALF;
-               else
-                       return -EOPNOTSUPP;
-
-               vptr->options.spd_dpx = spd_dpx;
-
-               velocity_set_media_mode(vptr, new_status);
-       }
-
-       return ret;
-}
-
-static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-       strcpy(info->driver, VELOCITY_NAME);
-       strcpy(info->version, VELOCITY_VERSION);
-       strcpy(info->bus_info, pci_name(vptr->pdev));
-}
-
-static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-       wol->supported = WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP;
-       wol->wolopts |= WAKE_MAGIC;
-       /*
-          if (vptr->wol_opts & VELOCITY_WOL_PHY)
-                  wol.wolopts|=WAKE_PHY;
-                        */
-       if (vptr->wol_opts & VELOCITY_WOL_UCAST)
-               wol->wolopts |= WAKE_UCAST;
-       if (vptr->wol_opts & VELOCITY_WOL_ARP)
-               wol->wolopts |= WAKE_ARP;
-       memcpy(&wol->sopass, vptr->wol_passwd, 6);
-}
-
-static int velocity_ethtool_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-
-       if (!(wol->wolopts & (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP)))
-               return -EFAULT;
-       vptr->wol_opts = VELOCITY_WOL_MAGIC;
-
-       /*
-          if (wol.wolopts & WAKE_PHY) {
-          vptr->wol_opts|=VELOCITY_WOL_PHY;
-          vptr->flags |=VELOCITY_FLAGS_WOL_ENABLED;
-          }
-        */
-
-       if (wol->wolopts & WAKE_MAGIC) {
-               vptr->wol_opts |= VELOCITY_WOL_MAGIC;
-               vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
-       }
-       if (wol->wolopts & WAKE_UCAST) {
-               vptr->wol_opts |= VELOCITY_WOL_UCAST;
-               vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
-       }
-       if (wol->wolopts & WAKE_ARP) {
-               vptr->wol_opts |= VELOCITY_WOL_ARP;
-               vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
-       }
-       memcpy(vptr->wol_passwd, wol->sopass, 6);
-       return 0;
-}
-
-static u32 velocity_get_msglevel(struct net_device *dev)
-{
-       return msglevel;
-}
-
-static void velocity_set_msglevel(struct net_device *dev, u32 value)
-{
-        msglevel = value;
-}
-
-static int get_pending_timer_val(int val)
-{
-       int mult_bits = val >> 6;
-       int mult = 1;
-
-       switch (mult_bits)
-       {
-       case 1:
-               mult = 4; break;
-       case 2:
-               mult = 16; break;
-       case 3:
-               mult = 64; break;
-       case 0:
-       default:
-               break;
-       }
-
-       return (val & 0x3f) * mult;
-}
-
-static void set_pending_timer_val(int *val, u32 us)
-{
-       u8 mult = 0;
-       u8 shift = 0;
-
-       if (us >= 0x3f) {
-               mult = 1; /* mult with 4 */
-               shift = 2;
-       }
-       if (us >= 0x3f * 4) {
-               mult = 2; /* mult with 16 */
-               shift = 4;
-       }
-       if (us >= 0x3f * 16) {
-               mult = 3; /* mult with 64 */
-               shift = 6;
-       }
-
-       *val = (mult << 6) | ((us >> shift) & 0x3f);
-}
-
-
-static int velocity_get_coalesce(struct net_device *dev,
-               struct ethtool_coalesce *ecmd)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-
-       ecmd->tx_max_coalesced_frames = vptr->options.tx_intsup;
-       ecmd->rx_max_coalesced_frames = vptr->options.rx_intsup;
-
-       ecmd->rx_coalesce_usecs = get_pending_timer_val(vptr->options.rxqueue_timer);
-       ecmd->tx_coalesce_usecs = get_pending_timer_val(vptr->options.txqueue_timer);
-
-       return 0;
-}
-
-static int velocity_set_coalesce(struct net_device *dev,
-               struct ethtool_coalesce *ecmd)
-{
-       struct velocity_info *vptr = netdev_priv(dev);
-       int max_us = 0x3f * 64;
-       unsigned long flags;
-
-       /* 6 bits of  */
-       if (ecmd->tx_coalesce_usecs > max_us)
-               return -EINVAL;
-       if (ecmd->rx_coalesce_usecs > max_us)
-               return -EINVAL;
-
-       if (ecmd->tx_max_coalesced_frames > 0xff)
-               return -EINVAL;
-       if (ecmd->rx_max_coalesced_frames > 0xff)
-               return -EINVAL;
-
-       vptr->options.rx_intsup = ecmd->rx_max_coalesced_frames;
-       vptr->options.tx_intsup = ecmd->tx_max_coalesced_frames;
-
-       set_pending_timer_val(&vptr->options.rxqueue_timer,
-                       ecmd->rx_coalesce_usecs);
-       set_pending_timer_val(&vptr->options.txqueue_timer,
-                       ecmd->tx_coalesce_usecs);
-
-       /* Setup the interrupt suppression and queue timers */
-       spin_lock_irqsave(&vptr->lock, flags);
-       mac_disable_int(vptr->mac_regs);
-       setup_adaptive_interrupts(vptr);
-       setup_queue_timers(vptr);
-
-       mac_write_int_mask(vptr->int_mask, vptr->mac_regs);
-       mac_clear_isr(vptr->mac_regs);
-       mac_enable_int(vptr->mac_regs);
-       spin_unlock_irqrestore(&vptr->lock, flags);
-
-       return 0;
-}
-
-static const char velocity_gstrings[][ETH_GSTRING_LEN] = {
-       "rx_all",
-       "rx_ok",
-       "tx_ok",
-       "rx_error",
-       "rx_runt_ok",
-       "rx_runt_err",
-       "rx_64",
-       "tx_64",
-       "rx_65_to_127",
-       "tx_65_to_127",
-       "rx_128_to_255",
-       "tx_128_to_255",
-       "rx_256_to_511",
-       "tx_256_to_511",
-       "rx_512_to_1023",
-       "tx_512_to_1023",
-       "rx_1024_to_1518",
-       "tx_1024_to_1518",
-       "tx_ether_collisions",
-       "rx_crc_errors",
-       "rx_jumbo",
-       "tx_jumbo",
-       "rx_mac_control_frames",
-       "tx_mac_control_frames",
-       "rx_frame_alignement_errors",
-       "rx_long_ok",
-       "rx_long_err",
-       "tx_sqe_errors",
-       "rx_no_buf",
-       "rx_symbol_errors",
-       "in_range_length_errors",
-       "late_collisions"
-};
-
-static void velocity_get_strings(struct net_device *dev, u32 sset, u8 *data)
-{
-       switch (sset) {
-       case ETH_SS_STATS:
-               memcpy(data, *velocity_gstrings, sizeof(velocity_gstrings));
-               break;
-       }
-}
-
-static int velocity_get_sset_count(struct net_device *dev, int sset)
-{
-       switch (sset) {
-       case ETH_SS_STATS:
-               return ARRAY_SIZE(velocity_gstrings);
-       default:
-               return -EOPNOTSUPP;
-       }
-}
-
-static void velocity_get_ethtool_stats(struct net_device *dev,
-                                      struct ethtool_stats *stats, u64 *data)
-{
-       if (netif_running(dev)) {
-               struct velocity_info *vptr = netdev_priv(dev);
-               u32 *p = vptr->mib_counter;
-               int i;
-
-               spin_lock_irq(&vptr->lock);
-               velocity_update_hw_mibs(vptr);
-               spin_unlock_irq(&vptr->lock);
-
-               for (i = 0; i < ARRAY_SIZE(velocity_gstrings); i++)
-                       *data++ = *p++;
-       }
-}
-
-static const struct ethtool_ops velocity_ethtool_ops = {
-       .get_settings           = velocity_get_settings,
-       .set_settings           = velocity_set_settings,
-       .get_drvinfo            = velocity_get_drvinfo,
-       .get_wol                = velocity_ethtool_get_wol,
-       .set_wol                = velocity_ethtool_set_wol,
-       .get_msglevel           = velocity_get_msglevel,
-       .set_msglevel           = velocity_set_msglevel,
-       .get_link               = velocity_get_link,
-       .get_strings            = velocity_get_strings,
-       .get_sset_count         = velocity_get_sset_count,
-       .get_ethtool_stats      = velocity_get_ethtool_stats,
-       .get_coalesce           = velocity_get_coalesce,
-       .set_coalesce           = velocity_set_coalesce,
-       .begin                  = velocity_ethtool_up,
-       .complete               = velocity_ethtool_down
-};
-
-#if defined(CONFIG_PM) && defined(CONFIG_INET)
-static int velocity_netdev_event(struct notifier_block *nb, unsigned long notification, void *ptr)
-{
-       struct in_ifaddr *ifa = ptr;
-       struct net_device *dev = ifa->ifa_dev->dev;
-
-       if (dev_net(dev) == &init_net &&
-           dev->netdev_ops == &velocity_netdev_ops)
-               velocity_get_ip(netdev_priv(dev));
-
-       return NOTIFY_DONE;
-}
-
-static struct notifier_block velocity_inetaddr_notifier = {
-       .notifier_call  = velocity_netdev_event,
-};
-
-static void velocity_register_notifier(void)
-{
-       register_inetaddr_notifier(&velocity_inetaddr_notifier);
-}
-
-static void velocity_unregister_notifier(void)
-{
-       unregister_inetaddr_notifier(&velocity_inetaddr_notifier);
-}
-
-#else
-
-#define velocity_register_notifier()   do {} while (0)
-#define velocity_unregister_notifier() do {} while (0)
-
-#endif /* defined(CONFIG_PM) && defined(CONFIG_INET) */
-
-/**
- *     velocity_init_module    -       load time function
- *
- *     Called when the velocity module is loaded. The PCI driver
- *     is registered with the PCI layer, and in turn will call
- *     the probe functions for each velocity adapter installed
- *     in the system.
- */
-static int __init velocity_init_module(void)
-{
-       int ret;
-
-       velocity_register_notifier();
-       ret = pci_register_driver(&velocity_driver);
-       if (ret < 0)
-               velocity_unregister_notifier();
-       return ret;
-}
-
-/**
- *     velocity_cleanup        -       module unload
- *
- *     When the velocity hardware is unloaded this function is called.
- *     It will clean up the notifiers and the unregister the PCI
- *     driver interface for this hardware. This in turn cleans up
- *     all discovered interfaces before returning from the function
- */
-static void __exit velocity_cleanup_module(void)
-{
-       velocity_unregister_notifier();
-       pci_unregister_driver(&velocity_driver);
-}
-
-module_init(velocity_init_module);
-module_exit(velocity_cleanup_module);
diff --git a/drivers/net/via-velocity.h b/drivers/net/via-velocity.h
deleted file mode 100644 (file)
index 4cb9f13..0000000
+++ /dev/null
@@ -1,1579 +0,0 @@
-/*
- * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
- * All rights reserved.
- *
- * This software may be redistributed and/or modified under
- * the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * File: via-velocity.h
- *
- * Purpose: Header file to define driver's private structures.
- *
- * Author: Chuang Liang-Shing, AJ Jiang
- *
- * Date: Jan 24, 2003
- */
-
-
-#ifndef VELOCITY_H
-#define VELOCITY_H
-
-#define VELOCITY_TX_CSUM_SUPPORT
-
-#define VELOCITY_NAME          "via-velocity"
-#define VELOCITY_FULL_DRV_NAM  "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver"
-#define VELOCITY_VERSION       "1.15"
-
-#define VELOCITY_IO_SIZE       256
-#define VELOCITY_NAPI_WEIGHT   64
-
-#define PKT_BUF_SZ          1540
-
-#define MAX_UNITS           8
-#define OPTION_DEFAULT      { [0 ... MAX_UNITS-1] = -1}
-
-#define REV_ID_VT6110       (0)
-
-#define BYTE_REG_BITS_ON(x,p)       do { writeb(readb((p))|(x),(p));} while (0)
-#define WORD_REG_BITS_ON(x,p)       do { writew(readw((p))|(x),(p));} while (0)
-#define DWORD_REG_BITS_ON(x,p)      do { writel(readl((p))|(x),(p));} while (0)
-
-#define BYTE_REG_BITS_IS_ON(x,p)    (readb((p)) & (x))
-#define WORD_REG_BITS_IS_ON(x,p)    (readw((p)) & (x))
-#define DWORD_REG_BITS_IS_ON(x,p)   (readl((p)) & (x))
-
-#define BYTE_REG_BITS_OFF(x,p)      do { writeb(readb((p)) & (~(x)),(p));} while (0)
-#define WORD_REG_BITS_OFF(x,p)      do { writew(readw((p)) & (~(x)),(p));} while (0)
-#define DWORD_REG_BITS_OFF(x,p)     do { writel(readl((p)) & (~(x)),(p));} while (0)
-
-#define BYTE_REG_BITS_SET(x,m,p)    do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
-#define WORD_REG_BITS_SET(x,m,p)    do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
-#define DWORD_REG_BITS_SET(x,m,p)   do { writel( (readl((p)) & (~(m)))|(x),(p));}  while (0)
-
-#define VAR_USED(p)     do {(p)=(p);} while (0)
-
-/*
- * Purpose: Structures for MAX RX/TX descriptors.
- */
-
-
-#define B_OWNED_BY_CHIP     1
-#define B_OWNED_BY_HOST     0
-
-/*
- * Bits in the RSR0 register
- */
-
-#define RSR_DETAG      cpu_to_le16(0x0080)
-#define RSR_SNTAG      cpu_to_le16(0x0040)
-#define RSR_RXER       cpu_to_le16(0x0020)
-#define RSR_RL         cpu_to_le16(0x0010)
-#define RSR_CE         cpu_to_le16(0x0008)
-#define RSR_FAE                cpu_to_le16(0x0004)
-#define RSR_CRC                cpu_to_le16(0x0002)
-#define RSR_VIDM       cpu_to_le16(0x0001)
-
-/*
- * Bits in the RSR1 register
- */
-
-#define RSR_RXOK       cpu_to_le16(0x8000) // rx OK
-#define RSR_PFT                cpu_to_le16(0x4000) // Perfect filtering address match
-#define RSR_MAR                cpu_to_le16(0x2000) // MAC accept multicast address packet
-#define RSR_BAR                cpu_to_le16(0x1000) // MAC accept broadcast address packet
-#define RSR_PHY                cpu_to_le16(0x0800) // MAC accept physical address packet
-#define RSR_VTAG       cpu_to_le16(0x0400) // 802.1p/1q tagging packet indicator
-#define RSR_STP                cpu_to_le16(0x0200) // start of packet
-#define RSR_EDP                cpu_to_le16(0x0100) // end of packet
-
-/*
- * Bits in the CSM register
- */
-
-#define CSM_IPOK            0x40       //IP Checksum validation ok
-#define CSM_TUPOK           0x20       //TCP/UDP Checksum validation ok
-#define CSM_FRAG            0x10       //Fragment IP datagram
-#define CSM_IPKT            0x04       //Received an IP packet
-#define CSM_TCPKT           0x02       //Received a TCP packet
-#define CSM_UDPKT           0x01       //Received a UDP packet
-
-/*
- * Bits in the TSR0 register
- */
-
-#define TSR0_ABT       cpu_to_le16(0x0080) // Tx abort because of excessive collision
-#define TSR0_OWT       cpu_to_le16(0x0040) // Jumbo frame Tx abort
-#define TSR0_OWC       cpu_to_le16(0x0020) // Out of window collision
-#define TSR0_COLS      cpu_to_le16(0x0010) // experience collision in this transmit event
-#define TSR0_NCR3      cpu_to_le16(0x0008) // collision retry counter[3]
-#define TSR0_NCR2      cpu_to_le16(0x0004) // collision retry counter[2]
-#define TSR0_NCR1      cpu_to_le16(0x0002) // collision retry counter[1]
-#define TSR0_NCR0      cpu_to_le16(0x0001) // collision retry counter[0]
-#define TSR0_TERR      cpu_to_le16(0x8000) //
-#define TSR0_FDX       cpu_to_le16(0x4000) // current transaction is serviced by full duplex mode
-#define TSR0_GMII      cpu_to_le16(0x2000) // current transaction is serviced by GMII mode
-#define TSR0_LNKFL     cpu_to_le16(0x1000) // packet serviced during link down
-#define TSR0_SHDN      cpu_to_le16(0x0400) // shutdown case
-#define TSR0_CRS       cpu_to_le16(0x0200) // carrier sense lost
-#define TSR0_CDH       cpu_to_le16(0x0100) // AQE test fail (CD heartbeat)
-
-//
-// Bits in the TCR0 register
-//
-#define TCR0_TIC            0x80       // assert interrupt immediately while descriptor has been send complete
-#define TCR0_PIC            0x40       // priority interrupt request, INA# is issued over adaptive interrupt scheme
-#define TCR0_VETAG          0x20       // enable VLAN tag
-#define TCR0_IPCK           0x10       // request IP  checksum calculation.
-#define TCR0_UDPCK          0x08       // request UDP checksum calculation.
-#define TCR0_TCPCK          0x04       // request TCP checksum calculation.
-#define TCR0_JMBO           0x02       // indicate a jumbo packet in GMAC side
-#define TCR0_CRC            0x01       // disable CRC generation
-
-#define TCPLS_NORMAL        3
-#define TCPLS_START         2
-#define TCPLS_END           1
-#define TCPLS_MED           0
-
-
-// max transmit or receive buffer size
-#define CB_RX_BUF_SIZE     2048UL      // max buffer size
-                                       // NOTE: must be multiple of 4
-
-#define CB_MAX_RD_NUM       512        // MAX # of RD
-#define CB_MAX_TD_NUM       256        // MAX # of TD
-
-#define CB_INIT_RD_NUM_3119 128        // init # of RD, for setup VT3119
-#define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119
-
-#define CB_INIT_RD_NUM      128        // init # of RD, for setup default
-#define CB_INIT_TD_NUM      64 // init # of TD, for setup default
-
-// for 3119
-#define CB_TD_RING_NUM      4  // # of TD rings.
-#define CB_MAX_SEG_PER_PKT  7  // max data seg per packet (Tx)
-
-
-/*
- *     If collisions excess 15 times , tx will abort, and
- *     if tx fifo underflow, tx will fail
- *     we should try to resend it
- */
-
-#define CB_MAX_TX_ABORT_RETRY   3
-
-/*
- *     Receive descriptor
- */
-
-struct rdesc0 {
-       __le16 RSR;             /* Receive status */
-       __le16 len;             /* bits 0--13; bit 15 - owner */
-};
-
-struct rdesc1 {
-       __le16 PQTAG;
-       u8 CSM;
-       u8 IPKT;
-};
-
-enum {
-       RX_INTEN = cpu_to_le16(0x8000)
-};
-
-struct rx_desc {
-       struct rdesc0 rdesc0;
-       struct rdesc1 rdesc1;
-       __le32 pa_low;          /* Low 32 bit PCI address */
-       __le16 pa_high;         /* Next 16 bit PCI address (48 total) */
-       __le16 size;            /* bits 0--14 - frame size, bit 15 - enable int. */
-} __packed;
-
-/*
- *     Transmit descriptor
- */
-
-struct tdesc0 {
-       __le16 TSR;             /* Transmit status register */
-       __le16 len;             /* bits 0--13 - size of frame, bit 15 - owner */
-};
-
-struct tdesc1 {
-       __le16 vlan;
-       u8 TCR;
-       u8 cmd;                 /* bits 0--1 - TCPLS, bits 4--7 - CMDZ */
-} __packed;
-
-enum {
-       TD_QUEUE = cpu_to_le16(0x8000)
-};
-
-struct td_buf {
-       __le32 pa_low;
-       __le16 pa_high;
-       __le16 size;            /* bits 0--13 - size, bit 15 - queue */
-} __packed;
-
-struct tx_desc {
-       struct tdesc0 tdesc0;
-       struct tdesc1 tdesc1;
-       struct td_buf td_buf[7];
-};
-
-struct velocity_rd_info {
-       struct sk_buff *skb;
-       dma_addr_t skb_dma;
-};
-
-/*
- *     Used to track transmit side buffers.
- */
-
-struct velocity_td_info {
-       struct sk_buff *skb;
-       int nskb_dma;
-       dma_addr_t skb_dma[7];
-};
-
-enum  velocity_owner {
-       OWNED_BY_HOST = 0,
-       OWNED_BY_NIC = cpu_to_le16(0x8000)
-};
-
-
-/*
- *     MAC registers and macros.
- */
-
-
-#define MCAM_SIZE           64
-#define VCAM_SIZE           64
-#define TX_QUEUE_NO         4
-
-#define MAX_HW_MIB_COUNTER  32
-#define VELOCITY_MIN_MTU    (64)
-#define VELOCITY_MAX_MTU    (9000)
-
-/*
- *     Registers in the MAC
- */
-
-#define MAC_REG_PAR         0x00       // physical address
-#define MAC_REG_RCR         0x06
-#define MAC_REG_TCR         0x07
-#define MAC_REG_CR0_SET     0x08
-#define MAC_REG_CR1_SET     0x09
-#define MAC_REG_CR2_SET     0x0A
-#define MAC_REG_CR3_SET     0x0B
-#define MAC_REG_CR0_CLR     0x0C
-#define MAC_REG_CR1_CLR     0x0D
-#define MAC_REG_CR2_CLR     0x0E
-#define MAC_REG_CR3_CLR     0x0F
-#define MAC_REG_MAR         0x10
-#define MAC_REG_CAM         0x10
-#define MAC_REG_DEC_BASE_HI 0x18
-#define MAC_REG_DBF_BASE_HI 0x1C
-#define MAC_REG_ISR_CTL     0x20
-#define MAC_REG_ISR_HOTMR   0x20
-#define MAC_REG_ISR_TSUPTHR 0x20
-#define MAC_REG_ISR_RSUPTHR 0x20
-#define MAC_REG_ISR_CTL1    0x21
-#define MAC_REG_TXE_SR      0x22
-#define MAC_REG_RXE_SR      0x23
-#define MAC_REG_ISR         0x24
-#define MAC_REG_ISR0        0x24
-#define MAC_REG_ISR1        0x25
-#define MAC_REG_ISR2        0x26
-#define MAC_REG_ISR3        0x27
-#define MAC_REG_IMR         0x28
-#define MAC_REG_IMR0        0x28
-#define MAC_REG_IMR1        0x29
-#define MAC_REG_IMR2        0x2A
-#define MAC_REG_IMR3        0x2B
-#define MAC_REG_TDCSR_SET   0x30
-#define MAC_REG_RDCSR_SET   0x32
-#define MAC_REG_TDCSR_CLR   0x34
-#define MAC_REG_RDCSR_CLR   0x36
-#define MAC_REG_RDBASE_LO   0x38
-#define MAC_REG_RDINDX      0x3C
-#define MAC_REG_TDBASE_LO   0x40
-#define MAC_REG_RDCSIZE     0x50
-#define MAC_REG_TDCSIZE     0x52
-#define MAC_REG_TDINDX      0x54
-#define MAC_REG_TDIDX0      0x54
-#define MAC_REG_TDIDX1      0x56
-#define MAC_REG_TDIDX2      0x58
-#define MAC_REG_TDIDX3      0x5A
-#define MAC_REG_PAUSE_TIMER 0x5C
-#define MAC_REG_RBRDU       0x5E
-#define MAC_REG_FIFO_TEST0  0x60
-#define MAC_REG_FIFO_TEST1  0x64
-#define MAC_REG_CAMADDR     0x68
-#define MAC_REG_CAMCR       0x69
-#define MAC_REG_GFTEST      0x6A
-#define MAC_REG_FTSTCMD     0x6B
-#define MAC_REG_MIICFG      0x6C
-#define MAC_REG_MIISR       0x6D
-#define MAC_REG_PHYSR0      0x6E
-#define MAC_REG_PHYSR1      0x6F
-#define MAC_REG_MIICR       0x70
-#define MAC_REG_MIIADR      0x71
-#define MAC_REG_MIIDATA     0x72
-#define MAC_REG_SOFT_TIMER0 0x74
-#define MAC_REG_SOFT_TIMER1 0x76
-#define MAC_REG_CFGA        0x78
-#define MAC_REG_CFGB        0x79
-#define MAC_REG_CFGC        0x7A
-#define MAC_REG_CFGD        0x7B
-#define MAC_REG_DCFG0       0x7C
-#define MAC_REG_DCFG1       0x7D
-#define MAC_REG_MCFG0       0x7E
-#define MAC_REG_MCFG1       0x7F
-
-#define MAC_REG_TBIST       0x80
-#define MAC_REG_RBIST       0x81
-#define MAC_REG_PMCC        0x82
-#define MAC_REG_STICKHW     0x83
-#define MAC_REG_MIBCR       0x84
-#define MAC_REG_EERSV       0x85
-#define MAC_REG_REVID       0x86
-#define MAC_REG_MIBREAD     0x88
-#define MAC_REG_BPMA        0x8C
-#define MAC_REG_EEWR_DATA   0x8C
-#define MAC_REG_BPMD_WR     0x8F
-#define MAC_REG_BPCMD       0x90
-#define MAC_REG_BPMD_RD     0x91
-#define MAC_REG_EECHKSUM    0x92
-#define MAC_REG_EECSR       0x93
-#define MAC_REG_EERD_DATA   0x94
-#define MAC_REG_EADDR       0x96
-#define MAC_REG_EMBCMD      0x97
-#define MAC_REG_JMPSR0      0x98
-#define MAC_REG_JMPSR1      0x99
-#define MAC_REG_JMPSR2      0x9A
-#define MAC_REG_JMPSR3      0x9B
-#define MAC_REG_CHIPGSR     0x9C
-#define MAC_REG_TESTCFG     0x9D
-#define MAC_REG_DEBUG       0x9E
-#define MAC_REG_CHIPGCR     0x9F       /* Chip Operation and Diagnostic Control */
-#define MAC_REG_WOLCR0_SET  0xA0
-#define MAC_REG_WOLCR1_SET  0xA1
-#define MAC_REG_PWCFG_SET   0xA2
-#define MAC_REG_WOLCFG_SET  0xA3
-#define MAC_REG_WOLCR0_CLR  0xA4
-#define MAC_REG_WOLCR1_CLR  0xA5
-#define MAC_REG_PWCFG_CLR   0xA6
-#define MAC_REG_WOLCFG_CLR  0xA7
-#define MAC_REG_WOLSR0_SET  0xA8
-#define MAC_REG_WOLSR1_SET  0xA9
-#define MAC_REG_WOLSR0_CLR  0xAC
-#define MAC_REG_WOLSR1_CLR  0xAD
-#define MAC_REG_PATRN_CRC0  0xB0
-#define MAC_REG_PATRN_CRC1  0xB2
-#define MAC_REG_PATRN_CRC2  0xB4
-#define MAC_REG_PATRN_CRC3  0xB6
-#define MAC_REG_PATRN_CRC4  0xB8
-#define MAC_REG_PATRN_CRC5  0xBA
-#define MAC_REG_PATRN_CRC6  0xBC
-#define MAC_REG_PATRN_CRC7  0xBE
-#define MAC_REG_BYTEMSK0_0  0xC0
-#define MAC_REG_BYTEMSK0_1  0xC4
-#define MAC_REG_BYTEMSK0_2  0xC8
-#define MAC_REG_BYTEMSK0_3  0xCC
-#define MAC_REG_BYTEMSK1_0  0xD0
-#define MAC_REG_BYTEMSK1_1  0xD4
-#define MAC_REG_BYTEMSK1_2  0xD8
-#define MAC_REG_BYTEMSK1_3  0xDC
-#define MAC_REG_BYTEMSK2_0  0xE0
-#define MAC_REG_BYTEMSK2_1  0xE4
-#define MAC_REG_BYTEMSK2_2  0xE8
-#define MAC_REG_BYTEMSK2_3  0xEC
-#define MAC_REG_BYTEMSK3_0  0xF0
-#define MAC_REG_BYTEMSK3_1  0xF4
-#define MAC_REG_BYTEMSK3_2  0xF8
-#define MAC_REG_BYTEMSK3_3  0xFC
-
-/*
- *     Bits in the RCR register
- */
-
-#define RCR_AS              0x80
-#define RCR_AP              0x40
-#define RCR_AL              0x20
-#define RCR_PROM            0x10
-#define RCR_AB              0x08
-#define RCR_AM              0x04
-#define RCR_AR              0x02
-#define RCR_SEP             0x01
-
-/*
- *     Bits in the TCR register
- */
-
-#define TCR_TB2BDIS         0x80
-#define TCR_COLTMC1         0x08
-#define TCR_COLTMC0         0x04
-#define TCR_LB1             0x02       /* loopback[1] */
-#define TCR_LB0             0x01       /* loopback[0] */
-
-/*
- *     Bits in the CR0 register
- */
-
-#define CR0_TXON            0x00000008UL
-#define CR0_RXON            0x00000004UL
-#define CR0_STOP            0x00000002UL       /* stop MAC, default = 1 */
-#define CR0_STRT            0x00000001UL       /* start MAC */
-#define CR0_SFRST           0x00008000UL       /* software reset */
-#define CR0_TM1EN           0x00004000UL
-#define CR0_TM0EN           0x00002000UL
-#define CR0_DPOLL           0x00000800UL       /* disable rx/tx auto polling */
-#define CR0_DISAU           0x00000100UL
-#define CR0_XONEN           0x00800000UL
-#define CR0_FDXTFCEN        0x00400000UL       /* full-duplex TX flow control enable */
-#define CR0_FDXRFCEN        0x00200000UL       /* full-duplex RX flow control enable */
-#define CR0_HDXFCEN         0x00100000UL       /* half-duplex flow control enable */
-#define CR0_XHITH1          0x00080000UL       /* TX XON high threshold 1 */
-#define CR0_XHITH0          0x00040000UL       /* TX XON high threshold 0 */
-#define CR0_XLTH1           0x00020000UL       /* TX pause frame low threshold 1 */
-#define CR0_XLTH0           0x00010000UL       /* TX pause frame low threshold 0 */
-#define CR0_GSPRST          0x80000000UL
-#define CR0_FORSRST         0x40000000UL
-#define CR0_FPHYRST         0x20000000UL
-#define CR0_DIAG            0x10000000UL
-#define CR0_INTPCTL         0x04000000UL
-#define CR0_GINTMSK1        0x02000000UL
-#define CR0_GINTMSK0        0x01000000UL
-
-/*
- *     Bits in the CR1 register
- */
-
-#define CR1_SFRST           0x80       /* software reset */
-#define CR1_TM1EN           0x40
-#define CR1_TM0EN           0x20
-#define CR1_DPOLL           0x08       /* disable rx/tx auto polling */
-#define CR1_DISAU           0x01
-
-/*
- *     Bits in the CR2 register
- */
-
-#define CR2_XONEN           0x80
-#define CR2_FDXTFCEN        0x40       /* full-duplex TX flow control enable */
-#define CR2_FDXRFCEN        0x20       /* full-duplex RX flow control enable */
-#define CR2_HDXFCEN         0x10       /* half-duplex flow control enable */
-#define CR2_XHITH1          0x08       /* TX XON high threshold 1 */
-#define CR2_XHITH0          0x04       /* TX XON high threshold 0 */
-#define CR2_XLTH1           0x02       /* TX pause frame low threshold 1 */
-#define CR2_XLTH0           0x01       /* TX pause frame low threshold 0 */
-
-/*
- *     Bits in the CR3 register
- */
-
-#define CR3_GSPRST          0x80
-#define CR3_FORSRST         0x40
-#define CR3_FPHYRST         0x20
-#define CR3_DIAG            0x10
-#define CR3_INTPCTL         0x04
-#define CR3_GINTMSK1        0x02
-#define CR3_GINTMSK0        0x01
-
-#define ISRCTL_UDPINT       0x8000
-#define ISRCTL_TSUPDIS      0x4000
-#define ISRCTL_RSUPDIS      0x2000
-#define ISRCTL_PMSK1        0x1000
-#define ISRCTL_PMSK0        0x0800
-#define ISRCTL_INTPD        0x0400
-#define ISRCTL_HCRLD        0x0200
-#define ISRCTL_SCRLD        0x0100
-
-/*
- *     Bits in the ISR_CTL1 register
- */
-
-#define ISRCTL1_UDPINT      0x80
-#define ISRCTL1_TSUPDIS     0x40
-#define ISRCTL1_RSUPDIS     0x20
-#define ISRCTL1_PMSK1       0x10
-#define ISRCTL1_PMSK0       0x08
-#define ISRCTL1_INTPD       0x04
-#define ISRCTL1_HCRLD       0x02
-#define ISRCTL1_SCRLD       0x01
-
-/*
- *     Bits in the TXE_SR register
- */
-
-#define TXESR_TFDBS         0x08
-#define TXESR_TDWBS         0x04
-#define TXESR_TDRBS         0x02
-#define TXESR_TDSTR         0x01
-
-/*
- *     Bits in the RXE_SR register
- */
-
-#define RXESR_RFDBS         0x08
-#define RXESR_RDWBS         0x04
-#define RXESR_RDRBS         0x02
-#define RXESR_RDSTR         0x01
-
-/*
- *     Bits in the ISR register
- */
-
-#define ISR_ISR3            0x80000000UL
-#define ISR_ISR2            0x40000000UL
-#define ISR_ISR1            0x20000000UL
-#define ISR_ISR0            0x10000000UL
-#define ISR_TXSTLI          0x02000000UL
-#define ISR_RXSTLI          0x01000000UL
-#define ISR_HFLD            0x00800000UL
-#define ISR_UDPI            0x00400000UL
-#define ISR_MIBFI           0x00200000UL
-#define ISR_SHDNI           0x00100000UL
-#define ISR_PHYI            0x00080000UL
-#define ISR_PWEI            0x00040000UL
-#define ISR_TMR1I           0x00020000UL
-#define ISR_TMR0I           0x00010000UL
-#define ISR_SRCI            0x00008000UL
-#define ISR_LSTPEI          0x00004000UL
-#define ISR_LSTEI           0x00002000UL
-#define ISR_OVFI            0x00001000UL
-#define ISR_FLONI           0x00000800UL
-#define ISR_RACEI           0x00000400UL
-#define ISR_TXWB1I          0x00000200UL
-#define ISR_TXWB0I          0x00000100UL
-#define ISR_PTX3I           0x00000080UL
-#define ISR_PTX2I           0x00000040UL
-#define ISR_PTX1I           0x00000020UL
-#define ISR_PTX0I           0x00000010UL
-#define ISR_PTXI            0x00000008UL
-#define ISR_PRXI            0x00000004UL
-#define ISR_PPTXI           0x00000002UL
-#define ISR_PPRXI           0x00000001UL
-
-/*
- *     Bits in the IMR register
- */
-
-#define IMR_TXSTLM          0x02000000UL
-#define IMR_UDPIM           0x00400000UL
-#define IMR_MIBFIM          0x00200000UL
-#define IMR_SHDNIM          0x00100000UL
-#define IMR_PHYIM           0x00080000UL
-#define IMR_PWEIM           0x00040000UL
-#define IMR_TMR1IM          0x00020000UL
-#define IMR_TMR0IM          0x00010000UL
-
-#define IMR_SRCIM           0x00008000UL
-#define IMR_LSTPEIM         0x00004000UL
-#define IMR_LSTEIM          0x00002000UL
-#define IMR_OVFIM           0x00001000UL
-#define IMR_FLONIM          0x00000800UL
-#define IMR_RACEIM          0x00000400UL
-#define IMR_TXWB1IM         0x00000200UL
-#define IMR_TXWB0IM         0x00000100UL
-
-#define IMR_PTX3IM          0x00000080UL
-#define IMR_PTX2IM          0x00000040UL
-#define IMR_PTX1IM          0x00000020UL
-#define IMR_PTX0IM          0x00000010UL
-#define IMR_PTXIM           0x00000008UL
-#define IMR_PRXIM           0x00000004UL
-#define IMR_PPTXIM          0x00000002UL
-#define IMR_PPRXIM          0x00000001UL
-
-/* 0x0013FB0FUL  =  initial value of IMR */
-
-#define INT_MASK_DEF        (IMR_PPTXIM|IMR_PPRXIM|IMR_PTXIM|IMR_PRXIM|\
-                            IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM|\
-                            IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\
-                            IMR_SHDNIM|IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM)
-
-/*
- *     Bits in the TDCSR0/1, RDCSR0 register
- */
-
-#define TRDCSR_DEAD         0x0008
-#define TRDCSR_WAK          0x0004
-#define TRDCSR_ACT          0x0002
-#define TRDCSR_RUN         0x0001
-
-/*
- *     Bits in the CAMADDR register
- */
-
-#define CAMADDR_CAMEN       0x80
-#define CAMADDR_VCAMSL      0x40
-
-/*
- *     Bits in the CAMCR register
- */
-
-#define CAMCR_PS1           0x80
-#define CAMCR_PS0           0x40
-#define CAMCR_AITRPKT       0x20
-#define CAMCR_AITR16        0x10
-#define CAMCR_CAMRD         0x08
-#define CAMCR_CAMWR         0x04
-#define CAMCR_PS_CAM_MASK   0x40
-#define CAMCR_PS_CAM_DATA   0x80
-#define CAMCR_PS_MAR        0x00
-
-/*
- *     Bits in the MIICFG register
- */
-
-#define MIICFG_MPO1         0x80
-#define MIICFG_MPO0         0x40
-#define MIICFG_MFDC         0x20
-
-/*
- *     Bits in the MIISR register
- */
-
-#define MIISR_MIDLE         0x80
-
-/*
- *      Bits in the PHYSR0 register
- */
-
-#define PHYSR0_PHYRST       0x80
-#define PHYSR0_LINKGD       0x40
-#define PHYSR0_FDPX         0x10
-#define PHYSR0_SPDG         0x08
-#define PHYSR0_SPD10        0x04
-#define PHYSR0_RXFLC        0x02
-#define PHYSR0_TXFLC        0x01
-
-/*
- *     Bits in the PHYSR1 register
- */
-
-#define PHYSR1_PHYTBI       0x01
-
-/*
- *     Bits in the MIICR register
- */
-
-#define MIICR_MAUTO         0x80
-#define MIICR_RCMD          0x40
-#define MIICR_WCMD          0x20
-#define MIICR_MDPM          0x10
-#define MIICR_MOUT          0x08
-#define MIICR_MDO           0x04
-#define MIICR_MDI           0x02
-#define MIICR_MDC           0x01
-
-/*
- *     Bits in the MIIADR register
- */
-
-#define MIIADR_SWMPL        0x80
-
-/*
- *     Bits in the CFGA register
- */
-
-#define CFGA_PMHCTG         0x08
-#define CFGA_GPIO1PD        0x04
-#define CFGA_ABSHDN         0x02
-#define CFGA_PACPI          0x01
-
-/*
- *     Bits in the CFGB register
- */
-
-#define CFGB_GTCKOPT        0x80
-#define CFGB_MIIOPT         0x40
-#define CFGB_CRSEOPT        0x20
-#define CFGB_OFSET          0x10
-#define CFGB_CRANDOM        0x08
-#define CFGB_CAP            0x04
-#define CFGB_MBA            0x02
-#define CFGB_BAKOPT         0x01
-
-/*
- *     Bits in the CFGC register
- */
-
-#define CFGC_EELOAD         0x80
-#define CFGC_BROPT          0x40
-#define CFGC_DLYEN          0x20
-#define CFGC_DTSEL          0x10
-#define CFGC_BTSEL          0x08
-#define CFGC_BPS2           0x04       /* bootrom select[2] */
-#define CFGC_BPS1           0x02       /* bootrom select[1] */
-#define CFGC_BPS0           0x01       /* bootrom select[0] */
-
-/*
- * Bits in the CFGD register
- */
-
-#define CFGD_IODIS          0x80
-#define CFGD_MSLVDACEN      0x40
-#define CFGD_CFGDACEN       0x20
-#define CFGD_PCI64EN        0x10
-#define CFGD_HTMRL4         0x08
-
-/*
- *     Bits in the DCFG1 register
- */
-
-#define DCFG_XMWI           0x8000
-#define DCFG_XMRM           0x4000
-#define DCFG_XMRL           0x2000
-#define DCFG_PERDIS         0x1000
-#define DCFG_MRWAIT         0x0400
-#define DCFG_MWWAIT         0x0200
-#define DCFG_LATMEN         0x0100
-
-/*
- *     Bits in the MCFG0 register
- */
-
-#define MCFG_RXARB          0x0080
-#define MCFG_RFT1           0x0020
-#define MCFG_RFT0           0x0010
-#define MCFG_LOWTHOPT       0x0008
-#define MCFG_PQEN           0x0004
-#define MCFG_RTGOPT         0x0002
-#define MCFG_VIDFR          0x0001
-
-/*
- *     Bits in the MCFG1 register
- */
-
-#define MCFG_TXARB          0x8000
-#define MCFG_TXQBK1         0x0800
-#define MCFG_TXQBK0         0x0400
-#define MCFG_TXQNOBK        0x0200
-#define MCFG_SNAPOPT        0x0100
-
-/*
- *     Bits in the PMCC  register
- */
-
-#define PMCC_DSI            0x80
-#define PMCC_D2_DIS         0x40
-#define PMCC_D1_DIS         0x20
-#define PMCC_D3C_EN         0x10
-#define PMCC_D3H_EN         0x08
-#define PMCC_D2_EN          0x04
-#define PMCC_D1_EN          0x02
-#define PMCC_D0_EN          0x01
-
-/*
- *     Bits in STICKHW
- */
-
-#define STICKHW_SWPTAG      0x10
-#define STICKHW_WOLSR       0x08
-#define STICKHW_WOLEN       0x04
-#define STICKHW_DS1         0x02       /* R/W by software/cfg cycle */
-#define STICKHW_DS0         0x01       /* suspend well DS write port */
-
-/*
- *     Bits in the MIBCR register
- */
-
-#define MIBCR_MIBISTOK      0x80
-#define MIBCR_MIBISTGO      0x40
-#define MIBCR_MIBINC        0x20
-#define MIBCR_MIBHI         0x10
-#define MIBCR_MIBFRZ        0x08
-#define MIBCR_MIBFLSH       0x04
-#define MIBCR_MPTRINI       0x02
-#define MIBCR_MIBCLR        0x01
-
-/*
- *     Bits in the EERSV register
- */
-
-#define EERSV_BOOT_RPL      ((u8) 0x01)         /* Boot method selection for VT6110 */
-
-#define EERSV_BOOT_MASK     ((u8) 0x06)
-#define EERSV_BOOT_INT19    ((u8) 0x00)
-#define EERSV_BOOT_INT18    ((u8) 0x02)
-#define EERSV_BOOT_LOCAL    ((u8) 0x04)
-#define EERSV_BOOT_BEV      ((u8) 0x06)
-
-
-/*
- *     Bits in BPCMD
- */
-
-#define BPCMD_BPDNE         0x80
-#define BPCMD_EBPWR         0x02
-#define BPCMD_EBPRD         0x01
-
-/*
- *     Bits in the EECSR register
- */
-
-#define EECSR_EMBP          0x40       /* eeprom embedded programming */
-#define EECSR_RELOAD        0x20       /* eeprom content reload */
-#define EECSR_DPM           0x10       /* eeprom direct programming */
-#define EECSR_ECS           0x08       /* eeprom CS pin */
-#define EECSR_ECK           0x04       /* eeprom CK pin */
-#define EECSR_EDI           0x02       /* eeprom DI pin */
-#define EECSR_EDO           0x01       /* eeprom DO pin */
-
-/*
- *     Bits in the EMBCMD register
- */
-
-#define EMBCMD_EDONE        0x80
-#define EMBCMD_EWDIS        0x08
-#define EMBCMD_EWEN         0x04
-#define EMBCMD_EWR          0x02
-#define EMBCMD_ERD          0x01
-
-/*
- *     Bits in TESTCFG register
- */
-
-#define TESTCFG_HBDIS       0x80
-
-/*
- *     Bits in CHIPGCR register
- */
-
-#define CHIPGCR_FCGMII      0x80       /* force GMII (else MII only) */
-#define CHIPGCR_FCFDX       0x40       /* force full duplex */
-#define CHIPGCR_FCRESV      0x20
-#define CHIPGCR_FCMODE      0x10       /* enable MAC forced mode */
-#define CHIPGCR_LPSOPT      0x08
-#define CHIPGCR_TM1US       0x04
-#define CHIPGCR_TM0US       0x02
-#define CHIPGCR_PHYINTEN    0x01
-
-/*
- *     Bits in WOLCR0
- */
-
-#define WOLCR_MSWOLEN7      0x0080     /* enable pattern match filtering */
-#define WOLCR_MSWOLEN6      0x0040
-#define WOLCR_MSWOLEN5      0x0020
-#define WOLCR_MSWOLEN4      0x0010
-#define WOLCR_MSWOLEN3      0x0008
-#define WOLCR_MSWOLEN2      0x0004
-#define WOLCR_MSWOLEN1      0x0002
-#define WOLCR_MSWOLEN0      0x0001
-#define WOLCR_ARP_EN        0x0001
-
-/*
- *     Bits in WOLCR1
- */
-
-#define WOLCR_LINKOFF_EN      0x0800   /* link off detected enable */
-#define WOLCR_LINKON_EN       0x0400   /* link on detected enable */
-#define WOLCR_MAGIC_EN        0x0200   /* magic packet filter enable */
-#define WOLCR_UNICAST_EN      0x0100   /* unicast filter enable */
-
-
-/*
- *     Bits in PWCFG
- */
-
-#define PWCFG_PHYPWOPT          0x80   /* internal MII I/F timing */
-#define PWCFG_PCISTICK          0x40   /* PCI sticky R/W enable */
-#define PWCFG_WOLTYPE           0x20   /* pulse(1) or button (0) */
-#define PWCFG_LEGCY_WOL         0x10
-#define PWCFG_PMCSR_PME_SR      0x08
-#define PWCFG_PMCSR_PME_EN      0x04   /* control by PCISTICK */
-#define PWCFG_LEGACY_WOLSR      0x02   /* Legacy WOL_SR shadow */
-#define PWCFG_LEGACY_WOLEN      0x01   /* Legacy WOL_EN shadow */
-
-/*
- *     Bits in WOLCFG
- */
-
-#define WOLCFG_PMEOVR           0x80   /* for legacy use, force PMEEN always */
-#define WOLCFG_SAM              0x20   /* accept multicast case reset, default=0 */
-#define WOLCFG_SAB              0x10   /* accept broadcast case reset, default=0 */
-#define WOLCFG_SMIIACC          0x08   /* ?? */
-#define WOLCFG_SGENWH           0x02
-#define WOLCFG_PHYINTEN         0x01   /* 0:PHYINT trigger enable, 1:use internal MII
-                                         to report status change */
-/*
- *     Bits in WOLSR1
- */
-
-#define WOLSR_LINKOFF_INT      0x0800
-#define WOLSR_LINKON_INT       0x0400
-#define WOLSR_MAGIC_INT        0x0200
-#define WOLSR_UNICAST_INT      0x0100
-
-/*
- *     Ethernet address filter type
- */
-
-#define PKT_TYPE_NONE               0x0000     /* Turn off receiver */
-#define PKT_TYPE_DIRECTED           0x0001     /* obselete, directed address is always accepted */
-#define PKT_TYPE_MULTICAST          0x0002
-#define PKT_TYPE_ALL_MULTICAST      0x0004
-#define PKT_TYPE_BROADCAST          0x0008
-#define PKT_TYPE_PROMISCUOUS        0x0020
-#define PKT_TYPE_LONG               0x2000     /* NOTE.... the definition of LONG is >2048 bytes in our chip */
-#define PKT_TYPE_RUNT               0x4000
-#define PKT_TYPE_ERROR              0x8000     /* Accept error packets, e.g. CRC error */
-
-/*
- *     Loopback mode
- */
-
-#define MAC_LB_NONE         0x00
-#define MAC_LB_INTERNAL     0x01
-#define MAC_LB_EXTERNAL     0x02
-
-/*
- *     Enabled mask value of irq
- */
-
-#if defined(_SIM)
-#define IMR_MASK_VALUE      0x0033FF0FUL       /* initial value of IMR
-                                                  set IMR0 to 0x0F according to spec */
-
-#else
-#define IMR_MASK_VALUE      0x0013FB0FUL       /* initial value of IMR
-                                                  ignore MIBFI,RACEI to
-                                                  reduce intr. frequency
-                                                  NOTE.... do not enable NoBuf int mask at driver driver
-                                                     when (1) NoBuf -> RxThreshold = SF
-                                                          (2) OK    -> RxThreshold = original value
-                                                */
-#endif
-
-/*
- *     Revision id
- */
-
-#define REV_ID_VT3119_A0       0x00
-#define REV_ID_VT3119_A1       0x01
-#define REV_ID_VT3216_A0       0x10
-
-/*
- *     Max time out delay time
- */
-
-#define W_MAX_TIMEOUT       0x0FFFU
-
-
-/*
- *     MAC registers as a structure. Cannot be directly accessed this
- *     way but generates offsets for readl/writel() calls
- */
-
-struct mac_regs {
-       volatile u8 PAR[6];             /* 0x00 */
-       volatile u8 RCR;
-       volatile u8 TCR;
-
-       volatile __le32 CR0Set;         /* 0x08 */
-       volatile __le32 CR0Clr;         /* 0x0C */
-
-       volatile u8 MARCAM[8];          /* 0x10 */
-
-       volatile __le32 DecBaseHi;      /* 0x18 */
-       volatile __le16 DbfBaseHi;      /* 0x1C */
-       volatile __le16 reserved_1E;
-
-       volatile __le16 ISRCTL;         /* 0x20 */
-       volatile u8 TXESR;
-       volatile u8 RXESR;
-
-       volatile __le32 ISR;            /* 0x24 */
-       volatile __le32 IMR;
-
-       volatile __le32 TDStatusPort;   /* 0x2C */
-
-       volatile __le16 TDCSRSet;       /* 0x30 */
-       volatile u8 RDCSRSet;
-       volatile u8 reserved_33;
-       volatile __le16 TDCSRClr;
-       volatile u8 RDCSRClr;
-       volatile u8 reserved_37;
-
-       volatile __le32 RDBaseLo;       /* 0x38 */
-       volatile __le16 RDIdx;          /* 0x3C */
-       volatile u8 TQETMR;             /* 0x3E, VT3216 and above only */
-       volatile u8 RQETMR;             /* 0x3F, VT3216 and above only */
-
-       volatile __le32 TDBaseLo[4];    /* 0x40 */
-
-       volatile __le16 RDCSize;        /* 0x50 */
-       volatile __le16 TDCSize;        /* 0x52 */
-       volatile __le16 TDIdx[4];       /* 0x54 */
-       volatile __le16 tx_pause_timer; /* 0x5C */
-       volatile __le16 RBRDU;          /* 0x5E */
-
-       volatile __le32 FIFOTest0;      /* 0x60 */
-       volatile __le32 FIFOTest1;      /* 0x64 */
-
-       volatile u8 CAMADDR;            /* 0x68 */
-       volatile u8 CAMCR;              /* 0x69 */
-       volatile u8 GFTEST;             /* 0x6A */
-       volatile u8 FTSTCMD;            /* 0x6B */
-
-       volatile u8 MIICFG;             /* 0x6C */
-       volatile u8 MIISR;
-       volatile u8 PHYSR0;
-       volatile u8 PHYSR1;
-       volatile u8 MIICR;
-       volatile u8 MIIADR;
-       volatile __le16 MIIDATA;
-
-       volatile __le16 SoftTimer0;     /* 0x74 */
-       volatile __le16 SoftTimer1;
-
-       volatile u8 CFGA;               /* 0x78 */
-       volatile u8 CFGB;
-       volatile u8 CFGC;
-       volatile u8 CFGD;
-
-       volatile __le16 DCFG;           /* 0x7C */
-       volatile __le16 MCFG;
-
-       volatile u8 TBIST;              /* 0x80 */
-       volatile u8 RBIST;
-       volatile u8 PMCPORT;
-       volatile u8 STICKHW;
-
-       volatile u8 MIBCR;              /* 0x84 */
-       volatile u8 reserved_85;
-       volatile u8 rev_id;
-       volatile u8 PORSTS;
-
-       volatile __le32 MIBData;        /* 0x88 */
-
-       volatile __le16 EEWrData;
-
-       volatile u8 reserved_8E;
-       volatile u8 BPMDWr;
-       volatile u8 BPCMD;
-       volatile u8 BPMDRd;
-
-       volatile u8 EECHKSUM;           /* 0x92 */
-       volatile u8 EECSR;
-
-       volatile __le16 EERdData;       /* 0x94 */
-       volatile u8 EADDR;
-       volatile u8 EMBCMD;
-
-
-       volatile u8 JMPSR0;             /* 0x98 */
-       volatile u8 JMPSR1;
-       volatile u8 JMPSR2;
-       volatile u8 JMPSR3;
-       volatile u8 CHIPGSR;            /* 0x9C */
-       volatile u8 TESTCFG;
-       volatile u8 DEBUG;
-       volatile u8 CHIPGCR;
-
-       volatile __le16 WOLCRSet;       /* 0xA0 */
-       volatile u8 PWCFGSet;
-       volatile u8 WOLCFGSet;
-
-       volatile __le16 WOLCRClr;       /* 0xA4 */
-       volatile u8 PWCFGCLR;
-       volatile u8 WOLCFGClr;
-
-       volatile __le16 WOLSRSet;       /* 0xA8 */
-       volatile __le16 reserved_AA;
-
-       volatile __le16 WOLSRClr;       /* 0xAC */
-       volatile __le16 reserved_AE;
-
-       volatile __le16 PatternCRC[8];  /* 0xB0 */
-       volatile __le32 ByteMask[4][4]; /* 0xC0 */
-};
-
-
-enum hw_mib {
-       HW_MIB_ifRxAllPkts = 0,
-       HW_MIB_ifRxOkPkts,
-       HW_MIB_ifTxOkPkts,
-       HW_MIB_ifRxErrorPkts,
-       HW_MIB_ifRxRuntOkPkt,
-       HW_MIB_ifRxRuntErrPkt,
-       HW_MIB_ifRx64Pkts,
-       HW_MIB_ifTx64Pkts,
-       HW_MIB_ifRx65To127Pkts,
-       HW_MIB_ifTx65To127Pkts,
-       HW_MIB_ifRx128To255Pkts,
-       HW_MIB_ifTx128To255Pkts,
-       HW_MIB_ifRx256To511Pkts,
-       HW_MIB_ifTx256To511Pkts,
-       HW_MIB_ifRx512To1023Pkts,
-       HW_MIB_ifTx512To1023Pkts,
-       HW_MIB_ifRx1024To1518Pkts,
-       HW_MIB_ifTx1024To1518Pkts,
-       HW_MIB_ifTxEtherCollisions,
-       HW_MIB_ifRxPktCRCE,
-       HW_MIB_ifRxJumboPkts,
-       HW_MIB_ifTxJumboPkts,
-       HW_MIB_ifRxMacControlFrames,
-       HW_MIB_ifTxMacControlFrames,
-       HW_MIB_ifRxPktFAE,
-       HW_MIB_ifRxLongOkPkt,
-       HW_MIB_ifRxLongPktErrPkt,
-       HW_MIB_ifTXSQEErrors,
-       HW_MIB_ifRxNobuf,
-       HW_MIB_ifRxSymbolErrors,
-       HW_MIB_ifInRangeLengthErrors,
-       HW_MIB_ifLateCollisions,
-       HW_MIB_SIZE
-};
-
-enum chip_type {
-       CHIP_TYPE_VT6110 = 1,
-};
-
-struct velocity_info_tbl {
-       enum chip_type chip_id;
-       const char *name;
-       int txqueue;
-       u32 flags;
-};
-
-#define mac_hw_mibs_init(regs) {\
-       BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\
-       BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\
-       do {}\
-               while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\
-       BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\
-}
-
-#define mac_read_isr(regs)             readl(&((regs)->ISR))
-#define mac_write_isr(regs, x)         writel((x),&((regs)->ISR))
-#define mac_clear_isr(regs)            writel(0xffffffffL,&((regs)->ISR))
-
-#define mac_write_int_mask(mask, regs)         writel((mask),&((regs)->IMR));
-#define mac_disable_int(regs)          writel(CR0_GINTMSK1,&((regs)->CR0Clr))
-#define mac_enable_int(regs)           writel(CR0_GINTMSK1,&((regs)->CR0Set))
-
-#define mac_set_dma_length(regs, n) {\
-       BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\
-}
-
-#define mac_set_rx_thresh(regs, n) {\
-       BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\
-}
-
-#define mac_rx_queue_run(regs) {\
-       writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\
-}
-
-#define mac_rx_queue_wake(regs) {\
-       writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\
-}
-
-#define mac_tx_queue_run(regs, n) {\
-       writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\
-}
-
-#define mac_tx_queue_wake(regs, n) {\
-       writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\
-}
-
-static inline void mac_eeprom_reload(struct mac_regs __iomem * regs) {
-       int i=0;
-
-       BYTE_REG_BITS_ON(EECSR_RELOAD,&(regs->EECSR));
-       do {
-               udelay(10);
-               if (i++>0x1000)
-                       break;
-       } while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&(regs->EECSR)));
-}
-
-/*
- * Header for WOL definitions. Used to compute hashes
- */
-
-typedef u8 MCAM_ADDR[ETH_ALEN];
-
-struct arp_packet {
-       u8 dest_mac[ETH_ALEN];
-       u8 src_mac[ETH_ALEN];
-       __be16 type;
-       __be16 ar_hrd;
-       __be16 ar_pro;
-       u8 ar_hln;
-       u8 ar_pln;
-       __be16 ar_op;
-       u8 ar_sha[ETH_ALEN];
-       u8 ar_sip[4];
-       u8 ar_tha[ETH_ALEN];
-       u8 ar_tip[4];
-} __packed;
-
-struct _magic_packet {
-       u8 dest_mac[6];
-       u8 src_mac[6];
-       __be16 type;
-       u8 MAC[16][6];
-       u8 password[6];
-} __packed;
-
-/*
- *     Store for chip context when saving and restoring status. Not
- *     all fields are saved/restored currently.
- */
-
-struct velocity_context {
-       u8 mac_reg[256];
-       MCAM_ADDR cam_addr[MCAM_SIZE];
-       u16 vcam[VCAM_SIZE];
-       u32 cammask[2];
-       u32 patcrc[2];
-       u32 pattern[8];
-};
-
-/*
- *     Registers in the MII (offset unit is WORD)
- */
-
-// Marvell 88E1000/88E1000S
-#define MII_REG_PSCR        0x10       // PHY specific control register
-
-//
-// Bits in the Silicon revision register
-//
-
-#define TCSR_ECHODIS        0x2000     //
-#define AUXCR_MDPPS         0x0004     //
-
-// Bits in the PLED register
-#define PLED_LALBE                     0x0004  //
-
-// Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h)
-#define PSCR_ACRSTX         0x0800     // Assert CRS on Transmit
-
-#define PHYID_CICADA_CS8201 0x000FC410UL
-#define PHYID_VT3216_32BIT  0x000FC610UL
-#define PHYID_VT3216_64BIT  0x000FC600UL
-#define PHYID_MARVELL_1000  0x01410C50UL
-#define PHYID_MARVELL_1000S 0x01410C40UL
-
-#define PHYID_REV_ID_MASK   0x0000000FUL
-
-#define PHYID_GET_PHY_ID(i)         ((i) & ~PHYID_REV_ID_MASK)
-
-#define MII_REG_BITS_ON(x,i,p) do {\
-    u16 w;\
-    velocity_mii_read((p),(i),&(w));\
-    (w)|=(x);\
-    velocity_mii_write((p),(i),(w));\
-} while (0)
-
-#define MII_REG_BITS_OFF(x,i,p) do {\
-    u16 w;\
-    velocity_mii_read((p),(i),&(w));\
-    (w)&=(~(x));\
-    velocity_mii_write((p),(i),(w));\
-} while (0)
-
-#define MII_REG_BITS_IS_ON(x,i,p) ({\
-    u16 w;\
-    velocity_mii_read((p),(i),&(w));\
-    ((int) ((w) & (x)));})
-
-#define MII_GET_PHY_ID(p) ({\
-    u32 id;\
-    velocity_mii_read((p),MII_PHYSID2,(u16 *) &id);\
-    velocity_mii_read((p),MII_PHYSID1,((u16 *) &id)+1);\
-    (id);})
-
-/*
- * Inline debug routine
- */
-
-
-enum velocity_msg_level {
-       MSG_LEVEL_ERR = 0,      //Errors that will cause abnormal operation.
-       MSG_LEVEL_NOTICE = 1,   //Some errors need users to be notified.
-       MSG_LEVEL_INFO = 2,     //Normal message.
-       MSG_LEVEL_VERBOSE = 3,  //Will report all trival errors.
-       MSG_LEVEL_DEBUG = 4     //Only for debug purpose.
-};
-
-#ifdef VELOCITY_DEBUG
-#define ASSERT(x) { \
-       if (!(x)) { \
-               printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x,\
-                       __func__, __LINE__);\
-               BUG(); \
-       }\
-}
-#define VELOCITY_DBG(p,args...) printk(p, ##args)
-#else
-#define ASSERT(x)
-#define VELOCITY_DBG(x)
-#endif
-
-#define VELOCITY_PRT(l, p, args...) do {if (l<=msglevel) printk( p ,##args);} while (0)
-
-#define VELOCITY_PRT_CAMMASK(p,t) {\
-       int i;\
-       if ((t)==VELOCITY_MULTICAST_CAM) {\
-               for (i=0;i<(MCAM_SIZE/8);i++)\
-                       printk("%02X",(p)->mCAMmask[i]);\
-       }\
-       else {\
-               for (i=0;i<(VCAM_SIZE/8);i++)\
-                       printk("%02X",(p)->vCAMmask[i]);\
-       }\
-       printk("\n");\
-}
-
-
-
-#define     VELOCITY_WOL_MAGIC             0x00000000UL
-#define     VELOCITY_WOL_PHY               0x00000001UL
-#define     VELOCITY_WOL_ARP               0x00000002UL
-#define     VELOCITY_WOL_UCAST             0x00000004UL
-#define     VELOCITY_WOL_BCAST             0x00000010UL
-#define     VELOCITY_WOL_MCAST             0x00000020UL
-#define     VELOCITY_WOL_MAGIC_SEC         0x00000040UL
-
-/*
- *     Flags for options
- */
-
-#define     VELOCITY_FLAGS_TAGGING         0x00000001UL
-#define     VELOCITY_FLAGS_RX_CSUM         0x00000004UL
-#define     VELOCITY_FLAGS_IP_ALIGN        0x00000008UL
-#define     VELOCITY_FLAGS_VAL_PKT_LEN     0x00000010UL
-
-#define     VELOCITY_FLAGS_FLOW_CTRL       0x01000000UL
-
-/*
- *     Flags for driver status
- */
-
-#define     VELOCITY_FLAGS_OPENED          0x00010000UL
-#define     VELOCITY_FLAGS_VMNS_CONNECTED  0x00020000UL
-#define     VELOCITY_FLAGS_VMNS_COMMITTED  0x00040000UL
-#define     VELOCITY_FLAGS_WOL_ENABLED     0x00080000UL
-
-/*
- *     Flags for MII status
- */
-
-#define     VELOCITY_LINK_FAIL             0x00000001UL
-#define     VELOCITY_SPEED_10              0x00000002UL
-#define     VELOCITY_SPEED_100             0x00000004UL
-#define     VELOCITY_SPEED_1000            0x00000008UL
-#define     VELOCITY_DUPLEX_FULL           0x00000010UL
-#define     VELOCITY_AUTONEG_ENABLE        0x00000020UL
-#define     VELOCITY_FORCED_BY_EEPROM      0x00000040UL
-
-/*
- *     For velocity_set_media_duplex
- */
-
-#define     VELOCITY_LINK_CHANGE           0x00000001UL
-
-enum speed_opt {
-       SPD_DPX_AUTO = 0,
-       SPD_DPX_100_HALF = 1,
-       SPD_DPX_100_FULL = 2,
-       SPD_DPX_10_HALF = 3,
-       SPD_DPX_10_FULL = 4,
-       SPD_DPX_1000_FULL = 5
-};
-
-enum velocity_init_type {
-       VELOCITY_INIT_COLD = 0,
-       VELOCITY_INIT_RESET,
-       VELOCITY_INIT_WOL
-};
-
-enum velocity_flow_cntl_type {
-       FLOW_CNTL_DEFAULT = 1,
-       FLOW_CNTL_TX,
-       FLOW_CNTL_RX,
-       FLOW_CNTL_TX_RX,
-       FLOW_CNTL_DISABLE,
-};
-
-struct velocity_opt {
-       int numrx;                      /* Number of RX descriptors */
-       int numtx;                      /* Number of TX descriptors */
-       enum speed_opt spd_dpx;         /* Media link mode */
-
-       int DMA_length;                 /* DMA length */
-       int rx_thresh;                  /* RX_THRESH */
-       int flow_cntl;
-       int wol_opts;                   /* Wake on lan options */
-       int td_int_count;
-       int int_works;
-       int rx_bandwidth_hi;
-       int rx_bandwidth_lo;
-       int rx_bandwidth_en;
-       int rxqueue_timer;
-       int txqueue_timer;
-       int tx_intsup;
-       int rx_intsup;
-       u32 flags;
-};
-
-#define AVAIL_TD(p,q)   ((p)->options.numtx-((p)->tx.used[(q)]))
-
-#define GET_RD_BY_IDX(vptr, idx)   (vptr->rd_ring[idx])
-
-struct velocity_info {
-       struct pci_dev *pdev;
-       struct net_device *dev;
-
-       unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
-       u8 ip_addr[4];
-       enum chip_type chip_id;
-
-       struct mac_regs __iomem * mac_regs;
-       unsigned long memaddr;
-       unsigned long ioaddr;
-
-       struct tx_info {
-               int numq;
-
-               /* FIXME: the locality of the data seems rather poor. */
-               int used[TX_QUEUE_NO];
-               int curr[TX_QUEUE_NO];
-               int tail[TX_QUEUE_NO];
-               struct tx_desc *rings[TX_QUEUE_NO];
-               struct velocity_td_info *infos[TX_QUEUE_NO];
-               dma_addr_t pool_dma[TX_QUEUE_NO];
-       } tx;
-
-       struct rx_info {
-               int buf_sz;
-
-               int dirty;
-               int curr;
-               u32 filled;
-               struct rx_desc *ring;
-               struct velocity_rd_info *info;  /* It's an array */
-               dma_addr_t pool_dma;
-       } rx;
-
-       u32 mib_counter[MAX_HW_MIB_COUNTER];
-       struct velocity_opt options;
-
-       u32 int_mask;
-
-       u32 flags;
-
-       u32 mii_status;
-       u32 phy_id;
-       int multicast_limit;
-
-       u8 vCAMmask[(VCAM_SIZE / 8)];
-       u8 mCAMmask[(MCAM_SIZE / 8)];
-
-       spinlock_t lock;
-
-       int wol_opts;
-       u8 wol_passwd[6];
-
-       struct velocity_context context;
-
-       u32 ticks;
-
-       u8 rev_id;
-
-       struct napi_struct napi;
-};
-
-/**
- *     velocity_get_ip         -       find an IP address for the device
- *     @vptr: Velocity to query
- *
- *     Dig out an IP address for this interface so that we can
- *     configure wakeup with WOL for ARP. If there are multiple IP
- *     addresses on this chain then we use the first - multi-IP WOL is not
- *     supported.
- *
- */
-
-static inline int velocity_get_ip(struct velocity_info *vptr)
-{
-       struct in_device *in_dev;
-       struct in_ifaddr *ifa;
-       int res = -ENOENT;
-
-       rcu_read_lock();
-       in_dev = __in_dev_get_rcu(vptr->dev);
-       if (in_dev != NULL) {
-               ifa = (struct in_ifaddr *) in_dev->ifa_list;
-               if (ifa != NULL) {
-                       memcpy(vptr->ip_addr, &ifa->ifa_address, 4);
-                       res = 0;
-               }
-       }
-       rcu_read_unlock();
-       return res;
-}
-
-/**
- *     velocity_update_hw_mibs -       fetch MIB counters from chip
- *     @vptr: velocity to update
- *
- *     The velocity hardware keeps certain counters in the hardware
- *     side. We need to read these when the user asks for statistics
- *     or when they overflow (causing an interrupt). The read of the
- *     statistic clears it, so we keep running master counters in user
- *     space.
- */
-
-static inline void velocity_update_hw_mibs(struct velocity_info *vptr)
-{
-       u32 tmp;
-       int i;
-       BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR));
-
-       while (BYTE_REG_BITS_IS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)));
-
-       BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR));
-       for (i = 0; i < HW_MIB_SIZE; i++) {
-               tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL;
-               vptr->mib_counter[i] += tmp;
-       }
-}
-
-/**
- *     init_flow_control_register      -       set up flow control
- *     @vptr: velocity to configure
- *
- *     Configure the flow control registers for this velocity device.
- */
-
-static inline void init_flow_control_register(struct velocity_info *vptr)
-{
-       struct mac_regs __iomem * regs = vptr->mac_regs;
-
-       /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1}
-          depend on RD=64, and Turn on XNOEN in FlowCR1 */
-       writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), &regs->CR0Set);
-       writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), &regs->CR0Clr);
-
-       /* Set TxPauseTimer to 0xFFFF */
-       writew(0xFFFF, &regs->tx_pause_timer);
-
-       /* Initialize RBRDU to Rx buffer count. */
-       writew(vptr->options.numrx, &regs->RBRDU);
-}
-
-
-#endif