return ret;
}
+static void wl12xx_trigger_cmd(struct wl1271 *wl)
+{
+ wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
+}
+
+static void wl12xx_ack_event(struct wl1271 *wl)
+{
+ wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_EVENT_ACK);
+}
+
static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
{
bool supported = false;
static struct wlcore_ops wl12xx_ops = {
.identify_chip = wl12xx_identify_chip,
.boot = wl12xx_boot,
+ .trigger_cmd = wl12xx_trigger_cmd,
+ .ack_event = wl12xx_ack_event,
.get_pg_ver = wl12xx_get_pg_ver,
.get_mac = wl12xx_get_mac,
};
/* end PLL configuration algorithm for wl128x */
+/*
+ * Host Command Interrupt. Setting this bit masks
+ * the interrupt that the host issues to inform
+ * the FW that it has sent a command
+ * to the Wlan hardware Command Mailbox.
+ */
+#define WL12XX_INTR_TRIG_CMD BIT(0)
+
+/*
+ * Host Event Acknowlegde Interrupt. The host
+ * sets this bit to acknowledge that it received
+ * the unsolicited information from the event
+ * mailbox.
+ */
+#define WL12XX_INTR_TRIG_EVENT_ACK BIT(1)
+
/*===============================================
HI_CFG Interface Configuration Register Values
------------------------------------------
wl1271_write(wl, wl->cmd_box_addr, buf, len, false);
- wlcore_write_reg(wl, REG_INTERRUPT_TRIG, INTR_TRIG_CMD);
+ /*
+ * TODO: we just need this because one bit is in a different
+ * place. Is there any better way?
+ */
+ wl->ops->trigger_cmd(wl);
timeout = jiffies + msecs_to_jiffies(WL1271_COMMAND_TIMEOUT);
if (ret < 0)
return ret;
- /* then we let the firmware know it can go on...*/
- wlcore_write_reg(wl, REG_INTERRUPT_TRIG, INTR_TRIG_EVENT_ACK);
+ /*
+ * TODO: we just need this because one bit is in a different
+ * place. Is there any better way?
+ */
+ wl->ops->ack_event(wl);
return 0;
}
struct wlcore_ops {
int (*identify_chip)(struct wl1271 *wl);
int (*boot)(struct wl1271 *wl);
+ void (*trigger_cmd)(struct wl1271 *wl);
+ void (*ack_event)(struct wl1271 *wl);
s8 (*get_pg_ver)(struct wl1271 *wl);
void (*get_mac)(struct wl1271 *wl);
};
/* Hardware to Embedded CPU Interrupts - first 32-bit register set */
-/*
- * Host Command Interrupt. Setting this bit masks
- * the interrupt that the host issues to inform
- * the FW that it has sent a command
- * to the Wlan hardware Command Mailbox.
- */
-#define INTR_TRIG_CMD BIT(0)
-
-/*
- * Host Event Acknowlegde Interrupt. The host
- * sets this bit to acknowledge that it received
- * the unsolicited information from the event
- * mailbox.
- */
-#define INTR_TRIG_EVENT_ACK BIT(1)
-
/*
* The host sets this bit to inform the Wlan
* FW that a TX packet is in the XFER