Documentation: dt: socfpga: Add Arria10 Ethernet binding

Add the device tree bindings needed to support the Altera Ethernet FIFO
buffers on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1466603939-7526-6-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 15eb0df1d36ecf31cc7f1058af50173f31c7134d..b545856a444fe929078b7f84ce75537ce8e7485f 100644 (file)
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -82,6 +82,14 @@ Required Properties:
 - interrupts : Should be single bit error interrupt, then double bit error
        interrupt, in this order.
 
+Ethernet FIFO ECC
+Required Properties:
+- compatible      : Should be "altr,socfpga-eth-mac-ecc"
+- reg             : Address and size for ECC block registers.
+- altr,ecc-parent : phandle to parent Ethernet node.
+- interrupts      : Should be single bit error interrupt, then double bit error
+       interrupt, in this order.
+
 Example:
 
        eccmgr: eccmgr@ffd06000 {
@@ -108,4 +116,20 @@ Example:
                        interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
                                     <33 IRQ_TYPE_LEVEL_HIGH> ;
                };
+
+               emac0-rx-ecc@ff8c0800 {
+                       compatible = "altr,socfpga-eth-mac-ecc";
+                       reg = <0xff8c0800 0x400>;
+                       altr,ecc-parent = <&gmac0>;
+                       interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
+                                    <36 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               emac0-tx-ecc@ff8c0c00 {
+                       compatible = "altr,socfpga-eth-mac-ecc";
+                       reg = <0xff8c0c00 0x400>;
+                       altr,ecc-parent = <&gmac0>;
+                       interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
+                                    <37 IRQ_TYPE_LEVEL_HIGH>;
+               };
        };