clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6

The pll6 has a /4 output that is used as an input to the ahb mux clock.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 9f31314a9cd7afe339b1694d7a4745b0ca0596fb..7e1e2bd189b6a6f6f3c0047d6b3f4d6b5899c3c6 100644 (file)
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1088,11 +1088,12 @@ static const struct divs_data pll5_divs_data __initconst = {
 
 static const struct divs_data pll6_divs_data __initconst = {
        .factors = &sun4i_pll6_data,
-       .ndivs = 3,
+       .ndivs = 4,
        .div = {
                { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
                { .fixed = 2 }, /* P, other */
                { .self = 1 }, /* base factor clock, 2x */
+               { .fixed = 4 }, /* pll6 / 4, used as ahb input */
        }
 };