imx-drm: ipuv3-crtc: Invert IPU DI0 clock polarity

sig_cfg.clk_pol controls the 'di0_polarity_disp_clk' bit of register
IPUx_DI0_GENERAL through the following code in imx-drm/ipu-v3/ipu-di.c:

	if (!sig->clk_pol)
		di_gen |= DI_GEN_POLARITY_DISP_CLK;

With 'di0_polarity_disp_clk' bit set we do not have stable HDMI output on
mx6solo: contours of pictures look jittery and the white colour does not appear
really white.

Russell King initially reported this problem at:
http://www.spinics.net/lists/arm-kernel/msg279805.html

Inverting 'di0_polarity_disp_clk' leads to stable HDMI output image.

Tested on the following boards:
- mx6solowandboard (HDMI output)
- mx6qwandboard (HDMI output)
- mx6qsabrelite (LVDS)
- mx6qsabresd (HDMI output and LVDS)
- mx6dlsabresd (HDMI output)
- mx53qsb (parallel WVGA display)

Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Suggested-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index f1112dfa6bf6b4a861f7306b85d43ebd5b43baa6..670a56a834f112b590e05d357fe0e0a099c45b48 100644 (file)
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -157,7 +157,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
                sig_cfg.Vsync_pol = 1;
 
        sig_cfg.enable_pol = 1;
-       sig_cfg.clk_pol = 0;
+       sig_cfg.clk_pol = 1;
        sig_cfg.width = mode->hdisplay;
        sig_cfg.height = mode->vdisplay;
        sig_cfg.pixel_fmt = out_pixel_fmt;