[RAMEN9610-10169] fbdev: dpu20: added dqe hsc full pixel num

Change-Id: I89c38cfa93a2247cfdfa844438cd129c70b8175c
Signed-off-by: ChiHun Won <chihun.won@samsung.com>

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/dqe_reg.c b/drivers/video/fbdev/exynos/dpu20/cal_9610/dqe_reg.c
index 9a50fbfab8eb4a8d538fe4e64b22bb0819d53195..06f5a5758305009de4f0fb2e8fb006a70ab730a2 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/dqe_reg.c
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/dqe_reg.c
@@ -67,6 +67,20 @@ u32 dqe_reg_get_hsc_control(void)
        return dqe_read_mask(DQEHSC_CONTROL, HSC_ALL_MASK);
 }
 
+void dqe_reg_set_hsc_full_pxl_num(struct decon_lcd *lcd_info)
+{
+       u32 val, mask;
+
+       val = (u32)(lcd_info->xres * lcd_info->yres);
+       mask = DQEHSC_FULL_PXL_NUM_MASK;
+       dqe_write_mask(DQEHSC_FULL_PXL_NUM, val, mask);
+}
+
+u32 dqe_reg_get_hsc_full_pxl_num(void)
+{
+       return dqe_read_mask(DQEHSC_FULL_PXL_NUM, DQEHSC_FULL_PXL_NUM_MASK);
+}
+
 void dqe_reg_set_img_size(u32 id, struct decon_lcd *lcd_info)
 {
        u32 width, val, mask;

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-dqe.h b/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-dqe.h
index 0fa7f950de46b20cec9bd239e8829742db6f5913..4863eee82f2d8d31228431f21186e75522502432 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-dqe.h
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-dqe.h
@@ -249,6 +249,10 @@
 #define DQEHSC_POLY_CURVE2             0x022c
 #define DQEHSC_SKIN_H                  0x0240
 
+#define DQEHSC_FULL_PXL_NUM            0x0310
+#define DQEHSC_FULL_PXL_NUM_MASK       (0x03ffffff << 0)
+#define DQEHSC_FULL_PXL_NUM_GET(_v)    (((_v) >> 0) & 0x03ffffff)
+
 #define SHADOW_DQE_OFFSET              0x9000
 
 #endif

diff --git a/drivers/video/fbdev/exynos/dpu20/dqe.h b/drivers/video/fbdev/exynos/dpu20/dqe.h
index 47e6177cefb580fe1b60ad4feb0f1ec67be7c6a2..51fe116b318de4ed7b0032de8dd239f480a58c75 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/dqe.h
+++ b/drivers/video/fbdev/exynos/dpu20/dqe.h
@@ -117,6 +117,8 @@ void dqe_reg_set_hsc_ppsc_on(u32 on);
 void dqe_reg_set_hsc_control(u32 val);
 void dqe_reg_set_hsc_control_all_reset(void);
 u32 dqe_reg_get_hsc_control(void);
+void dqe_reg_set_hsc_full_pxl_num(struct decon_lcd *lcd_info);
+u32 dqe_reg_get_hsc_full_pxl_num(void);
 void dqe_reg_set_aps_on(u32 on);
 void dqe_reg_hsc_sw_reset(u32 en);
 void dqe_reg_aps_sw_reset(u32 en);

diff --git a/drivers/video/fbdev/exynos/dpu20/dqe_drv.c b/drivers/video/fbdev/exynos/dpu20/dqe_drv.c
index b281fc36fcb2b21e01b3df1a512530b55a870966..5c9d6bdde603f1f5da6c50f62717d344b618be18 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/dqe_drv.c
+++ b/drivers/video/fbdev/exynos/dpu20/dqe_drv.c
@@ -219,6 +219,7 @@ static int dqe_restore_context(void)
 {
        int i;
        struct dqe_device *dqe = dqe_drvdata;
+       struct decon_device *decon = dqe->decon;
 
        dqe_dbg("%s\n", __func__);
 
@@ -241,6 +242,11 @@ static int dqe_restore_context(void)
                                dqe->ctx.hsc[i].val);
 
        if (dqe->ctx.hsc_on) {
+               if (decon) {
+                       dqe_reg_set_hsc_full_pxl_num(decon->lcd_info);
+                       dqe_dbg("dqe DQEHSC_FULL_PXL_NUM: %d\n",
+                               dqe_reg_get_hsc_full_pxl_num());
+               }
                dqe_reg_set_hsc_control_all_reset();
                dqe_reg_set_hsc_on(1);
                dqe_reg_set_hsc_control(dqe->ctx.hsc_control);