ARM: 8661/1: dts: r7s72100: add l2 cache

Note that early-bresp-disable and full-line-zero-disable are required
because the sideband signals between the CPU and L2C were not connected
in this SoC.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index b8aa256bd51533ba4ba7484aa02d26738c040535..1cf2bd0380901d1d6f8ec05cfc38e693defaddfe 100644 (file)
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -177,6 +177,7 @@
                        compatible = "arm,cortex-a9";
                        reg = <0>;
                        clock-frequency = <400000000>;
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -368,6 +369,16 @@
                        <0xe8202000 0x1000>;
        };
 
+       L2: cache-controller@3ffff000 {
+               compatible = "arm,pl310-cache";
+               reg = <0x3ffff000 0x1000>;
+               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+               arm,early-bresp-disable;
+               arm,full-line-zero-disable;
+               cache-unified;
+               cache-level = <2>;
+       };
+
        i2c0: i2c@fcfee000 {
                #address-cells = <1>;
                #size-cells = <0>;