/* DWORD 0 */
tx_desc->TxHT = (tcb_desc->data_rate&0x80)?1:0;
-#ifdef RTL8192SU_DISABLE_CCK_RATE
- if(tx_hal_is_cck_rate(tcb_desc->data_rate))
- tcb_desc->data_rate = MGN_6M;
-#endif
tx_desc->TxRate = MRateToHwRate8190Pci(tcb_desc->data_rate);
//tx_desc->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur;
//update Basic rate: RR, BRSR
rtl8192_config_rate(dev, &rate_config); //HalSetBrateCfg
-#ifdef RTL8192SU_DISABLE_CCK_RATE
- priv->basic_rate = rate_config = rate_config & 0x150; // Disable CCK 11M, 5.5M, 2M, and 1M rates.
-#else
priv->basic_rate = rate_config = rate_config & 0x15f;
-#endif
// Set RRSR rate table.
write_nic_byte(dev, RRSR, rate_config&0xff);
break;
}
-#ifdef RTL8192SU_DISABLE_CCK_RATE
- ratr_value &= 0x0FFFFFF0;
-#else
ratr_value &= 0x0FFFFFFF;
-#endif
// Get MAX MCS available.
if ( (bNMode && ((ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_SHORT_GI)==0)) &&
// Set Data Auto Rate Fallback Reg. Added by Roger, 2008.09.22.
for (i = 0; i < 8; i++)
-#ifdef RTL8192SU_DISABLE_CCK_RATE
- write_nic_dword(dev, ARFR0+i*4, 0x1f0ff0f0);
-#else
write_nic_dword(dev, ARFR0+i*4, 0x1f0ffff0);
-#endif
//
// Set driver info, we only accept PHY status now.
// 2008.09.23.
//
regTmp = read_nic_byte(dev, INIRTSMCS_SEL);
-#ifdef RTL8192SU_DISABLE_CCK_RATE
- regRRSR = ((regRRSR & 0x000ffff0)<<8) | regTmp;
-#else
regRRSR = ((regRRSR & 0x000fffff)<<8) | regTmp;
-#endif
//
// Update SIFS timing.
// Set Data Auto Rate Fallback Reg. Added by Roger, 2008.09.22.
for (i = 0; i < 8; i++)
-#ifdef RTL8192SU_DISABLE_CCK_RATE
- write_nic_dword(dev, ARFR0+i*4, 0x1f0ff0f0);
-#else
write_nic_dword(dev, ARFR0+i*4, 0x1f0ffff0);
-#endif
//
// Aggregation length limit. Revised by Roger. 2008.09.22.