#include "comedi_fc.h"
#include "8255.h"
-#define _8255_SIZE 4
-
-#define _8255_DATA 0
-#define _8255_CR 3
-
-#define CR_C_LO_IO 0x01
-#define CR_B_IO 0x02
-#define CR_B_MODE 0x04
-#define CR_C_HI_IO 0x08
-#define CR_A_IO 0x10
-#define CR_A_MODE(a) ((a)<<5)
-#define CR_CW 0x80
-
struct subdev_8255_private {
unsigned long regbase;
int (*io)(struct comedi_device *, int, int, int, unsigned long);
mask = comedi_dio_update_state(s, data);
if (mask) {
if (mask & 0xff)
- spriv->io(dev, 1, _8255_DATA, s->state & 0xff, regbase);
+ spriv->io(dev, 1, I8255_DATA_A_REG,
+ s->state & 0xff, regbase);
if (mask & 0xff00)
- spriv->io(dev, 1, _8255_DATA + 1,
+ spriv->io(dev, 1, I8255_DATA_B_REG,
(s->state >> 8) & 0xff, regbase);
if (mask & 0xff0000)
- spriv->io(dev, 1, _8255_DATA + 2,
+ spriv->io(dev, 1, I8255_DATA_C_REG,
(s->state >> 16) & 0xff, regbase);
}
- v = spriv->io(dev, 0, _8255_DATA, 0, regbase);
- v |= (spriv->io(dev, 0, _8255_DATA + 1, 0, regbase) << 8);
- v |= (spriv->io(dev, 0, _8255_DATA + 2, 0, regbase) << 16);
+ v = spriv->io(dev, 0, I8255_DATA_A_REG, 0, regbase);
+ v |= (spriv->io(dev, 0, I8255_DATA_B_REG, 0, regbase) << 8);
+ v |= (spriv->io(dev, 0, I8255_DATA_C_REG, 0, regbase) << 16);
data[1] = v;
unsigned long regbase = spriv->regbase;
int config;
- config = CR_CW;
+ config = I8255_CTRL_CW;
/* 1 in io_bits indicates output, 1 in config indicates input */
if (!(s->io_bits & 0x0000ff))
- config |= CR_A_IO;
+ config |= I8255_CTRL_A_IO;
if (!(s->io_bits & 0x00ff00))
- config |= CR_B_IO;
+ config |= I8255_CTRL_B_IO;
if (!(s->io_bits & 0x0f0000))
- config |= CR_C_LO_IO;
+ config |= I8255_CTRL_C_LO_IO;
if (!(s->io_bits & 0xf00000))
- config |= CR_C_HI_IO;
+ config |= I8255_CTRL_C_HI_IO;
- spriv->io(dev, 1, _8255_CR, config, regbase);
+ spriv->io(dev, 1, I8255_CTRL_REG, config, regbase);
}
static int subdev_8255_insn_config(struct comedi_device *dev,
* comedi_config, the 'iobase' is the actual I/O port
* base address of the chip.
*/
- ret = __comedi_request_region(dev, iobase, _8255_SIZE);
+ ret = __comedi_request_region(dev, iobase, I8255_SIZE);
if (ret) {
s->type = COMEDI_SUBD_UNUSED;
} else {
s = &dev->subdevices[i];
if (s->type != COMEDI_SUBD_UNUSED) {
spriv = s->private;
- release_region(spriv->regbase, _8255_SIZE);
+ release_region(spriv->regbase, I8255_SIZE);
}
}
}
#include "../comedidev.h"
+#define I8255_SIZE 0x04
+
+#define I8255_DATA_A_REG 0x00
+#define I8255_DATA_B_REG 0x01
+#define I8255_DATA_C_REG 0x02
+#define I8255_CTRL_REG 0x03
+#define I8255_CTRL_C_LO_IO (1 << 0)
+#define I8255_CTRL_B_IO (1 << 1)
+#define I8255_CTRL_B_MODE (1 << 2)
+#define I8255_CTRL_C_HI_IO (1 << 3)
+#define I8255_CTRL_A_IO (1 << 4)
+#define I8255_CTRL_A_MODE(x) ((x) << 5)
+#define I8255_CTRL_CW (1 << 7)
+
int subdev_8255_init(struct comedi_device *, struct comedi_subdevice *,
int (*io)(struct comedi_device *,
int, int, int, unsigned long),
for (i = 0; i < board->n_8255; i++) {
s = &dev->subdevices[i];
if (dev->mmio)
- ret = subdev_8255_mm_init(dev, s, NULL, i * 4);
+ ret = subdev_8255_mm_init(dev, s, NULL, i * I8255_SIZE);
else
- ret = subdev_8255_init(dev, s, NULL, i * 4);
+ ret = subdev_8255_init(dev, s, NULL, i * I8255_SIZE);
if (ret)
return ret;
}
* subdevice) */
#define SIZE_8254 4 /* 8254 IO space length */
-#define SIZE_8255 4 /* 8255 IO space length */
#define PCIDIO_MAINREG 2 /* main I/O region for all Advantech cards? */
s = &dev->subdevices[subdev];
ret = subdev_8255_init(dev, s, NULL,
this_board->sdio[i].addr +
- SIZE_8255 * j);
+ j * I8255_SIZE);
if (ret)
return ret;
subdev++;
#include "amplc_dio200.h"
#include "comedi_fc.h"
#include "8253.h"
-
-/* 8255 control register bits */
-#define CR_C_LO_IO 0x01
-#define CR_B_IO 0x02
-#define CR_B_MODE 0x04
-#define CR_C_HI_IO 0x08
-#define CR_A_IO 0x10
-#define CR_A_MODE(a) ((a)<<5)
-#define CR_CW 0x80
+#include "8255.h" /* only for register defines */
/* 200 series registers */
#define DIO200_IO_SIZE 0x20
struct dio200_subdev_8255 *subpriv = s->private;
int config;
- config = CR_CW;
+ config = I8255_CTRL_CW;
/* 1 in io_bits indicates output, 1 in config indicates input */
if (!(s->io_bits & 0x0000ff))
- config |= CR_A_IO;
+ config |= I8255_CTRL_A_IO;
if (!(s->io_bits & 0x00ff00))
- config |= CR_B_IO;
+ config |= I8255_CTRL_B_IO;
if (!(s->io_bits & 0x0f0000))
- config |= CR_C_LO_IO;
+ config |= I8255_CTRL_C_LO_IO;
if (!(s->io_bits & 0xf00000))
- config |= CR_C_HI_IO;
- dio200_write8(dev, subpriv->ofs + 3, config);
+ config |= I8255_CTRL_C_HI_IO;
+ dio200_write8(dev, subpriv->ofs + I8255_CTRL_REG, config);
}
static int dio200_subdev_8255_bits(struct comedi_device *dev,
mask = comedi_dio_update_state(s, data);
if (mask) {
if (mask & 0xff)
- dio200_write8(dev, subpriv->ofs, s->state & 0xff);
+ dio200_write8(dev, subpriv->ofs + I8255_DATA_A_REG,
+ s->state & 0xff);
if (mask & 0xff00)
- dio200_write8(dev, subpriv->ofs + 1,
+ dio200_write8(dev, subpriv->ofs + I8255_DATA_B_REG,
(s->state >> 8) & 0xff);
if (mask & 0xff0000)
- dio200_write8(dev, subpriv->ofs + 2,
+ dio200_write8(dev, subpriv->ofs + I8255_DATA_C_REG,
(s->state >> 16) & 0xff);
}
- val = dio200_read8(dev, subpriv->ofs);
- val |= dio200_read8(dev, subpriv->ofs + 1) << 8;
- val |= dio200_read8(dev, subpriv->ofs + 2) << 16;
+ val = dio200_read8(dev, subpriv->ofs + I8255_DATA_A_REG);
+ val |= dio200_read8(dev, subpriv->ofs + I8255_DATA_B_REG) << 8;
+ val |= dio200_read8(dev, subpriv->ofs + I8255_DATA_C_REG) << 16;
data[1] = val;
/* two 8255 digital io subdevices */
for (i = 0; i < 2; i++) {
s = &dev->subdevices[1 + i];
- ret = subdev_8255_init(dev, s, NULL, i * 4);
+ ret = subdev_8255_init(dev, s, NULL, i * I8255_SIZE);
if (ret)
return ret;
}
#include "8255.h"
-#define SIZE_8255 4
-
struct pcl724_board {
const char *name;
unsigned int io_range;
int dir, int port, int data,
unsigned long iobase)
{
- int movport = SIZE_8255 * (iobase >> 12);
+ int movport = I8255_SIZE * (iobase >> 12);
iobase &= 0x0fff;
ret = subdev_8255_init(dev, s, pcl724_8255mapped_io,
iobase);
} else {
- ret = subdev_8255_init(dev, s, NULL, i * SIZE_8255);
+ ret = subdev_8255_init(dev, s, NULL, i * I8255_SIZE);
}
if (ret)
return ret;
#include "8255.h"
-#define SIZE_8255 4
-
#define BUF_C0 0x1
#define BUF_B0 0x2
#define BUF_A0 0x4
#define GATE_B1 0x10
#define GATE_C1 0x8
-/* from 8255.c */
-#define CR_CW 0x80
-#define _8255_CR 3
-#define CR_B_IO 0x02
-#define CR_B_MODE 0x04
-#define CR_C_IO 0x09
-#define CR_A_IO 0x10
-#define CR_A_MODE(a) ((a)<<5)
-#define CR_CW 0x80
-
/* used to track configured dios */
struct priv_pcm3724 {
int dio_1;
int buffer_config;
unsigned long port_8255_cfg;
- config = CR_CW;
+ config = I8255_CTRL_CW;
buffer_config = 0;
/* 1 in io_bits indicates output, 1 in config indicates input */
if (!(s->io_bits & 0x0000ff))
- config |= CR_A_IO;
+ config |= I8255_CTRL_A_IO;
if (!(s->io_bits & 0x00ff00))
- config |= CR_B_IO;
+ config |= I8255_CTRL_B_IO;
if (!(s->io_bits & 0xff0000))
- config |= CR_C_IO;
+ config |= I8255_CTRL_C_HI_IO | I8255_CTRL_C_LO_IO;
buffer_config = compute_buffer(0, 0, s_dio1);
buffer_config = compute_buffer(buffer_config, 1, s_dio2);
if (s == s_dio1)
- port_8255_cfg = dev->iobase + _8255_CR;
+ port_8255_cfg = dev->iobase + I8255_CTRL_REG;
else
- port_8255_cfg = dev->iobase + SIZE_8255 + _8255_CR;
+ port_8255_cfg = dev->iobase + I8255_SIZE + I8255_CTRL_REG;
outb(buffer_config, dev->iobase + 8); /* update buffer register */
for (i = 0; i < dev->n_subdevices; i++) {
s = &dev->subdevices[i];
- ret = subdev_8255_init(dev, s, NULL, i * SIZE_8255);
+ ret = subdev_8255_init(dev, s, NULL, i * I8255_SIZE);
if (ret)
return ret;
s->insn_config = subdev_3724_insn_config;