selftests/powerpc: Add more SPR numbers, TM & VMX instructions to 'reg.h'/'instructio...

This patch adds SPR number for TAR, PPR, DSCR special
purpose registers. It also adds TM, VSX, VMX related
instructions which will then be used by patches later
in the series.

Now that the new DSCR register definitions (SPRN_DSCR_PRIV and
SPRN_DSCR) are defined outside this directory, use them instead.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/tools/testing/selftests/powerpc/dscr/dscr.h b/tools/testing/selftests/powerpc/dscr/dscr.h
index a36af1b2c2bb30b1ddd7e8c284e448f6e3f5acef..18ea223bd398a27aa966e3007e418f6a19d0de2c 100644 (file)
--- a/tools/testing/selftests/powerpc/dscr/dscr.h
+++ b/tools/testing/selftests/powerpc/dscr/dscr.h
@@ -28,8 +28,6 @@
 
 #include "utils.h"
 
-#define SPRN_DSCR      0x11    /* Privilege state SPR */
-#define SPRN_DSCR_USR  0x03    /* Problem state SPR */
 #define THREADS                100     /* Max threads */
 #define COUNT          100     /* Max iterations */
 #define DSCR_MAX       16      /* Max DSCR value */
@@ -48,14 +46,14 @@ inline unsigned long get_dscr(void)
 {
        unsigned long ret;
 
-       asm volatile("mfspr %0,%1" : "=r" (ret): "i" (SPRN_DSCR));
+       asm volatile("mfspr %0,%1" : "=r" (ret) : "i" (SPRN_DSCR_PRIV));
 
        return ret;
 }
 
 inline void set_dscr(unsigned long val)
 {
-       asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR));
+       asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR_PRIV));
 }
 
 /* Problem state DSCR access */
@@ -63,14 +61,14 @@ inline unsigned long get_dscr_usr(void)
 {
        unsigned long ret;
 
-       asm volatile("mfspr %0,%1" : "=r" (ret): "i" (SPRN_DSCR_USR));
+       asm volatile("mfspr %0,%1" : "=r" (ret) : "i" (SPRN_DSCR));
 
        return ret;
 }
 
 inline void set_dscr_usr(unsigned long val)
 {
-       asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR_USR));
+       asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR));
 }
 
 /* Default DSCR access */

diff --git a/tools/testing/selftests/powerpc/reg.h b/tools/testing/selftests/powerpc/reg.h
index 65bfdeeebdee876c77a2094776b4904f440eca4f..bb843b2d9bacb2916256c9062ff72f85ea765b5b 100644 (file)
--- a/tools/testing/selftests/powerpc/reg.h
+++ b/tools/testing/selftests/powerpc/reg.h
@@ -46,10 +46,39 @@
 #define SPRN_SDAR      781
 #define SPRN_SIER      768
 
-#define SPRN_TEXASR     0x82
+#define SPRN_TEXASR     0x82    /* Transaction Exception and Status Register */
 #define SPRN_TFIAR      0x81    /* Transaction Failure Inst Addr    */
 #define SPRN_TFHAR      0x80    /* Transaction Failure Handler Addr */
-#define TEXASR_FS       0x08000000
-#define SPRN_TAR        0x32f
+#define SPRN_TAR        0x32f  /* Target Address Register */
+
+#define SPRN_DSCR_PRIV 0x11    /* Privilege State DSCR */
+#define SPRN_DSCR      0x03    /* Data Stream Control Register */
+#define SPRN_PPR       896     /* Program Priority Register */
+
+/* TEXASR register bits */
+#define TEXASR_FC      0xFE00000000000000
+#define TEXASR_FP      0x0100000000000000
+#define TEXASR_DA      0x0080000000000000
+#define TEXASR_NO      0x0040000000000000
+#define TEXASR_FO      0x0020000000000000
+#define TEXASR_SIC     0x0010000000000000
+#define TEXASR_NTC     0x0008000000000000
+#define TEXASR_TC      0x0004000000000000
+#define TEXASR_TIC     0x0002000000000000
+#define TEXASR_IC      0x0001000000000000
+#define TEXASR_IFC     0x0000800000000000
+#define TEXASR_ABT     0x0000000100000000
+#define TEXASR_SPD     0x0000000080000000
+#define TEXASR_HV      0x0000000020000000
+#define TEXASR_PR      0x0000000010000000
+#define TEXASR_FS      0x0000000008000000
+#define TEXASR_TE      0x0000000004000000
+#define TEXASR_ROT     0x0000000002000000
+
+/* Vector Instructions */
+#define VSX_XX1(xs, ra, rb)    (((xs) & 0x1f) << 21 | ((ra) << 16) |  \
+                                ((rb) << 11) | (((xs) >> 5)))
+#define STXVD2X(xs, ra, rb)    .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
+#define LXVD2X(xs, ra, rb)     .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
 
 #endif /* _SELFTESTS_POWERPC_REG_H */