mmc: meson-gx: initialize sane clk default before clock register

On boot, the clock divider value is 0 which is a weird unsupported value.
For example, accessing the cfg register with this value set would crash
the SoC.

Previous change removed 0 as possible value for CCF but forgot to properly
initialize the register before registering the clock. This leads to the
CCF finding an illegal value, which it complains about.

Initialize the register properly in a standalone patch so the fix can be
picked up if necessary. The change this fixed is: "mmc: meson-gx: remove
CLK_DIVIDER_ALLOW_ZERO clock flag".

Reported-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 8a74a048db8812821adaa59169c4fc008e2a0e76..d2de5c11cdcebe5f03ae1a585ce0db11d1bb0c76 100644 (file)
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -339,6 +339,15 @@ static int meson_mmc_clk_init(struct meson_host *host)
        const char *clk_div_parents[1];
        u32 clk_reg, cfg;
 
+       /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
+       clk_reg = 0;
+       clk_reg |= CLK_ALWAYS_ON;
+       clk_reg |= CLK_DIV_MASK;
+       clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase);
+       clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase);
+       clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase);
+       writel(clk_reg, host->regs + SD_EMMC_CLOCK);
+
        /* get the mux parents */
        for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
                struct clk *clk;
@@ -393,16 +402,6 @@ static int meson_mmc_clk_init(struct meson_host *host)
        if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk)))
                return PTR_ERR(host->cfg_div_clk);
 
-       /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
-       clk_reg = 0;
-       clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase);
-       clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase);
-       clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase);
-       clk_reg |= FIELD_PREP(CLK_SRC_MASK, CLK_SRC_XTAL);
-       clk_reg |= FIELD_PREP(CLK_DIV_MASK, CLK_DIV_MAX);
-       clk_reg &= ~CLK_ALWAYS_ON;
-       writel(clk_reg, host->regs + SD_EMMC_CLOCK);
-
        /* Ensure clock starts in "auto" mode, not "always on" */
        cfg = readl(host->regs + SD_EMMC_CFG);
        cfg &= ~CFG_CLK_ALWAYS_ON;