/* reset fifo */
ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
if (devpriv->is_6xxx)
- ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
+ ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
/* load some data */
nbytes = comedi_buf_read_n_available(s);
int i;
if (devpriv->is_6xxx) {
- ni_ao_win_outw(dev, 1 << chan, AO_Immediate_671x);
+ ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
- reg = DACx_Direct_Data_671x(chan);
+ reg = NI671X_DAC_DIRECT_DATA_REG(chan);
} else if (devpriv->is_m_series) {
reg = NI_M_DAC_DIRECT_DATA_REG(chan);
} else {
#ifdef PCIDMA
ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
if (devpriv->is_6xxx)
- ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
+ ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
ret = ni_ao_setup_MITE_dma(dev);
if (ret)
return ret;
ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
if (devpriv->is_6xxx) {
- ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
+ ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
+ NI611X_AO_MISC_REG);
bits = 0;
for (i = 0; i < cmd->chanlist_len; i++) {
chan = CR_CHAN(cmd->chanlist[i]);
bits |= 1 << chan;
- ni_ao_win_outw(dev, chan, AO_Waveform_Generation_611x);
+ ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
}
- ni_ao_win_outw(dev, bits, AO_Timed_611x);
+ ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
}
ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
for (i = 0; i < s->n_chan; ++i)
immediate_bits |= 1 << i;
- ni_ao_win_outw(dev, immediate_bits, AO_Immediate_671x);
- ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
+ ni_ao_win_outw(dev, immediate_bits, NI671X_AO_IMMEDIATE_REG);
+ ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
+ NI611X_AO_MISC_REG);
}
ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
for (i = 0; i < s->n_chan; i++) {
ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
- AO_Configuration_2_67xx);
+ NI67XX_AO_CFG2_REG);
}
- ni_ao_win_outw(dev, 0x0, AO_Later_Single_Point_Updates);
+ ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
}
static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
int i;
for (i = 0; i < timeout; i++) {
- status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
- if ((status & CSS_ADC_BUSY) == 0)
+ status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
+ if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
break;
set_current_state(TASK_INTERRUPTIBLE);
if (schedule_timeout(1))
static const int timeout = 100;
int i;
- ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
+ ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
/* give time for command to start being serially clocked into cs5529.
- * this insures that the CSS_ADC_BUSY bit will get properly
+ * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
* set before we exit this function.
*/
for (i = 0; i < timeout; i++) {
- if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
+ if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
+ NI67XX_CAL_STATUS_BUSY)
break;
udelay(1);
}
"timeout or signal in cs5529_do_conversion()\n");
return -ETIME;
}
- status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
- if (status & CSS_OSC_DETECT) {
+ status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
+ if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
dev_err(dev->class_dev,
"cs5529 conversion error, status CSS_OSC_DETECT\n");
return -EIO;
}
- if (status & CSS_OVERRANGE) {
+ if (status & NI67XX_CAL_STATUS_OVERRANGE) {
dev_err(dev->class_dev,
"cs5529 conversion error, overrange (ignoring)\n");
}
if (data) {
- *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
+ *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
/* cs5529 returns 16 bit signed data in bipolar mode */
*data ^= (1 << 15);
}
channel_select = INTERNAL_REF;
else
channel_select = CR_CHAN(insn->chanspec);
- ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
+ ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
for (n = 0; n < insn->n; n++) {
retval = cs5529_do_conversion(dev, &sample);
static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
unsigned int reg_select_bits)
{
- ni_ao_win_outw(dev, ((value >> 16) & 0xff),
- CAL_ADC_Config_Data_High_Word_67xx);
- ni_ao_win_outw(dev, (value & 0xffff),
- CAL_ADC_Config_Data_Low_Word_67xx);
+ ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
+ ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
reg_select_bits &= CS5529_CMD_REG_MASK;
cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
if (cs5529_wait_for_idle(dev))
#define NI6143_RELEASE_DATE_REG 0x54 /* w32 */
#define NI6143_RELEASE_OLDEST_DATE_REG 0x58 /* w32 */
-/* 671x, 611x registers */
-
-/* 671xi, 611x windowed ao registers */
-enum windowed_regs_67xx_61xx {
- AO_Immediate_671x = 0x11, /* W 16 */
- AO_Timed_611x = 0x10, /* W 16 */
- AO_FIFO_Offset_Load_611x = 0x13, /* W32 */
- AO_Later_Single_Point_Updates = 0x14, /* W 16 */
- AO_Waveform_Generation_611x = 0x15, /* W 16 */
- AO_Misc_611x = 0x16, /* W 16 */
- AO_Calibration_Channel_Select_67xx = 0x17, /* W 16 */
- AO_Configuration_2_67xx = 0x18, /* W 16 */
- CAL_ADC_Command_67xx = 0x19, /* W 8 */
- CAL_ADC_Status_67xx = 0x1a, /* R 8 */
- CAL_ADC_Data_67xx = 0x1b, /* R 16 */
- CAL_ADC_Config_Data_High_Word_67xx = 0x1c, /* RW 16 */
- CAL_ADC_Config_Data_Low_Word_67xx = 0x1d, /* RW 16 */
-};
-static inline unsigned int DACx_Direct_Data_671x(int channel)
-{
- return channel;
-}
-
-enum AO_Misc_611x_Bits {
- CLEAR_WG = 1,
-};
+/*
+ * 671x, 611x windowed ao registers
+ */
+#define NI671X_DAC_DIRECT_DATA_REG(x) (0x00 + (x)) /* w16 */
+#define NI611X_AO_TIMED_REG 0x10 /* w16 */
+#define NI671X_AO_IMMEDIATE_REG 0x11 /* w16 */
+#define NI611X_AO_FIFO_OFFSET_LOAD_REG 0x13 /* w32 */
+#define NI67XX_AO_SP_UPDATES_REG 0x14 /* w16 */
+#define NI611X_AO_WAVEFORM_GEN_REG 0x15 /* w16 */
+#define NI611X_AO_MISC_REG 0x16 /* w16 */
+#define NI611X_AO_MISC_CLEAR_WG BIT(0)
+#define NI67XX_AO_CAL_CHAN_SEL_REG 0x17 /* w16 */
+#define NI67XX_AO_CFG2_REG 0x18 /* w16 */
+#define NI67XX_CAL_CMD_REG 0x19 /* w16 */
+#define NI67XX_CAL_STATUS_REG 0x1a /* r8 */
+#define NI67XX_CAL_STATUS_BUSY BIT(0)
+#define NI67XX_CAL_STATUS_OSC_DETECT BIT(1)
+#define NI67XX_CAL_STATUS_OVERRANGE BIT(2)
+#define NI67XX_CAL_DATA_REG 0x1b /* r16 */
+#define NI67XX_CAL_CFG_HI_REG 0x1c /* rw16 */
+#define NI67XX_CAL_CFG_LO_REG 0x1d /* rw16 */
#define CS5529_CMD_CB BIT(7)
#define CS5529_CMD_SINGLE_CONV BIT(6)
#define CS5529_CFG_CALIB_OFFSET_SYS CS5529_CFG_CALIB(5)
#define CS5529_CFG_CALIB_GAIN_SYS CS5529_CFG_CALIB(6)
-enum cs5529_status_bits {
- CSS_ADC_BUSY = 0x1,
- CSS_OSC_DETECT = 0x2, /* indicates adc error */
- CSS_OVERRANGE = 0x4,
-};
-
/*
This is stuff unique to the NI E series drivers,
but I thought I'd put it here anyway.