drm/i915: set default value for config->pixel_multiplier

This way we can simplify the code quite a bit.

Also add a WARN in the sdvo code to complain about a bogus value
and kill the readout code in intel_ddi.c that Jesse sneaked in.
HW state readout for the pixel multiplier will work a bit differently
in the end.

v2: Rebase on top of the fdi pixel mutliplier handling fix.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 486c46bf5ccf74e6b3214fe993e60218774aa81c..224ce25129cef87e042f8c258818cc8d5cf645c6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1279,7 +1279,6 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
                flags |= DRM_MODE_FLAG_NVSYNC;
 
        pipe_config->adjusted_mode.flags |= flags;
-       pipe_config->pixel_multiplier = 1;
 }
 
 static void intel_ddi_destroy(struct drm_encoder *encoder)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 827d7ca2d9d99b941a5e04f9d424c00088286a39..ca90d36fd650c3acd688f9a4ef97930b8ac2c70a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4003,8 +4003,7 @@ retry:
        link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
 
        fdi_dotclock = adjusted_mode->clock;
-       if (pipe_config->pixel_multiplier > 1)
-               fdi_dotclock /= pipe_config->pixel_multiplier;
+       fdi_dotclock /= pipe_config->pixel_multiplier;
 
        lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
                                           pipe_config->pipe_bpp);
@@ -4458,11 +4457,8 @@ static void vlv_update_pll(struct intel_crtc *crtc)
        if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
                DRM_ERROR("DPLL %d failed to lock\n", pipe);
 
-       dpll_md = 0;
-       if (crtc->config.pixel_multiplier > 1) {
-               dpll_md = (crtc->config.pixel_multiplier - 1)
-                       << DPLL_MD_UDI_MULTIPLIER_SHIFT;
-       }
+       dpll_md = (crtc->config.pixel_multiplier - 1)
+               << DPLL_MD_UDI_MULTIPLIER_SHIFT;
        I915_WRITE(DPLL_MD(pipe), dpll_md);
        POSTING_READ(DPLL_MD(pipe));
 
@@ -4496,8 +4492,7 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
        else
                dpll |= DPLLB_MODE_DAC_SERIAL;
 
-       if ((crtc->config.pixel_multiplier > 1) &&
-           (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
+       if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
                dpll |= (crtc->config.pixel_multiplier - 1)
                        << SDVO_MULTIPLIER_SHIFT_HIRES;
        }
@@ -4560,11 +4555,8 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
        udelay(150);
 
        if (INTEL_INFO(dev)->gen >= 4) {
-               u32 dpll_md = 0;
-               if (crtc->config.pixel_multiplier > 1) {
-                       dpll_md = (crtc->config.pixel_multiplier - 1)
-                               << DPLL_MD_UDI_MULTIPLIER_SHIFT;
-               }
+               u32 dpll_md = (crtc->config.pixel_multiplier - 1)
+                       << DPLL_MD_UDI_MULTIPLIER_SHIFT;
                I915_WRITE(DPLL_MD(pipe), dpll_md);
        } else {
                /* The pixel multiplier can only be updated once the
@@ -5613,10 +5605,8 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
        else
                dpll |= DPLLB_MODE_DAC_SERIAL;
 
-       if (intel_crtc->config.pixel_multiplier > 1) {
-               dpll |= (intel_crtc->config.pixel_multiplier - 1)
-                       << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
-       }
+       dpll |= (intel_crtc->config.pixel_multiplier - 1)
+               << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
 
        if (is_sdvo)
                dpll |= DPLL_DVO_HIGH_SPEED;
@@ -7783,8 +7773,9 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
                goto fail;
 
 encoder_retry:
-       /* Ensure the port clock default is reset when retrying. */
+       /* Ensure the port clock defaults are reset when retrying. */
        pipe_config->port_clock = 0;
+       pipe_config->pixel_multiplier = 1;
 
        /* Pass our mode to the connectors and the CRTC to give them a chance to
         * adjust it according to limitations or connector properties, and also

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 7068195376ef0c7ab2a912d08d45ece43d3b488d..f4588a2c65ac4a28f2e03704358a7079e619c5e0 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1219,6 +1219,7 @@ static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
 
        switch (intel_crtc->config.pixel_multiplier) {
        default:
+               WARN(1, "unknown pixel mutlipler specified\n");
        case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
        case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
        case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;