MIPS: Add detection of DSP ASE Revision 2.

[ralf@linux-mips.org: This patch really only detects the ASE and passes its
existence on to userland via /proc/cpuinfo.  The DSP ASE Rev 2. adds new
resources but no resources that would need management by the kernel.]

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4165/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 089125a6ae6a019bcfb051b957a9b4547aea4c0c..c507b931b484c69913fc2aedc1a9a960b2b317d4 100644 (file)
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -171,6 +171,10 @@
 #define cpu_has_dsp            (cpu_data[0].ases & MIPS_ASE_DSP)
 #endif
 
+#ifndef cpu_has_dsp2
+#define cpu_has_dsp2           (cpu_data[0].ases & MIPS_ASE_DSP2P)
+#endif
+
 #ifndef cpu_has_mipsmt
 #define cpu_has_mipsmt         (cpu_data[0].ases & MIPS_ASE_MIPSMT)
 #endif

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 7dc0db8b942609107f8e066c89b461b825ed6c48..52c4e914f95aef97ce72af5fd186678cc7ce9081 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -332,6 +332,7 @@ enum cpu_type_enum {
 #define MIPS_ASE_SMARTMIPS     0x00000008 /* SmartMIPS */
 #define MIPS_ASE_DSP           0x00000010 /* Signal Processing ASE */
 #define MIPS_ASE_MIPSMT                0x00000020 /* CPU supports MIPS MT */
+#define MIPS_ASE_DSP2P         0x00000040 /* Signal Processing ASE Rev 2 */
 
 
 #endif /* _ASM_CPU_H */

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 04d7560dfafb8ac1e02423bea6f9908fc3c076ad..eb742895dcbe97a3e7c81813c76eeec2e41bac02 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -592,6 +592,7 @@
 #define MIPS_CONF3_VEIC                (_ULCAST_(1) <<  6)
 #define MIPS_CONF3_LPA         (_ULCAST_(1) <<  7)
 #define MIPS_CONF3_DSP         (_ULCAST_(1) << 10)
+#define MIPS_CONF3_DSP2P       (_ULCAST_(1) << 11)
 #define MIPS_CONF3_RXI         (_ULCAST_(1) << 12)
 #define MIPS_CONF3_ULRI                (_ULCAST_(1) << 13)
 

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index bd2809698e3927bc9047d260b884ab0361f4475e..b1fb7af3c35058f2e739b4ec41fb28d62d00c2d2 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -142,7 +142,7 @@ int __cpuinitdata mips_dsp_disabled;
 
 static int __init dsp_disable(char *s)
 {
-       cpu_data[0].ases &= ~MIPS_ASE_DSP;
+       cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
        mips_dsp_disabled = 1;
 
        return 1;
@@ -429,6 +429,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
                c->options |= MIPS_CPU_RIXI;
        if (config3 & MIPS_CONF3_DSP)
                c->ases |= MIPS_ASE_DSP;
+       if (config3 & MIPS_CONF3_DSP2P)
+               c->ases |= MIPS_ASE_DSP2P;
        if (config3 & MIPS_CONF3_VINT)
                c->options |= MIPS_CPU_VINT;
        if (config3 & MIPS_CONF3_VEIC)
@@ -1180,7 +1182,7 @@ __cpuinit void cpu_probe(void)
                c->options &= ~MIPS_CPU_FPU;
 
        if (mips_dsp_disabled)
-               c->ases &= ~MIPS_ASE_DSP;
+               c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
 
        if (c->options & MIPS_CPU_FPU) {
                c->fpu_id = cpu_get_fpu_id();

diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 5542817c1b498869cef930f4bd09c7ce680fe130..35cf2094f9aef73edc82550d1a60b0244c78cc74 100644 (file)
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -70,6 +70,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                      cpu_has_mips3d ? " mips3d" : "",
                      cpu_has_smartmips ? " smartmips" : "",
                      cpu_has_dsp ? " dsp" : "",
+                     cpu_has_dsp2 ? " dsp2" : "",
                      cpu_has_mipsmt ? " mt" : ""
                );
        seq_printf(m, "shadow register sets\t: %d\n",