ARM: 5678/1: SSP/SPI PL022 polarity terminology fix

The definition of the SPI clock phase for the Motorola mode of
the PL022 driver was incorrect: the spec had been interpreted as
data being recieved on rising or falling edge of the clocks while
the correct interpretation is that data can be recieved on the
first or second edge transition, falling or rising depending on
the polarity setting.

Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index 307d007ea7f370c6777ada039c75b18c4a63a81c..f0e887bea30e6b18218c2bac2e6c4f1d8a1b50bb 100644 (file)
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -48,7 +48,7 @@ struct pl022_config_chip dummy_chip_info = {
        .data_size = SSP_DATA_BITS_8, /* used to be 12 in some default */
        .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
        .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
-       .clk_phase = SSP_CLK_FALLING_EDGE,
+       .clk_phase = SSP_CLK_SECOND_EDGE,
        .clk_pol = SSP_CLK_POL_IDLE_LOW,
        .ctrl_len = SSP_BITS_12,
        .wait_state = SSP_MWIRE_WAIT_ZERO,

diff --git a/drivers/spi/amba-pl022.c b/drivers/spi/amba-pl022.c
index da76797ce8b9d7791fe82ede26e6ca4bd96b3e57..35521af0d0d7f3b7bf68adabeeb770facede4c3f 100644 (file)
--- a/drivers/spi/amba-pl022.c
+++ b/drivers/spi/amba-pl022.c
@@ -534,7 +534,7 @@ static void restore_state(struct pl022 *pl022)
        GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0)    | \
        GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP, 5) | \
        GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
-       GEN_MASK_BITS(SSP_CLK_FALLING_EDGE, SSP_CR0_MASK_SPH, 7) | \
+       GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
        GEN_MASK_BITS(NMDK_SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
        GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS, 16) | \
        GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 21) \
@@ -1249,8 +1249,8 @@ static int verify_controller_parameters(struct pl022 *pl022,
                return -EINVAL;
        }
        if (chip_info->iface == SSP_INTERFACE_MOTOROLA_SPI) {
-               if ((chip_info->clk_phase != SSP_CLK_RISING_EDGE)
-                   && (chip_info->clk_phase != SSP_CLK_FALLING_EDGE)) {
+               if ((chip_info->clk_phase != SSP_CLK_FIRST_EDGE)
+                   && (chip_info->clk_phase != SSP_CLK_SECOND_EDGE)) {
                        dev_err(chip_info->dev,
                                "Clock Phase is configured incorrectly\n");
                        return -EINVAL;
@@ -1487,7 +1487,7 @@ static int pl022_setup(struct spi_device *spi)
                chip_info->data_size = SSP_DATA_BITS_12;
                chip_info->rx_lev_trig = SSP_RX_1_OR_MORE_ELEM;
                chip_info->tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC;
-               chip_info->clk_phase = SSP_CLK_FALLING_EDGE;
+               chip_info->clk_phase = SSP_CLK_SECOND_EDGE;
                chip_info->clk_pol = SSP_CLK_POL_IDLE_LOW;
                chip_info->ctrl_len = SSP_BITS_8;
                chip_info->wait_state = SSP_MWIRE_WAIT_ZERO;

diff --git a/include/linux/amba/pl022.h b/include/linux/amba/pl022.h
index dcad0ffd17550d6937944981cac9b7a940e233cc..e4836c6b3dd75bc925e1d530704cb8834633bb35 100644 (file)
--- a/include/linux/amba/pl022.h
+++ b/include/linux/amba/pl022.h
@@ -136,12 +136,12 @@ enum ssp_tx_level_trig {
 
 /**
  * enum SPI Clock Phase - clock phase (Motorola SPI interface only)
- * @SSP_CLK_RISING_EDGE: Receive data on rising edge
- * @SSP_CLK_FALLING_EDGE: Receive data on falling edge
+ * @SSP_CLK_FIRST_EDGE: Receive data on first edge transition (actual direction depends on polarity)
+ * @SSP_CLK_SECOND_EDGE: Receive data on second edge transition (actual direction depends on polarity)
  */
 enum ssp_spi_clk_phase {
-       SSP_CLK_RISING_EDGE,
-       SSP_CLK_FALLING_EDGE
+       SSP_CLK_FIRST_EDGE,
+       SSP_CLK_SECOND_EDGE
 };
 
 /**