pwm: sunxi: document OF bindings
authorAlexandre Belloni <alexandre.belloni@free-electrons.com>
Wed, 17 Dec 2014 21:15:40 +0000 (22:15 +0100)
committerThierry Reding <thierry.reding@gmail.com>
Fri, 30 Jan 2015 11:16:02 +0000 (12:16 +0100)
This is the documentation for the Allwinner SoCs PWM bindings.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Documentation/devicetree/bindings/pwm/pwm-sun4i.txt [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt b/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt
new file mode 100644 (file)
index 0000000..ae0273e
--- /dev/null
@@ -0,0 +1,20 @@
+Allwinner sun4i and sun7i SoC PWM controller
+
+Required properties:
+  - compatible: should be one of:
+    - "allwinner,sun4i-a10-pwm"
+    - "allwinner,sun7i-a20-pwm"
+  - reg: physical base address and length of the controller's registers
+  - #pwm-cells: should be 3. See pwm.txt in this directory for a description of
+    the cells format.
+  - clocks: From common clock binding, handle to the parent clock.
+
+Example:
+
+       pwm: pwm@01c20e00 {
+               compatible = "allwinner,sun7i-a20-pwm";
+               reg = <0x01c20e00 0xc>;
+               clocks = <&osc24M>;
+               #pwm-cells = <3>;
+               status = "disabled";
+       };