IXP4xx: Extend PCI MMIO indirect address space to 1 GB.

IXP4xx CPUs can indirectly access the whole 4 GB PCI MMIO address space (using
the non-prefetch registers). Previously the available space depended on the CPU
variant, since one of the IXP43x platforms needed more than the usual 128 MB.
1 GB should be enough for everyone, and if not, we can trivially increase it.

Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>

diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 264f4d59f898158bdd0175ed9ccf17b1fb3392ef..9e5070da17ae8f2d6033eeb0c43adc7127a3b992 100644 (file)
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -179,21 +179,21 @@ config IXP4XX_INDIRECT_PCI
        help
           IXP4xx provides two methods of accessing PCI memory space:
 
-          1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
+          1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
              To access PCI via this space, we simply ioremap() the BAR
              into the kernel and we can use the standard read[bwl]/write[bwl]
              macros. This is the preferred method due to speed but it
-             limits the system to just 64MB of PCI memory. This can be 
+             limits the system to just 64MB of PCI memory. This can be
              problematic if using video cards and other memory-heavy devices.
-          
-          2) If > 64MB of memory space is required, the IXP4xx can be 
-            configured to use indirect registers to access PCI This allows 
-            for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. 
-            The disadvantage of this is that every PCI access requires 
-            three local register accesses plus a spinlock, but in some 
-            cases the performance hit is acceptable. In addition, you cannot 
-            mmap() PCI devices in this case due to the indirect nature
-            of the PCI window.
+
+         2) If > 64MB of memory space is required, the IXP4xx can be
+            configured to use indirect registers to access the whole PCI
+            memory space. This currently allows for up to 1 GB (0x10000000
+            to 0x4FFFFFFF) of memory on the bus. The disadvantage of this
+            is that every PCI access requires three local register accesses
+            plus a spinlock, but in some cases the performance hit is
+            acceptable. In addition, you cannot mmap() PCI devices in this
+            case due to the indirect nature of the PCI window.
 
          By default, the direct method is used. Choose this option if you
          need to use the indirect method instead. If you don't know

diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 70afcfe5b8810943012ee5ee394ccea404f63ce0..c4a01594c761bf380c7b0ac8e8469ce2d1aad6f2 100644 (file)
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -481,11 +481,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
 
        res[1].name = "PCI Memory Space";
        res[1].start = PCIBIOS_MIN_MEM;
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-       res[1].end = 0x4bffffff;
-#else
-       res[1].end = 0x4fffffff;
-#endif
+       res[1].end = PCIBIOS_MAX_MEM;
        res[1].flags = IORESOURCE_MEM;
 
        request_resource(&ioport_resource, &res[0]);

diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
index f58a43a2396638bc315d3e8444472272f61c1353..f822b223b7e00f52480d21ff0d85f338622a6e56 100644 (file)
--- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
+++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
@@ -18,7 +18,13 @@
 #define __ASM_ARCH_HARDWARE_H__
 
 #define PCIBIOS_MIN_IO         0x00001000
-#define PCIBIOS_MIN_MEM                (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
+#ifdef CONFIG_IXP4XX_INDIRECT_PCI
+#define PCIBIOS_MIN_MEM                0x10000000 /* 1 GB of indirect PCI MMIO space */
+#define PCIBIOS_MAX_MEM                0x4FFFFFFF
+#else
+#define PCIBIOS_MIN_MEM                0x48000000 /* 64 MB of PCI MMIO space */
+#define PCIBIOS_MAX_MEM                0x4BFFFFFF
+#endif
 
 /*
  * We override the standard dma-mask routines for bouncing.

diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index 0e601fe50162bebed52dc0bd8e35863ad2e60c0f..6ea7e2fb2701b755830d4285da7266bec3591c04 100644 (file)
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -26,22 +26,20 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
 /*
  * IXP4xx provides two methods of accessing PCI memory space:
  *
- * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
+ * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
  *    To access PCI via this space, we simply ioremap() the BAR
  *    into the kernel and we can use the standard read[bwl]/write[bwl]
  *    macros. This is the preffered method due to speed but it
- *    limits the system to just 64MB of PCI memory. This can be 
- *    problamatic if using video cards and other memory-heavy
- *    targets.
- *
- * 2) If > 64MB of memory space is required, the IXP4xx can be configured
- *    to use indirect registers to access PCI (as we do below for I/O
- *    transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
- *    of memory on the bus. The disadvantage of this is that every 
- *    PCI access requires three local register accesses plus a spinlock,
- *    but in some cases the performance hit is acceptable. In addition,
- *    you cannot mmap() PCI devices in this case.
+ *    limits the system to just 64MB of PCI memory. This can be
+ *    problematic if using video cards and other memory-heavy targets.
  *
+ * 2) If > 64MB of memory space is required, the IXP4xx can use indirect
+ *    registers to access the whole 4 GB of PCI memory space (as we do below
+ *    for I/O transactions). This allows currently for up to 1 GB (0x10000000
+ *    to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that
+ *    every PCI access requires three local register accesses plus a spinlock,
+ *    but in some cases the performance hit is acceptable. In addition, you
+ *    cannot mmap() PCI devices in this case.
  */
 #ifndef        CONFIG_IXP4XX_INDIRECT_PCI