ARM: dts: sun6i: Add GMAC clock node to the A31 dtsi
authorChen-Yu Tsai <wens@csie.org>
Tue, 15 Jul 2014 17:15:44 +0000 (01:15 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Fri, 18 Jul 2014 20:36:29 +0000 (22:36 +0200)
The GMAC uses 1 of 2 sources for its transmit clock, depending on the
PHY interface mode. Add both sources as dummy clocks, and as parents
to the GMAC clock node.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
arch/arm/boot/dts/sun6i-a31.dtsi

index 47e143aa82fefe11b5f2e49d607bb86da6962381..b78a5aa4bcccdbb67c1b51817540417bb3536e54 100644 (file)
                                             "usb_ohci0", "usb_ohci1",
                                             "usb_ohci2";
                };
+
+               /*
+                * The following two are dummy clocks, placeholders used in the gmac_tx
+                * clock. The gmac driver will choose one parent depending on the PHY
+                * interface mode, using clk_set_rate auto-reparenting.
+                * The actual TX clock rate is not controlled by the gmac_tx clock.
+                */
+               mii_phy_tx_clk: clk@1 {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <25000000>;
+                       clock-output-names = "mii_phy_tx";
+               };
+
+               gmac_int_tx_clk: clk@2 {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <125000000>;
+                       clock-output-names = "gmac_int_tx";
+               };
+
+               gmac_tx_clk: clk@01c200d0 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun7i-a20-gmac-clk";
+                       reg = <0x01c200d0 0x4>;
+                       clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+                       clock-output-names = "gmac_tx";
+               };
        };
 
        soc@01c00000 {