sh: Centralize the CPU cache initialization routines.

This provides a central point for CPU cache initialization routines.
This replaces the antiquated p3_cache_init() method, which the vast
majority of CPUs never cared about.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h
index 9ec13fb909ddbbc6a973cbee768f552cc1728e89..e37654f7f54552f6ff84e06c2a0dd09a46750be8 100644 (file)
--- a/arch/sh/include/asm/cacheflush.h
+++ b/arch/sh/include/asm/cacheflush.h
@@ -12,7 +12,6 @@
  *
  * See arch/sh/kernel/cpu/init.c:cache_init().
  */
-#define p3_cache_init()                                do { } while (0)
 #define flush_cache_all()                      do { } while (0)
 #define flush_cache_mm(mm)                     do { } while (0)
 #define flush_cache_dup_mm(mm)                 do { } while (0)
@@ -78,5 +77,7 @@ void kunmap_coherent(void);
 
 #define PG_dcache_dirty        PG_arch_1
 
+void cpu_cache_init(void);
+
 #endif /* __KERNEL__ */
 #endif /* __ASM_SH_CACHEFLUSH_H */

diff --git a/arch/sh/include/cpu-common/cpu/cacheflush.h b/arch/sh/include/cpu-common/cpu/cacheflush.h
index c3db00b73605c77411e64da6469e5356184af6ff..0c38278509cb3533f2e45e77019e81c909371d61 100644 (file)
--- a/arch/sh/include/cpu-common/cpu/cacheflush.h
+++ b/arch/sh/include/cpu-common/cpu/cacheflush.h
@@ -39,6 +39,4 @@
 #define flush_icache_user_range(vma,pg,adr,len)        do { } while (0)
 #define flush_cache_sigtramp(vaddr)            do { } while (0)
 
-#define p3_cache_init()                                do { } while (0)
-
 #endif /* __ASM_CPU_SH2_CACHEFLUSH_H */

diff --git a/arch/sh/include/cpu-sh2a/cpu/cacheflush.h b/arch/sh/include/cpu-sh2a/cpu/cacheflush.h
index 3d3b9205d2acc80850aabbf221ef0bea56242e13..b9eaa19325e205f666b0eba5434c6364490d72af 100644 (file)
--- a/arch/sh/include/cpu-sh2a/cpu/cacheflush.h
+++ b/arch/sh/include/cpu-sh2a/cpu/cacheflush.h
@@ -30,5 +30,4 @@ void flush_icache_range(unsigned long start, unsigned long end);
 #define flush_icache_user_range(vma,pg,adr,len)        do { } while (0)
 #define flush_cache_sigtramp(vaddr)            do { } while (0)
 
-#define p3_cache_init()                                do { } while (0)
 #endif /* __ASM_CPU_SH2A_CACHEFLUSH_H */

diff --git a/arch/sh/include/cpu-sh3/cpu/cacheflush.h b/arch/sh/include/cpu-sh3/cpu/cacheflush.h
index 3b5f3df4e1c8a169b3e23000214ec27d995d75d7..cf656a093770aba30831bcc0291d9082ffa062f4 100644 (file)
--- a/arch/sh/include/cpu-sh3/cpu/cacheflush.h
+++ b/arch/sh/include/cpu-sh3/cpu/cacheflush.h
@@ -32,8 +32,6 @@ void flush_icache_page(struct vm_area_struct *vma, struct page *page);
 #define flush_cache_sigtramp(vaddr)            do { } while (0)
 #define flush_icache_user_range(vma,pg,adr,len)        do { } while (0)
 
-#define p3_cache_init()                                do { } while (0)
-
 #else
 #include <cpu-common/cpu/cacheflush.h>
 #endif

diff --git a/arch/sh/include/cpu-sh4/cpu/cacheflush.h b/arch/sh/include/cpu-sh4/cpu/cacheflush.h
index 76764f0fb88aefe34de3ba9b3abf9e5148171730..a28c542f5179d1a2027eba29a73393f8ab662208 100644 (file)
--- a/arch/sh/include/cpu-sh4/cpu/cacheflush.h
+++ b/arch/sh/include/cpu-sh4/cpu/cacheflush.h
@@ -35,7 +35,4 @@ void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
 
 #define flush_icache_page(vma,pg)              do { } while (0)
 
-/* Initialization of P3 area for copy_user_page */
-void p3_cache_init(void);
-
 #endif /* __ASM_CPU_SH4_CACHEFLUSH_H */

diff --git a/arch/sh/include/cpu-sh5/cpu/cacheflush.h b/arch/sh/include/cpu-sh5/cpu/cacheflush.h
index 5a11f0b7e66a9b5b4fbe53d22950b096003ef2d0..8350cc7ed1c5dbb01578073c95f251e6a0cabde0 100644 (file)
--- a/arch/sh/include/cpu-sh5/cpu/cacheflush.h
+++ b/arch/sh/include/cpu-sh5/cpu/cacheflush.h
@@ -25,7 +25,6 @@ extern void flush_icache_user_range(struct vm_area_struct *vma,
 #define flush_dcache_mmap_unlock(mapping)      do { } while (0)
 
 #define flush_icache_page(vma, page)   do { } while (0)
-void p3_cache_init(void);
 
 #endif /* __ASSEMBLY__ */
 

diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 92f87a460a81e0c9c970d1877284140216cc804e..df2eb87f1524d7c81e0e2215668c5a56e7d88742 100644 (file)
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -94,7 +94,7 @@ static void __init emit_cache_params(void)
 /*
  * SH-4 has virtually indexed and physically tagged cache.
  */
-void __init p3_cache_init(void)
+void __init sh4_cache_init(void)
 {
        compute_alias(&boot_cpu_data.icache);
        compute_alias(&boot_cpu_data.dcache);

diff --git a/arch/sh/mm/cache-sh5.c b/arch/sh/mm/cache-sh5.c
index 28f3c8fb1b9964ebdd1cc749e8adb80a10e86fb7..576cad04b11b79016f1bf4a534b194eec68a4b3a 100644 (file)
--- a/arch/sh/mm/cache-sh5.c
+++ b/arch/sh/mm/cache-sh5.c
@@ -23,7 +23,7 @@
 /* Wired TLB entry for the D-cache */
 static unsigned long long dtlb_cache_slot;
 
-void __init p3_cache_init(void)
+void __init cpu_cache_init(void)
 {
        /* Reserve a slot for dcache colouring in the DTLB */
        dtlb_cache_slot = sh64_get_wired_dtlb_entry();

diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c
index f51d0a4eb3ba78c43676555be39a2f54738a2be2..659981ffae2418304c749cd17cd1bc0b61748517 100644 (file)
--- a/arch/sh/mm/cache.c
+++ b/arch/sh/mm/cache.c
@@ -127,3 +127,14 @@ void __flush_anon_page(struct page *page, unsigned long vmaddr)
                        __flush_wback_region((void *)addr, PAGE_SIZE);
        }
 }
+
+void __init cpu_cache_init(void)
+{
+       if ((boot_cpu_data.family == CPU_FAMILY_SH4) ||
+           (boot_cpu_data.family == CPU_FAMILY_SH4A) ||
+           (boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) {
+               extern void __weak sh4_cache_init(void);
+
+               sh4_cache_init();
+       }
+}

diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index fe532aeaa16d9a9861eddd7665a2f9c49358337f..cf0e9c5146b107bf1af4929edc948890246bb51d 100644 (file)
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -230,7 +230,7 @@ void __init mem_init(void)
                datasize >> 10,
                initsize >> 10);
 
-       p3_cache_init();
+       cpu_cache_init();
 
        /* Initialize the vDSO */
        vsyscall_init();