ARM: dts: exynos: Add UART2 DT node for Exynos3250 SoC
authorPankaj Dubey <pankaj.dubey@samsung.com>
Thu, 31 Mar 2016 02:48:01 +0000 (11:48 +0900)
committerKrzysztof Kozlowski <k.kozlowski@samsung.com>
Fri, 1 Apr 2016 00:20:53 +0000 (09:20 +0900)
This patch add the UART2 Device Tree node for Exynos3250 SoC.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
arch/arm/boot/dts/exynos3250-pinctrl.dtsi
arch/arm/boot/dts/exynos3250.dtsi

index ecf79386e891ba9298cc1a64b1d98d44e1c83e55..54c587f2726596b7597896871936747472f32428 100644 (file)
                samsung,pin-drv = <0>;
        };
 
+       uart2_data: uart2-data {
+               samsung,pins = "gpa1-0", "gpa1-1";
+               samsung,pin-function = <2>;
+               samsung,pin-pud = <0>;
+               samsung,pin-drv = <0>;
+       };
+
        i2c3_bus: i2c3-bus {
                samsung,pins = "gpa1-2", "gpa1-3";
                samsung,pin-function = <3>;
index 137f9015d4e87a89ed30732a70bd5bd5c134a6cf..030ce800f748119f82464a9523172715172376ae 100644 (file)
@@ -43,6 +43,7 @@
                i2c7 = &i2c_7;
                serial0 = &serial_0;
                serial1 = &serial_1;
+               serial2 = &serial_2;
        };
 
        cpus {
                        status = "disabled";
                };
 
+               serial_2: serial@13820000 {
+                       compatible = "samsung,exynos4210-uart";
+                       reg = <0x13820000 0x100>;
+                       interrupts = <0 111 0>;
+                       clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
+                       clock-names = "uart", "clk_uart_baud0";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart2_data>;
+                       status = "disabled";
+               };
+
                i2c_0: i2c@13860000 {
                        #address-cells = <1>;
                        #size-cells = <0>;