drm/nvc0/pfifo: support for chipsets with only one PSUBFIFO (0xc1)

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nvc0_fifo.c b/drivers/gpu/drm/nouveau/nvc0_fifo.c
index 82a4ded5dae82330942a0f869fa4a5610a0d2a09..e6f92c541dba47b1b4d8bbf6a3431c4c5ccb13fb 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvc0_fifo.c
+++ b/drivers/gpu/drm/nouveau/nvc0_fifo.c
@@ -33,6 +33,7 @@ struct nvc0_fifo_priv {
        struct nouveau_gpuobj *playlist[2];
        int cur_playlist;
        struct nouveau_vma user_vma;
+       int spoon_nr;
 };
 
 struct nvc0_fifo_chan {
@@ -324,13 +325,18 @@ nvc0_fifo_init(struct drm_device *dev)
        nv_wr32(dev, 0x000204, 0xffffffff);
        nv_wr32(dev, 0x002204, 0xffffffff);
 
+       priv->spoon_nr = hweight32(nv_rd32(dev, 0x002204));
+       NV_DEBUG(dev, "PFIFO: %d subfifo(s)\n", priv->spoon_nr);
+
        /* assign engines to subfifos */
-       nv_wr32(dev, 0x002208, ~(1 << 0)); /* PGRAPH */
-       nv_wr32(dev, 0x00220c, ~(1 << 1)); /* PVP */
-       nv_wr32(dev, 0x002210, ~(1 << 1)); /* PPP */
-       nv_wr32(dev, 0x002214, ~(1 << 1)); /* PBSP */
-       nv_wr32(dev, 0x002218, ~(1 << 2)); /* PCE0 */
-       nv_wr32(dev, 0x00221c, ~(1 << 1)); /* PCE1 */
+       if (priv->spoon_nr >= 3) {
+               nv_wr32(dev, 0x002208, ~(1 << 0)); /* PGRAPH */
+               nv_wr32(dev, 0x00220c, ~(1 << 1)); /* PVP */
+               nv_wr32(dev, 0x002210, ~(1 << 1)); /* PPP */
+               nv_wr32(dev, 0x002214, ~(1 << 1)); /* PBSP */
+               nv_wr32(dev, 0x002218, ~(1 << 2)); /* PCE0 */
+               nv_wr32(dev, 0x00221c, ~(1 << 1)); /* PCE1 */
+       }
 
        /* PSUBFIFO[n] */
        for (i = 0; i < 3; i++) {