projects
/
GitHub
/
mt8127
/
android_kernel_alcatel_ttab.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
126336f
)
MIPS: Add Cavium OCTEON slot into proper tlb category.
author
David Daney
<ddaney@caviumnetworks.com>
Thu, 11 Dec 2008 23:33:35 +0000
(15:33 -0800)
committer
Ralf Baechle
<ralf@linux-mips.org>
Sun, 11 Jan 2009 09:57:24 +0000
(09:57 +0000)
Expand the case statement for build_tlb_write_entry so that it does
the right thing on Cavium CPU variants.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mm/tlbex.c
patch
|
blob
|
blame
|
history
diff --git
a/arch/mips/mm/tlbex.c
b/arch/mips/mm/tlbex.c
index 979cf9197282ca1f315a0ca8430da4d527332cd8..42942038d0fd4daa4a3a7a4be7fcabe43d014fa0 100644
(file)
--- a/
arch/mips/mm/tlbex.c
+++ b/
arch/mips/mm/tlbex.c
@@
-317,6
+317,7
@@
static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_BCM3302:
case CPU_BCM4710:
case CPU_LOONGSON2:
+ case CPU_CAVIUM_OCTEON:
if (m4kc_tlbp_war())
uasm_i_nop(p);
tlbw(p);