ARM: OMAP2+: Remove hardcoded IRQs and enable SPARSE_IRQ

Remove hardcoded IRQs in irqs.h and related files as these
are no longer needed.

Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 7e60a69bfe612e2d1baff7881873262dc2ab8200..4cdb08c8ab52df8636a509c724c8607801ccced4 100644 (file)
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -26,12 +26,13 @@
 #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
 #ifndef __ASSEMBLER__
 
+#include <linux/irq.h>
 #include <linux/delay.h>
 #include <linux/i2c/twl.h>
 #include <plat/common.h>
 #include <asm/proc-fns.h>
 
-#define OMAP_INTC_START                0
+#define OMAP_INTC_START                NR_IRQS
 
 #ifdef CONFIG_SOC_OMAP2420
 extern void omap242x_map_common_io(void);

diff --git a/arch/arm/mach-omap2/include/mach/irqs.h b/arch/arm/mach-omap2/include/mach/irqs.h
index 44dab7725696b5348bd36c7d7fc77417434c0794..ba5282cafa420131d423c0f31368d729cc420fd5 100644 (file)
--- a/arch/arm/mach-omap2/include/mach/irqs.h
+++ b/arch/arm/mach-omap2/include/mach/irqs.h
@@ -1,5 +1,3 @@
 /*
  * arch/arm/mach-omap2/include/mach/irqs.h
  */
-
-#include <plat/irqs.h>

diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index dd36eba9506c85877d91e57d2d95894343199d7d..d15a4a6d614698291a058a5a72710fb4f7184d21 100644 (file)
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -25,6 +25,7 @@ config ARCH_OMAP2PLUS
        bool "TI OMAP2/3/4"
        select CLKDEV_LOOKUP
        select GENERIC_IRQ_CHIP
+       select SPARSE_IRQ
        select OMAP_DM_TIMER
        select USE_OF
        select PROC_DEVICETREE if PROC_FS

diff --git a/arch/arm/plat-omap/include/plat/irqs-44xx.h b/arch/arm/plat-omap/include/plat/irqs-44xx.h
deleted file mode 100644 (file)
index 518322c..0000000
--- a/arch/arm/plat-omap/include/plat/irqs-44xx.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * OMAP4 Interrupt lines definitions
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Santosh Shilimkar (santosh.shilimkar@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
-#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
-
-/* OMAP44XX IRQs numbers definitions */
-#define OMAP44XX_IRQ_LOCALTIMER                        29
-#define OMAP44XX_IRQ_LOCALWDT                  30
-
-#define OMAP44XX_IRQ_GIC_START                 32
-
-#define OMAP44XX_IRQ_PL310                     (0 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CTI0                      (1 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CTI1                      (2 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ELM                       (4 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SYS_1N                    (7 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SECURITY_EVENTS           (8 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_L3_DBG                    (9 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_L3_APP                    (10 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_PRCM                      (11 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_0                    (12 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_1                    (13 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_2                    (14 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_3                    (15 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP4                    (16 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP1                    (17 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_MCU                    (18 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_CORE                   (19 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPMC                      (20 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GFX                       (21 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP2                    (22 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP3                    (23 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ISS_5                     (24 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DISPC                 (25 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MAIL_U0                   (26 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_C2C_SSCM_0                        (27 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_TESLA_MMU                 (28 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO1                     (29 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO2                     (30 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO3                     (31 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO4                     (32 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO5                     (33 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO6                     (34 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_USIM                      (35 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_WDT3                      (36 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT1                      (37 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT2                      (38 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT3                      (39 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT4                      (40 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT5                      (41 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT6                      (42 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT7                      (43 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT8                      (44 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT9                      (45 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT10                     (46 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT11                     (47 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI4                      (48 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SHA1_S                    (49 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FPKA_SINTREQUEST_S                (50 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SHA1_P                    (51 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_RNG                       (52 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DSI1                  (53 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C1                      (56 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C2                      (57 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HDQ                       (58 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC5                      (59 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C3                      (61 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C4                      (62 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES2_S                    (63 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES2_P                    (64 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI1                      (65 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI2                      (66 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_P1                    (67 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_P2                    (68 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FDIF_3                    (69 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART4                     (70 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_DMA                   (71 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART1                     (72 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART2                     (73 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART3                     (74 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_PBIAS                     (75 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_OHCI                      (76 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EHCI                      (77 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_TLL                       (78 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES1_S                    (79 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_WDT2                      (80 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DES_S                     (81 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DES_P                     (82 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC1                      (83 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DSI2                  (84 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES1_P                    (85 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC2                      (86 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MPU_ICR                   (87 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_C2C_SSCM_1                        (88 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FSUSB                     (89 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FSUSB_SMI                 (90 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI3                      (91 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HS_USB_MC_N               (92 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HS_USB_DMA_N              (93 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC3                      (94 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT12                     (95 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC4                      (96 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SLIMBUS1                  (97 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SLIMBUS2                  (98 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ABE                       (99 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DUCATI_MMU                        (100 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_HDMI                  (101 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_IVA                    (102 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1    (103 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0    (104 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0     (107 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCASP1_AR                 (108 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCASP1_AX                 (109 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EMIF4_1                   (110 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EMIF4_2                   (111 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCPDM                     (112 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DMM                       (113 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DMIC                      (114 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_0                    (115 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_1                    (116 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_2                    (117 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_3                    (118 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SYS_2N                    (119 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_KBD_CTL                   (120 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UNIPRO1                   (124 + OMAP44XX_IRQ_GIC_START)
-
-#endif

diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index fc3959cdac314a66db71b6027bd04a902d7c6fb5..729992d7d26a871cf237d08378d13ff383f102c2 100644 (file)
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -28,9 +28,6 @@
 #ifndef __ASM_ARCH_OMAP15XX_IRQS_H
 #define __ASM_ARCH_OMAP15XX_IRQS_H
 
-/* All OMAP4 specific defines are moved to irqs-44xx.h */
-#include "irqs-44xx.h"
-
 /*
  * IRQ numbers for interrupt handler 1
  *
@@ -242,125 +239,6 @@
 #define INT_7XX_DMA_CH15       (62 + IH2_BASE)
 #define INT_7XX_NAND           (63 + IH2_BASE)
 
-#define INT_24XX_SYS_NIRQ      7
-#define INT_24XX_SDMA_IRQ0     12
-#define INT_24XX_SDMA_IRQ1     13
-#define INT_24XX_SDMA_IRQ2     14
-#define INT_24XX_SDMA_IRQ3     15
-#define INT_24XX_CAM_IRQ       24
-#define INT_24XX_DSS_IRQ       25
-#define INT_24XX_MAIL_U0_MPU   26
-#define INT_24XX_DSP_UMA       27
-#define INT_24XX_DSP_MMU       28
-#define INT_24XX_GPIO_BANK1    29
-#define INT_24XX_GPIO_BANK2    30
-#define INT_24XX_GPIO_BANK3    31
-#define INT_24XX_GPIO_BANK4    32
-#define INT_24XX_GPIO_BANK5    33
-#define INT_24XX_MAIL_U3_MPU   34
-#define INT_24XX_GPTIMER1      37
-#define INT_24XX_GPTIMER2      38
-#define INT_24XX_GPTIMER3      39
-#define INT_24XX_GPTIMER4      40
-#define INT_24XX_GPTIMER5      41
-#define INT_24XX_GPTIMER6      42
-#define INT_24XX_GPTIMER7      43
-#define INT_24XX_GPTIMER8      44
-#define INT_24XX_GPTIMER9      45
-#define INT_24XX_GPTIMER10     46
-#define INT_24XX_GPTIMER11     47
-#define INT_24XX_GPTIMER12     48
-#define INT_24XX_SHA1MD5       51
-#define INT_24XX_MCBSP4_IRQ_TX 54
-#define INT_24XX_MCBSP4_IRQ_RX 55
-#define INT_24XX_I2C1_IRQ      56
-#define INT_24XX_I2C2_IRQ      57
-#define INT_24XX_HDQ_IRQ       58
-#define INT_24XX_MCBSP1_IRQ_TX 59
-#define INT_24XX_MCBSP1_IRQ_RX 60
-#define INT_24XX_MCBSP2_IRQ_TX 62
-#define INT_24XX_MCBSP2_IRQ_RX 63
-#define INT_24XX_SPI1_IRQ      65
-#define INT_24XX_SPI2_IRQ      66
-#define INT_24XX_UART1_IRQ     72
-#define INT_24XX_UART2_IRQ     73
-#define INT_24XX_UART3_IRQ     74
-#define INT_24XX_USB_IRQ_GEN   75
-#define INT_24XX_USB_IRQ_NISO  76
-#define INT_24XX_USB_IRQ_ISO   77
-#define INT_24XX_USB_IRQ_HGEN  78
-#define INT_24XX_USB_IRQ_HSOF  79
-#define INT_24XX_USB_IRQ_OTG   80
-#define INT_24XX_MCBSP5_IRQ_TX 81
-#define INT_24XX_MCBSP5_IRQ_RX 82
-#define INT_24XX_MMC_IRQ       83
-#define INT_24XX_MMC2_IRQ      86
-#define INT_24XX_MCBSP3_IRQ_TX 89
-#define INT_24XX_MCBSP3_IRQ_RX 90
-#define INT_24XX_SPI3_IRQ      91
-
-#define INT_243X_MCBSP2_IRQ    16
-#define INT_243X_MCBSP3_IRQ    17
-#define INT_243X_MCBSP4_IRQ    18
-#define INT_243X_MCBSP5_IRQ    19
-#define INT_243X_MCBSP1_IRQ    64
-#define INT_243X_HS_USB_MC     92
-#define INT_243X_HS_USB_DMA    93
-#define INT_243X_CARKIT_IRQ    94
-
-#define INT_34XX_BENCH_MPU_EMUL        3
-#define INT_34XX_ST_MCBSP2_IRQ 4
-#define INT_34XX_ST_MCBSP3_IRQ 5
-#define INT_34XX_SSM_ABORT_IRQ 6
-#define INT_34XX_SYS_NIRQ      7
-#define INT_34XX_D2D_FW_IRQ    8
-#define INT_34XX_L3_DBG_IRQ     9
-#define INT_34XX_L3_APP_IRQ     10
-#define INT_34XX_PRCM_MPU_IRQ  11
-#define INT_34XX_MCBSP1_IRQ    16
-#define INT_34XX_MCBSP2_IRQ    17
-#define INT_34XX_GPMC_IRQ      20
-#define INT_34XX_MCBSP3_IRQ    22
-#define INT_34XX_MCBSP4_IRQ    23
-#define INT_34XX_CAM_IRQ       24
-#define INT_34XX_MCBSP5_IRQ    27
-#define INT_34XX_GPIO_BANK1    29
-#define INT_34XX_GPIO_BANK2    30
-#define INT_34XX_GPIO_BANK3    31
-#define INT_34XX_GPIO_BANK4    32
-#define INT_34XX_GPIO_BANK5    33
-#define INT_34XX_GPIO_BANK6    34
-#define INT_34XX_USIM_IRQ      35
-#define INT_34XX_WDT3_IRQ      36
-#define INT_34XX_SPI4_IRQ      48
-#define INT_34XX_SHA1MD52_IRQ  49
-#define INT_34XX_FPKA_READY_IRQ        50
-#define INT_34XX_SHA1MD51_IRQ  51
-#define INT_34XX_RNG_IRQ       52
-#define INT_34XX_I2C3_IRQ      61
-#define INT_34XX_FPKA_ERROR_IRQ        64
-#define INT_34XX_PBIAS_IRQ     75
-#define INT_34XX_OHCI_IRQ      76
-#define INT_34XX_EHCI_IRQ      77
-#define INT_34XX_TLL_IRQ       78
-#define INT_34XX_PARTHASH_IRQ  79
-#define INT_34XX_MMC3_IRQ      94
-#define INT_34XX_GPT12_IRQ     95
-
-#define INT_36XX_UART4_IRQ     80
-
-#define INT_35XX_HECC0_IRQ             24
-#define INT_35XX_HECC1_IRQ             28
-#define INT_35XX_EMAC_C0_RXTHRESH_IRQ  67
-#define INT_35XX_EMAC_C0_RX_PULSE_IRQ  68
-#define INT_35XX_EMAC_C0_TX_PULSE_IRQ  69
-#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ        70
-#define INT_35XX_USBOTG_IRQ            71
-#define INT_35XX_UART4_IRQ             84
-#define INT_35XX_CCDC_VD0_IRQ          88
-#define INT_35XX_CCDC_VD1_IRQ          92
-#define INT_35XX_CCDC_VD2_IRQ          93
-
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
  * 16 MPUIO lines */
 #define OMAP_MAX_GPIO_LINES    192
@@ -377,66 +255,7 @@
 #endif
 #define OMAP_FPGA_IRQ_END      (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
 
-/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
-#define        TWL4030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
-#ifdef CONFIG_TWL4030_CORE
-#define        TWL4030_BASE_NR_IRQS    8
-#define        TWL4030_PWR_NR_IRQS     8
-#else
-#define        TWL4030_BASE_NR_IRQS    0
-#define        TWL4030_PWR_NR_IRQS     0
-#endif
-#define TWL4030_IRQ_END                (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
-#define TWL4030_PWR_IRQ_BASE   TWL4030_IRQ_END
-#define        TWL4030_PWR_IRQ_END     (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
-
-/* External TWL4030 gpio interrupts are optional */
-#define TWL4030_GPIO_IRQ_BASE  TWL4030_PWR_IRQ_END
-#ifdef CONFIG_GPIO_TWL4030
-#define TWL4030_GPIO_NR_IRQS   18
-#else
-#define        TWL4030_GPIO_NR_IRQS    0
-#endif
-#define TWL4030_GPIO_IRQ_END   (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
-
-#define        TWL6030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
-#ifdef CONFIG_TWL4030_CORE
-#define        TWL6030_BASE_NR_IRQS    20
-#else
-#define        TWL6030_BASE_NR_IRQS    0
-#endif
-#define TWL6030_IRQ_END                (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
-
-#define TWL6040_CODEC_IRQ_BASE TWL6030_IRQ_END
-#ifdef CONFIG_TWL6040_CODEC
-#define TWL6040_CODEC_NR_IRQS  6
-#else
-#define TWL6040_CODEC_NR_IRQS  0
-#endif
-#define TWL6040_CODEC_IRQ_END  (TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS)
-
-/* Total number of interrupts depends on the enabled blocks above */
-#if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END)
-#define TWL_IRQ_END            TWL4030_GPIO_IRQ_END
-#else
-#define TWL_IRQ_END            TWL6040_CODEC_IRQ_END
-#endif
-
-/* GPMC related */
-#define OMAP_GPMC_IRQ_BASE     (TWL_IRQ_END)
-#define OMAP_GPMC_NR_IRQS      8
-#define OMAP_GPMC_IRQ_END      (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
-
-/* PRCM IRQ handler */
-#ifdef CONFIG_ARCH_OMAP2PLUS
-#define OMAP_PRCM_IRQ_BASE     (OMAP_GPMC_IRQ_END)
-#define OMAP_PRCM_NR_IRQS      64
-#define OMAP_PRCM_IRQ_END      (OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
-#else
-#define OMAP_PRCM_IRQ_END      OMAP_GPMC_IRQ_END
-#endif
-
-#define NR_IRQS                        OMAP_PRCM_IRQ_END
+#define NR_IRQS                        OMAP_FPGA_IRQ_END
 
 #define OMAP_IRQ_BIT(irq)      (1 << ((irq) % 32))
 

diff --git a/drivers/media/video/omap/omap_vout.c b/drivers/media/video/omap/omap_vout.c
index 88cf9d952631719293b48093459f9e74ac7cd762..409da0f8e5cfdb92fa0347bd3b4a6f4cee56cfa3 100644 (file)
--- a/drivers/media/video/omap/omap_vout.c
+++ b/drivers/media/video/omap/omap_vout.c
@@ -44,6 +44,7 @@
 #include <media/v4l2-device.h>
 #include <media/v4l2-ioctl.h>
 
+#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/vrfb.h>
 #include <video/omapdss.h>

diff --git a/drivers/media/video/omap3isp/isp.c b/drivers/media/video/omap3isp/isp.c
index 1c347633e663b65b1acb561ad6c2e00a868920c2..43e61fe5df50f9b07150c1dcd2442f8607afe882 100644 (file)
--- a/drivers/media/video/omap3isp/isp.c
+++ b/drivers/media/video/omap3isp/isp.c
@@ -70,6 +70,8 @@
 #include <media/v4l2-common.h>
 #include <media/v4l2-device.h>
 
+#include <plat/cpu.h>
+
 #include "isp.h"
 #include "ispreg.h"
 #include "ispccdc.h"

diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 44efc6e202afdfeb2f9cd98d6305cb517ad78dd8..d4957b4edb62850d8414c449eed8c31a62969355 100644 (file)
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -27,6 +27,8 @@
 #include <linux/pm_runtime.h>
 #include <linux/power/smartreflex.h>
 
+#include <plat/cpu.h>
+
 #define SMARTREFLEX_NAME_LEN   16
 #define NVALUE_NAME_LEN                40
 #define SR_DISABLE_TIMEOUT     200

diff --git a/drivers/staging/tidspbridge/core/wdt.c b/drivers/staging/tidspbridge/core/wdt.c
index 870f934f4f3bee4002e0400ba77afc96e155cc23..453ef748bf45c3460162245eeecdcd05da832520 100644 (file)
--- a/drivers/staging/tidspbridge/core/wdt.c
+++ b/drivers/staging/tidspbridge/core/wdt.c
@@ -25,7 +25,7 @@
 #include <dspbridge/host_os.h>
 
 
-#define OMAP34XX_WDT3_BASE             (L4_PER_34XX_BASE + 0x30000)
+#define INT_34XX_WDT3_IRQ              (36 + NR_IRQS)
 
 static struct dsp_wdt_setting dsp_wdt;