powerpc/powernv: Support PCI slot ID
authorGavin Shan <gwshan@linux.vnet.ibm.com>
Fri, 20 May 2016 06:41:38 +0000 (16:41 +1000)
committerMichael Ellerman <mpe@ellerman.id.au>
Tue, 21 Jun 2016 05:30:57 +0000 (15:30 +1000)
The reset and poll functionality from (OPAL) firmware supports
PHB and PCI slot at same time. They are identified by ID. This
supports PCI slot ID by:

   * Rename the argument name for opal_pci_reset() and opal_pci_poll()
     accordingly
   * Rename pnv_eeh_phb_poll() to pnv_eeh_poll() and adjust its argument
     name.
   * One macro is added to produce PCI slot ID.

Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
arch/powerpc/include/asm/opal.h
arch/powerpc/include/asm/pnv-pci.h
arch/powerpc/platforms/powernv/eeh-powernv.c

index 9d86c665171693da90767981beb5b0755ad6c76d..348132c00601c1a84fa03d393ed009d70477af26 100644 (file)
@@ -131,7 +131,7 @@ int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t
 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
                                        uint16_t dma_window_number, uint64_t pci_start_addr,
                                        uint64_t pci_mem_size);
-int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
+int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state);
 
 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
                                   uint64_t diag_buffer_len);
@@ -148,7 +148,7 @@ int64_t opal_get_dpo_status(__be64 *dpo_timeout);
 int64_t opal_set_system_attention_led(uint8_t led_action);
 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
                            __be16 *pci_error_type, __be16 *severity);
-int64_t opal_pci_poll(uint64_t phb_id);
+int64_t opal_pci_poll(uint64_t id);
 int64_t opal_return_cpu(void);
 int64_t opal_check_token(uint64_t token);
 int64_t opal_reinit_cpus(uint64_t flags);
index 6f77f71ee96445792a7263f1bf370aa73c2095cf..c607902c5477583c3f2783e332876575ef2c1470 100644 (file)
 #include <linux/pci.h>
 #include <misc/cxl-base.h>
 
+#define PCI_SLOT_ID_PREFIX     0x8000000000000000
+#define PCI_SLOT_ID(phb_id, bdfn)      \
+       (PCI_SLOT_ID_PREFIX | ((uint64_t)(bdfn) << 16) | (phb_id))
+
 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode);
 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
                           unsigned int virq);
index 9226df11bf39605f83c99211f94542f0dc949cc0..26bb60b1d66c7db846ab60494e935cf5acf7652e 100644 (file)
@@ -717,12 +717,12 @@ static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)
        return ret;
 }
 
-static s64 pnv_eeh_phb_poll(struct pnv_phb *phb)
+static s64 pnv_eeh_poll(unsigned long id)
 {
        s64 rc = OPAL_HARDWARE;
 
        while (1) {
-               rc = opal_pci_poll(phb->opal_id);
+               rc = opal_pci_poll(id);
                if (rc <= 0)
                        break;
 
@@ -762,7 +762,7 @@ int pnv_eeh_phb_reset(struct pci_controller *hose, int option)
         * reset followed by hot reset on root bus. So we also
         * need the PCI bus settlement delay.
         */
-       rc = pnv_eeh_phb_poll(phb);
+       rc = pnv_eeh_poll(phb->opal_id);
        if (option == EEH_RESET_DEACTIVATE) {
                if (system_state < SYSTEM_RUNNING)
                        udelay(1000 * EEH_PE_RST_SETTLE_TIME);
@@ -805,7 +805,7 @@ static int pnv_eeh_root_reset(struct pci_controller *hose, int option)
                goto out;
 
        /* Poll state of the PHB until the request is done */
-       rc = pnv_eeh_phb_poll(phb);
+       rc = pnv_eeh_poll(phb->opal_id);
        if (option == EEH_RESET_DEACTIVATE)
                msleep(EEH_PE_RST_SETTLE_TIME);
 out: