#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
-
/* Register offsets for the GPIO device */
/* LSW Mask & Data -WO */
#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
u32 int_any[ZYNQMP_GPIO_MAX_BANK];
};
+
/**
* struct zynq_gpio - gpio device private data structure
* @chip: instance of the gpio_chip
ZYNQ_GPIO_INTANY_OFFSET(bank_num));
}
}
+
static int __maybe_unused zynq_gpio_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);