PARAM_3AA_OTF_OUTPUT,
PARAM_3AA_VDMA4_OUTPUT,
PARAM_3AA_VDMA2_OUTPUT,
+ PARAM_3AA_FDDMA_OUTPUT,
+ PARAM_3AA_MRGDMA_OUTPUT,
PARAM_3AA_DDMA_OUTPUT,
PARAM_ISP_CONTROL,
PARAM_ISP_OTF_INPUT,
OTF_INPUT_FORMAT_YUV444 = 1, /* 3 Channel */
OTF_INPUT_FORMAT_YUV422 = 2, /* 3 Channel */
OTF_INPUT_FORMAT_YUV420 = 3, /* 3 Channel */
- OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER = 10,
- OTF_INPUT_FORMAT_BAYER_DMA = 11,
+ OTF_INPUT_FORMAT_Y = 7,
+ OTF_INPUT_FORMAT_BAYER_PLUS = 10,
+ OTF_INPUT_FORMAT_BAYER_COMP = 11,
};
enum otf_input_bitwidth {
DMA_INPUT_COMMAND_ENABLE = 1,
};
-enum dma_inut_format {
+enum dma_input_format {
DMA_INPUT_FORMAT_BAYER = 0,
DMA_INPUT_FORMAT_YUV444 = 1,
DMA_INPUT_FORMAT_YUV422 = 2,
DMA_INPUT_FORMAT_BAYER_PACKED = 5,
DMA_INPUT_FORMAT_YUV422_CHUNKER = 6,
DMA_INPUT_FORMAT_Y = 7,
+ DMA_INPUT_FORMAT_BAYER_PLUS = 10,
+ DMA_INPUT_FORMAT_BAYER_COMP = 11,
};
enum dma_input_bitwidth {
OTF_OUTPUT_FORMAT_YUV420 = 3,
OTF_OUTPUT_FORMAT_RGB = 4,
OTF_OUTPUT_FORMAT_YUV444_TRUNCATED = 5,
- OTF_OUTPUT_FORMAT_YUV422_TRUNCATED = 6
+ OTF_OUTPUT_FORMAT_YUV422_TRUNCATED = 6,
+ OTF_OUTPUT_FORMAT_Y = 9,
+ OTF_OUTPUT_FORMAT_BAYER_PLUS = 10,
+ OTF_OUTPUT_FORMAT_BAYER_COMP = 11,
};
enum otf_output_bitwidth {
DMA_OUTPUT_FORMAT_YUV422_CHUNKER = 6,
DMA_OUTPUT_FORMAT_YUV444_TRUNCATED = 7,
DMA_OUTPUT_FORMAT_YUV422_TRUNCATED = 8,
- DMA_OUTPUT_FORMAT_Y = 9
+ DMA_OUTPUT_FORMAT_Y = 9,
+ DMA_OUTPUT_FORMAT_BAYER_PLUS = 10,
+ DMA_OUTPUT_FORMAT_BAYER_COMP = 11,
};
enum dma_output_bitwidth {