pinctrl: sh-pfc: r8a7795: Fix SCIF_CLK_{A,B} pin's MOD_SEL assignment to MOD_SEL1...

This patch fixes SCIF_CLK_{A,B} pin's MOD_SEL assignment from MOD_SEL1
bit11 to MOD_SEL1 bit10.

This is a correction to the incorrect implementation of IPSR register
pin assignment for R8A7795 ES2.0 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.53E or later.

Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 86e3ea0adc55c11b850f86e5eea5ecc52e642869..a688a252b4953159f67468f4bc2c226c26fdd6cf 100644 (file)
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -480,7 +480,7 @@ FM(IP16_31_28)      IP16_31_28      FM(IP17_31_28)  IP17_31_28
 #define MOD_SEL1_13            FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 #define MOD_SEL1_12            FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 #define MOD_SEL1_11            FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
-#define MOD_SEL1_10            FM(SEL_SATA_0)          FM(SEL_SATA_1)
+#define MOD_SEL1_10            FM(SEL_SCIF_0)          FM(SEL_SCIF_1)
 #define MOD_SEL1_9             FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 #define MOD_SEL1_6             FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 #define MOD_SEL1_5             FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
@@ -1201,7 +1201,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP12_27_24,    ADICHS0),
 
        PINMUX_IPSR_GPSR(IP12_31_28,    SCK2),
-       PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,             SEL_SCIF1_1),
+       PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,             SEL_SCIF_1),
        PINMUX_IPSR_MSEL(IP12_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
        PINMUX_IPSR_MSEL(IP12_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
        PINMUX_IPSR_MSEL(IP12_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
@@ -1416,7 +1416,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP17_3_0,      CC5_OSCOUT),
 
        PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKB_B,           SEL_ADG_B_1),
-       PINMUX_IPSR_MSEL(IP17_7_4,      SCIF_CLK_A,             SEL_SCIF1_0),
+       PINMUX_IPSR_MSEL(IP17_7_4,      SCIF_CLK_A,             SEL_SCIF_0),
        PINMUX_IPSR_MSEL(IP17_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
        PINMUX_IPSR_MSEL(IP17_7_4,      REMOCON_A,              SEL_REMOCON_0),
        PINMUX_IPSR_MSEL(IP17_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),