*width = 1;
break;
case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
- *bank = g->drv_bank;
- *reg = g->drv_reg;
+ if (pmx->soc->hsm_in_mux) {
+ *bank = g->mux_bank;
+ *reg = g->mux_reg;
+ } else {
+ *bank = g->drv_bank;
+ *reg = g->drv_reg;
+ }
*bit = g->hsm_bit;
*width = 1;
break;
case TEGRA_PINCONF_PARAM_SCHMITT:
- *bank = g->drv_bank;
- *reg = g->drv_reg;
+ if (pmx->soc->schmitt_in_mux) {
+ *bank = g->mux_bank;
+ *reg = g->mux_reg;
+ } else {
+ *bank = g->drv_bank;
+ *reg = g->drv_reg;
+ }
*bit = g->schmitt_bit;
*width = 1;
break;
*width = g->slwr_width;
break;
case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
- *bank = g->drv_bank;
- *reg = g->drv_reg;
+ if (pmx->soc->drvtype_in_mux) {
+ *bank = g->mux_bank;
+ *reg = g->mux_reg;
+ } else {
+ *bank = g->drv_bank;
+ *reg = g->drv_reg;
+ }
*bit = g->drvtype_bit;
*width = 2;
break;
unsigned nfunctions;
const struct tegra_pingroup *groups;
unsigned ngroups;
+ bool hsm_in_mux;
+ bool schmitt_in_mux;
+ bool drvtype_in_mux;
};
int tegra_pinctrl_probe(struct platform_device *pdev,
.nfunctions = ARRAY_SIZE(tegra114_functions),
.groups = tegra114_groups,
.ngroups = ARRAY_SIZE(tegra114_groups),
+ .hsm_in_mux = false,
+ .schmitt_in_mux = false,
+ .drvtype_in_mux = false,
};
static int tegra114_pinctrl_probe(struct platform_device *pdev)
.nfunctions = ARRAY_SIZE(tegra124_functions),
.groups = tegra124_groups,
.ngroups = ARRAY_SIZE(tegra124_groups),
+ .hsm_in_mux = false,
+ .schmitt_in_mux = false,
+ .drvtype_in_mux = false,
};
static int tegra124_pinctrl_probe(struct platform_device *pdev)
.nfunctions = ARRAY_SIZE(tegra20_functions),
.groups = tegra20_groups,
.ngroups = ARRAY_SIZE(tegra20_groups),
+ .hsm_in_mux = false,
+ .schmitt_in_mux = false,
+ .drvtype_in_mux = false,
};
static int tegra20_pinctrl_probe(struct platform_device *pdev)
.nfunctions = ARRAY_SIZE(tegra30_functions),
.groups = tegra30_groups,
.ngroups = ARRAY_SIZE(tegra30_groups),
+ .hsm_in_mux = false,
+ .schmitt_in_mux = false,
+ .drvtype_in_mux = false,
};
static int tegra30_pinctrl_probe(struct platform_device *pdev)