****************************************************************************/
void __init dove_init_early(void)
{
- orion_time_set_base((unsigned long) TIMER_VIRT_BASE);
+ orion_time_set_base(TIMER_VIRT_BASE);
}
static int get_tclk(void)
static void __init dove_timer_init(void)
{
- orion_time_init((unsigned long) BRIDGE_VIRT_BASE,
- BRIDGE_INT_TIMER1_CLR,
+ orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
IRQ_DOVE_BRIDGE, get_tclk());
}
****************************************************************************/
void __init kirkwood_init_early(void)
{
- orion_time_set_base((unsigned long) TIMER_VIRT_BASE);
+ orion_time_set_base(TIMER_VIRT_BASE);
/*
* Some Kirkwood devices allocate their coherent buffers from atomic
{
kirkwood_tclk = kirkwood_find_tclk();
- orion_time_init((unsigned long) BRIDGE_VIRT_BASE,
- BRIDGE_INT_TIMER1_CLR,
+ orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
}
****************************************************************************/
void __init mv78xx0_init_early(void)
{
- orion_time_set_base((unsigned long) TIMER_VIRT_BASE);
+ orion_time_set_base(TIMER_VIRT_BASE);
}
static void mv78xx0_timer_init(void)
{
- orion_time_init((unsigned long) BRIDGE_VIRT_BASE,
- BRIDGE_INT_TIMER1_CLR,
+ orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
IRQ_MV78XX0_TIMER_1, get_tclk());
}
****************************************************************************/
void __init orion5x_init_early(void)
{
- orion_time_set_base((unsigned long) TIMER_VIRT_BASE);
+ orion_time_set_base(TIMER_VIRT_BASE);
}
int orion5x_tclk;
{
orion5x_tclk = orion5x_find_tclk();
- orion_time_init((unsigned long) ORION5X_BRIDGE_VIRT_BASE,
- BRIDGE_INT_TIMER1_CLR,
+ orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
IRQ_ORION5X_BRIDGE, orion5x_tclk);
}
#ifndef __PLAT_TIME_H
#define __PLAT_TIME_H
-void orion_time_set_base(u32 timer_base);
+void orion_time_set_base(void __iomem *timer_base);
-void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask,
+void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask,
unsigned int irq, unsigned int tclk);
};
void __init
-orion_time_set_base(u32 _timer_base)
+orion_time_set_base(void __iomem *_timer_base)
{
- timer_base = (void __iomem *)_timer_base;
+ timer_base = _timer_base;
}
void __init
-orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
+orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
unsigned int irq, unsigned int tclk)
{
u32 u;
/*
* Set SoC-specific data.
*/
- bridge_base = (void __iomem *)_bridge_base;
+ bridge_base = _bridge_base;
bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
ticks_per_jiffy = (tclk + HZ/2) / HZ;