Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queued

Backmerge -fixes since there's more DDI-E related cleanups on top of
the pile of -fixes for skl that just landed for 4.3.

Conflicts:
	drivers/gpu/drm/i915/intel_display.c
	drivers/gpu/drm/i914/intel_dp.c
	drivers/gpu/drm/i915/intel_lrc.c

Conflicts are all fairly harmless adjacent line stuff.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>

diff --cc drivers/gpu/drm/i915/Makefile
Simple merge

diff --cc drivers/gpu/drm/i915/i915_debugfs.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/i915_irq.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_reg.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_ddi.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_display.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_dp.c
index f45872cc6d24ec9188069694841b782ed4aafba8,0a2e33fbf20dd2902817d85c10aa6b402d40e869..f8f4d99440c1becf92b8a57778f21d8840120a2a
--- 1/drivers/gpu/drm/i915/intel_dp.c
--- 2/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -3993,9 -3909,15 +4000,14 @@@ intel_dp_get_dpcd(struct intel_dp *inte
                }
        }
  
-       /* Training Pattern 3 support, both source and sink */
+       /* Training Pattern 3 support, Intel platforms that support HBR2 alone
+        * have support for TP3 hence that check is used along with dpcd check
+        * to ensure TP3 can be enabled.
+        * SKL < B0: due it's WaDisableHBR2 is the only exception where TP3 is
+        * supported but still not enabled.
+        */
 -      if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
 -          intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
 +      if (drm_dp_tps3_supported(intel_dp->dpcd) &&
-           (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
+           intel_dp_source_supports_hbr2(dev)) {
                intel_dp->use_tps3 = true;
                DRM_DEBUG_KMS("Displayport TPS3 supported\n");
        } else

diff --cc drivers/gpu/drm/i915/intel_dp_mst.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_fbdev.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_hdmi.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_lrc.c
index e9520afc2033bf39c8ac319bfd064d987cd9485e,72e0edd7bbde77d3b12812bead2a3f676589385a..40cbba4ea4bab41eed4e915a96780792e58ebfb2
--- 1/drivers/gpu/drm/i915/intel_lrc.c
--- 2/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@@ -1027,9 -1004,7 +1027,11 @@@ static int intel_lr_context_pin(struct 
                if (ret)
                        goto unpin_ctx_obj;
  
+               ctx_obj->dirty = true;
++
 +              /* Invalidate GuC TLB. */
 +              if (i915.enable_guc_submission)
 +                      I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
        }
  
        return ret;

diff --cc drivers/gpu/drm/i915/intel_runtime_pm.c
Simple merge

diff --cc include/drm/drm_dp_helper.h
Simple merge