{
struct ixgbe_mac_info *mac = &hw->mac;
struct ixgbe_phy_info *phy = &hw->phy;
- s32 ret_val = 0;
+ s32 ret_val;
u16 list_offset, data_offset;
/* Identify the PHY */
/* Call SFP+ identify routine to get the SFP+ module type */
ret_val = phy->ops.identify_sfp(hw);
- if (ret_val != 0)
- goto out;
- else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
- ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
- goto out;
- }
+ if (ret_val)
+ return ret_val;
+ if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
+ return IXGBE_ERR_SFP_NOT_SUPPORTED;
/* Check to see if SFP+ module is supported */
ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
&list_offset,
&data_offset);
- if (ret_val != 0) {
- ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
- goto out;
- }
+ if (ret_val)
+ return IXGBE_ERR_SFP_NOT_SUPPORTED;
break;
default:
break;
}
-out:
- return ret_val;
+ return 0;
}
/**
{
u32 regval;
u32 i;
- s32 ret_val = 0;
+ s32 ret_val;
ret_val = ixgbe_start_hw_generic(hw);
IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
}
+ if (ret_val)
+ return ret_val;
+
/* set the completion timeout for interface */
- if (ret_val == 0)
- ixgbe_set_pcie_completion_timeout(hw);
+ ixgbe_set_pcie_completion_timeout(hw);
- return ret_val;
+ return 0;
}
/**
ixgbe_link_speed *speed,
bool *autoneg)
{
- s32 status = 0;
u32 autoc = 0;
/*
break;
default:
- status = IXGBE_ERR_LINK_SETUP;
- break;
+ return IXGBE_ERR_LINK_SETUP;
}
- return status;
+ return 0;
}
/**
**/
static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
{
- enum ixgbe_media_type media_type;
-
/* Detect if there is a copper PHY attached. */
switch (hw->phy.type) {
case ixgbe_phy_cu_unknown:
case ixgbe_phy_tn:
- media_type = ixgbe_media_type_copper;
- goto out;
+ return ixgbe_media_type_copper;
+
default:
break;
}
case IXGBE_DEV_ID_82598:
case IXGBE_DEV_ID_82598_BX:
/* Default device ID is mezzanine card KX/KX4 */
- media_type = ixgbe_media_type_backplane;
- break;
+ return ixgbe_media_type_backplane;
+
case IXGBE_DEV_ID_82598AF_DUAL_PORT:
case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
case IXGBE_DEV_ID_82598EB_XF_LR:
case IXGBE_DEV_ID_82598EB_SFP_LOM:
- media_type = ixgbe_media_type_fiber;
- break;
+ return ixgbe_media_type_fiber;
+
case IXGBE_DEV_ID_82598EB_CX4:
case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
- media_type = ixgbe_media_type_cx4;
- break;
+ return ixgbe_media_type_cx4;
+
case IXGBE_DEV_ID_82598AT:
case IXGBE_DEV_ID_82598AT2:
- media_type = ixgbe_media_type_copper;
- break;
+ return ixgbe_media_type_copper;
+
default:
- media_type = ixgbe_media_type_unknown;
- break;
+ return ixgbe_media_type_unknown;
}
-out:
- return media_type;
}
/**
**/
static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
{
- s32 ret_val = 0;
u32 fctrl_reg;
u32 rmcs_reg;
u32 reg;
bool link_up;
/* Validate the water mark configuration */
- if (!hw->fc.pause_time) {
- ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
- goto out;
- }
+ if (!hw->fc.pause_time)
+ return IXGBE_ERR_INVALID_LINK_SETTINGS;
/* Low water mark of zero causes XOFF floods */
for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
if (!hw->fc.low_water[i] ||
hw->fc.low_water[i] >= hw->fc.high_water[i]) {
hw_dbg(hw, "Invalid water mark configuration\n");
- ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
- goto out;
+ return IXGBE_ERR_INVALID_LINK_SETTINGS;
}
}
}
break;
default:
hw_dbg(hw, "Flow control param set incorrectly\n");
- ret_val = IXGBE_ERR_CONFIG;
- goto out;
+ return IXGBE_ERR_CONFIG;
}
/* Set 802.3x based flow control settings. */
/* Configure flow control refresh threshold value */
IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
-out:
- return ret_val;
+ return 0;
}
/**
}
if (!*link_up)
- goto out;
+ return 0;
}
links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
(ixgbe_validate_link_ready(hw) != 0))
*link_up = false;
-out:
return 0;
}
bool autoneg_wait_to_complete)
{
bool autoneg = false;
- s32 status = 0;
ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
u32 autoc = curr_autoc;
speed &= link_capabilities;
if (speed == IXGBE_LINK_SPEED_UNKNOWN)
- status = IXGBE_ERR_LINK_SETUP;
+ return IXGBE_ERR_LINK_SETUP;
/* Set KX4/KX support according to speed requested */
else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
}
- if (status == 0) {
- /*
- * Setup and restart the link based on the new values in
- * ixgbe_hw This will write the AUTOC register based on the new
- * stored values
- */
- status = ixgbe_start_mac_link_82598(hw,
- autoneg_wait_to_complete);
- }
-
- return status;
+ /* Setup and restart the link based on the new values in
+ * ixgbe_hw This will write the AUTOC register based on the new
+ * stored values
+ */
+ return ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
}
**/
static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
{
- s32 status = 0;
+ s32 status;
s32 phy_status = 0;
u32 ctrl;
u32 gheccr;
/* Call adapter stop to disable tx/rx and clear interrupts */
status = hw->mac.ops.stop_adapter(hw);
- if (status != 0)
- goto reset_hw_out;
+ if (status)
+ return status;
/*
* Power up the Atlas Tx lanes if they are currently powered down.
/* Init PHY and function pointers, perform SFP setup */
phy_status = hw->phy.ops.init(hw);
if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
- goto reset_hw_out;
+ return phy_status;
if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
goto mac_reset_top;
*/
hw->mac.ops.init_rx_addrs(hw);
-reset_hw_out:
if (phy_status)
status = phy_status;
static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
{
- s32 ret_val = 0;
+ s32 ret_val;
u16 list_offset, data_offset, data_value;
if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
&data_offset);
- if (ret_val != 0)
- goto setup_sfp_out;
+ if (ret_val)
+ return ret_val;
/* PHY config will finish before releasing the semaphore */
ret_val = hw->mac.ops.acquire_swfw_sync(hw,
IXGBE_GSSR_MAC_CSR_SM);
- if (ret_val != 0) {
- ret_val = IXGBE_ERR_SWFW_SYNC;
- goto setup_sfp_out;
- }
+ if (ret_val)
+ return IXGBE_ERR_SWFW_SYNC;
if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
goto setup_sfp_err;
if (ret_val) {
hw_dbg(hw, " sfp module setup not complete\n");
- ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
- goto setup_sfp_out;
+ return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
}
}
-setup_sfp_out:
- return ret_val;
+ return 0;
setup_sfp_err:
/* Release the semaphore */
{
struct ixgbe_mac_info *mac = &hw->mac;
struct ixgbe_phy_info *phy = &hw->phy;
- s32 ret_val = 0;
+ s32 ret_val;
u32 esdp;
if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
ixgbe_link_speed *speed,
bool *autoneg)
{
- s32 status = 0;
u32 autoc = 0;
/* Determine 1G link capabilities off of SFP+ type */
hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
*speed = IXGBE_LINK_SPEED_1GB_FULL;
*autoneg = true;
- goto out;
+ return 0;
}
/*
break;
default:
- status = IXGBE_ERR_LINK_SETUP;
- goto out;
+ return IXGBE_ERR_LINK_SETUP;
}
if (hw->phy.multispeed_fiber) {
*autoneg = true;
}
-out:
- return status;
+ return 0;
}
/**
**/
static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
{
- enum ixgbe_media_type media_type;
-
/* Detect if there is a copper PHY attached. */
switch (hw->phy.type) {
case ixgbe_phy_cu_unknown:
case ixgbe_phy_tn:
- media_type = ixgbe_media_type_copper;
- goto out;
+ return ixgbe_media_type_copper;
+
default:
break;
}
case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
case IXGBE_DEV_ID_82599_XAUI_LOM:
/* Default device ID is mezzanine card KX/KX4 */
- media_type = ixgbe_media_type_backplane;
- break;
+ return ixgbe_media_type_backplane;
+
case IXGBE_DEV_ID_82599_SFP:
case IXGBE_DEV_ID_82599_SFP_FCOE:
case IXGBE_DEV_ID_82599_SFP_EM:
case IXGBE_DEV_ID_82599_SFP_SF2:
case IXGBE_DEV_ID_82599_SFP_SF_QP:
case IXGBE_DEV_ID_82599EN_SFP:
- media_type = ixgbe_media_type_fiber;
- break;
+ return ixgbe_media_type_fiber;
+
case IXGBE_DEV_ID_82599_CX4:
- media_type = ixgbe_media_type_cx4;
- break;
+ return ixgbe_media_type_cx4;
+
case IXGBE_DEV_ID_82599_T3_LOM:
- media_type = ixgbe_media_type_copper;
- break;
+ return ixgbe_media_type_copper;
+
case IXGBE_DEV_ID_82599_LS:
- media_type = ixgbe_media_type_fiber_lco;
- break;
+ return ixgbe_media_type_fiber_lco;
+
case IXGBE_DEV_ID_82599_QSFP_SF_QP:
- media_type = ixgbe_media_type_fiber_qsfp;
- break;
+ return ixgbe_media_type_fiber_qsfp;
+
default:
- media_type = ixgbe_media_type_unknown;
- break;
+ return ixgbe_media_type_unknown;
}
-out:
- return media_type;
}
/**
status = hw->mac.ops.acquire_swfw_sync(hw,
IXGBE_GSSR_MAC_CSR_SM);
if (status)
- goto out;
+ return status;
got_lock = true;
}
/* Add delay to filter out noises during initial link setup */
msleep(50);
-out:
return status;
}
bool autoneg_wait_to_complete)
{
bool autoneg = false;
- s32 status = 0;
+ s32 status;
u32 pma_pmd_1g, link_mode, links_reg, i;
u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
/* Check to see if speed passed in is supported. */
status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities,
&autoneg);
- if (status != 0)
- goto out;
+ if (status)
+ return status;
speed &= link_capabilities;
- if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
- status = IXGBE_ERR_LINK_SETUP;
- goto out;
- }
+ if (speed == IXGBE_LINK_SPEED_UNKNOWN)
+ return IXGBE_ERR_LINK_SETUP;
/* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
if (hw->mac.orig_link_settings_stored)
/* Restart link */
status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
if (status)
- goto out;
+ return status;
/* Only poll for autoneg to complete if specified to do so */
if (autoneg_wait_to_complete) {
msleep(50);
}
-out:
return status;
}
/* Call adapter stop to disable tx/rx and clear interrupts */
status = hw->mac.ops.stop_adapter(hw);
- if (status != 0)
- goto reset_hw_out;
+ if (status)
+ return status;
/* flush pending Tx transactions */
ixgbe_clear_tx_pending(hw);
status = hw->phy.ops.init(hw);
if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
- goto reset_hw_out;
+ return status;
/* Setup SFP module if there is one present. */
if (hw->phy.sfp_setup_needed) {
}
if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
- goto reset_hw_out;
+ return status;
/* Reset PHY */
if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
hw->mac.orig_autoc,
false);
if (status)
- goto reset_hw_out;
+ return status;
}
if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
&hw->mac.wwpn_prefix);
-reset_hw_out:
return status;
}
s32 ret_val = 0;
ret_val = ixgbe_start_hw_generic(hw);
- if (ret_val != 0)
- goto out;
+ if (ret_val)
+ return ret_val;
ret_val = ixgbe_start_hw_gen2(hw);
- if (ret_val != 0)
- goto out;
+ if (ret_val)
+ return ret_val;
/* We need to run link autotry after the driver loads */
hw->mac.autotry_restart = true;
- if (ret_val == 0)
- ret_val = ixgbe_verify_fw_version_82599(hw);
-out:
- return ret_val;
+ if (ret_val)
+ return ret_val;
+
+ return ixgbe_verify_fw_version_82599(hw);
}
/**
**/
static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
{
- s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
+ s32 status;
/* Detect PHY if not unknown - returns success if already detected. */
status = ixgbe_identify_phy_generic(hw);
- if (status != 0) {
+ if (status) {
/* 82599 10GBASE-T requires an external PHY */
if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
- goto out;
- else
- status = ixgbe_identify_module_generic(hw);
+ return status;
+ status = ixgbe_identify_module_generic(hw);
}
/* Set PHY type none if no PHY detected */
/* Return error if SFP module has been detected but is not supported */
if (hw->phy.type == ixgbe_phy_sfp_unsupported)
- status = IXGBE_ERR_SFP_NOT_SUPPORTED;
+ return IXGBE_ERR_SFP_NOT_SUPPORTED;
-out:
return status;
}
u16 fw_version = 0;
/* firmware check is only necessary for SFI devices */
- if (hw->phy.media_type != ixgbe_media_type_fiber) {
- status = 0;
- goto fw_version_out;
- }
+ if (hw->phy.media_type != ixgbe_media_type_fiber)
+ return 0;
/* get the offset to the Firmware Module block */
offset = IXGBE_FW_PTR;
if (hw->eeprom.ops.read(hw, offset, &fw_offset))
goto fw_version_err;
- if ((fw_offset == 0) || (fw_offset == 0xFFFF))
- goto fw_version_out;
+ if (fw_offset == 0 || fw_offset == 0xFFFF)
+ return IXGBE_ERR_EEPROM_VERSION;
/* get the offset to the Pass Through Patch Configuration block */
offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR;
if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset))
goto fw_version_err;
- if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
- goto fw_version_out;
+ if (fw_ptp_cfg_offset == 0 || fw_ptp_cfg_offset == 0xFFFF)
+ return IXGBE_ERR_EEPROM_VERSION;
/* get the firmware version */
offset = fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4;
if (fw_version > 0x5)
status = 0;
-fw_version_out:
return status;
fw_version_err:
**/
static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
{
- bool lesm_enabled = false;
u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
s32 status;
/* get the offset to the Firmware Module block */
status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
- if ((status != 0) ||
- (fw_offset == 0) || (fw_offset == 0xFFFF))
- goto out;
+ if (status || fw_offset == 0 || fw_offset == 0xFFFF)
+ return false;
/* get the offset to the LESM Parameters block */
status = hw->eeprom.ops.read(hw, (fw_offset +
IXGBE_FW_LESM_PARAMETERS_PTR),
&fw_lesm_param_offset);
- if ((status != 0) ||
- (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
- goto out;
+ if (status ||
+ fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
+ return false;
/* get the lesm state word */
status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
IXGBE_FW_LESM_STATE_1),
&fw_lesm_state);
- if ((status == 0) &&
- (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
- lesm_enabled = true;
+ if (!status && (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
+ return true;
-out:
- return lesm_enabled;
+ return false;
}
/**
u16 words, u16 *data)
{
struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
- s32 ret_val = IXGBE_ERR_CONFIG;
- /*
- * If EEPROM is detected and can be addressed using 14 bits,
+ /* If EEPROM is detected and can be addressed using 14 bits,
* use EERD otherwise use bit bang
*/
- if ((eeprom->type == ixgbe_eeprom_spi) &&
- (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
- ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
- data);
- else
- ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
- words,
- data);
+ if (eeprom->type == ixgbe_eeprom_spi &&
+ offset + (words - 1) <= IXGBE_EERD_MAX_ADDR)
+ return ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
- return ret_val;
+ return ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, words,
+ data);
}
/**
u16 offset, u16 *data)
{
struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
- s32 ret_val = IXGBE_ERR_CONFIG;
/*
* If EEPROM is detected and can be addressed using 14 bits,
* use EERD otherwise use bit bang
*/
- if ((eeprom->type == ixgbe_eeprom_spi) &&
- (offset <= IXGBE_EERD_MAX_ADDR))
- ret_val = ixgbe_read_eerd_generic(hw, offset, data);
- else
- ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
+ if (eeprom->type == ixgbe_eeprom_spi && offset <= IXGBE_EERD_MAX_ADDR)
+ return ixgbe_read_eerd_generic(hw, offset, data);
- return ret_val;
+ return ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
}
/**
*/
if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
- ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
- goto out;
+ return IXGBE_ERR_INVALID_LINK_SETTINGS;
}
/*
/* some MAC's need RMW protection on AUTOC */
ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
if (ret_val)
- goto out;
+ return ret_val;
/* only backplane uses autoc so fall though */
case ixgbe_media_type_fiber:
break;
default:
hw_dbg(hw, "Flow control param set incorrectly\n");
- ret_val = IXGBE_ERR_CONFIG;
- goto out;
+ return IXGBE_ERR_CONFIG;
}
if (hw->mac.type != ixgbe_mac_X540) {
*/
ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
if (ret_val)
- goto out;
+ return ret_val;
} else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
ixgbe_device_supports_autoneg_fc(hw)) {
}
hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
-out:
return ret_val;
}
/* Setup flow control */
ret_val = ixgbe_setup_fc(hw);
if (!ret_val)
- goto out;
+ return 0;
/* Clear adapter stopped flag */
hw->adapter_stopped = false;
-out:
return ret_val;
}
s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
u16 words, u16 *data)
{
- s32 status = 0;
+ s32 status;
u16 i, count;
hw->eeprom.ops.init_params(hw);
- if (words == 0) {
- status = IXGBE_ERR_INVALID_ARGUMENT;
- goto out;
- }
+ if (words == 0)
+ return IXGBE_ERR_INVALID_ARGUMENT;
- if (offset + words > hw->eeprom.word_size) {
- status = IXGBE_ERR_EEPROM;
- goto out;
- }
+ if (offset + words > hw->eeprom.word_size)
+ return IXGBE_ERR_EEPROM;
/*
* The EEPROM page size cannot be queried from the chip. We do lazy
break;
}
-out:
return status;
}
/* Prepare the EEPROM for writing */
status = ixgbe_acquire_eeprom(hw);
+ if (status)
+ return status;
- if (status == 0) {
- if (ixgbe_ready_eeprom(hw) != 0) {
- ixgbe_release_eeprom(hw);
- status = IXGBE_ERR_EEPROM;
- }
+ if (ixgbe_ready_eeprom(hw) != 0) {
+ ixgbe_release_eeprom(hw);
+ return IXGBE_ERR_EEPROM;
}
- if (status == 0) {
- for (i = 0; i < words; i++) {
- ixgbe_standby_eeprom(hw);
+ for (i = 0; i < words; i++) {
+ ixgbe_standby_eeprom(hw);
+
+ /* Send the WRITE ENABLE command (8 bit opcode) */
+ ixgbe_shift_out_eeprom_bits(hw,
+ IXGBE_EEPROM_WREN_OPCODE_SPI,
+ IXGBE_EEPROM_OPCODE_BITS);
- /* Send the WRITE ENABLE command (8 bit opcode ) */
- ixgbe_shift_out_eeprom_bits(hw,
- IXGBE_EEPROM_WREN_OPCODE_SPI,
- IXGBE_EEPROM_OPCODE_BITS);
+ ixgbe_standby_eeprom(hw);
- ixgbe_standby_eeprom(hw);
+ /* Some SPI eeproms use the 8th address bit embedded
+ * in the opcode
+ */
+ if ((hw->eeprom.address_bits == 8) &&
+ ((offset + i) >= 128))
+ write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
- /*
- * Some SPI eeproms use the 8th address bit embedded
- * in the opcode
- */
- if ((hw->eeprom.address_bits == 8) &&
- ((offset + i) >= 128))
- write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
-
- /* Send the Write command (8-bit opcode + addr) */
- ixgbe_shift_out_eeprom_bits(hw, write_opcode,
- IXGBE_EEPROM_OPCODE_BITS);
- ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
- hw->eeprom.address_bits);
-
- page_size = hw->eeprom.word_page_size;
-
- /* Send the data in burst via SPI*/
- do {
- word = data[i];
- word = (word >> 8) | (word << 8);
- ixgbe_shift_out_eeprom_bits(hw, word, 16);
-
- if (page_size == 0)
- break;
-
- /* do not wrap around page */
- if (((offset + i) & (page_size - 1)) ==
- (page_size - 1))
- break;
- } while (++i < words);
-
- ixgbe_standby_eeprom(hw);
- usleep_range(10000, 20000);
- }
- /* Done with writing - release the EEPROM */
- ixgbe_release_eeprom(hw);
+ /* Send the Write command (8-bit opcode + addr) */
+ ixgbe_shift_out_eeprom_bits(hw, write_opcode,
+ IXGBE_EEPROM_OPCODE_BITS);
+ ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
+ hw->eeprom.address_bits);
+
+ page_size = hw->eeprom.word_page_size;
+
+ /* Send the data in burst via SPI */
+ do {
+ word = data[i];
+ word = (word >> 8) | (word << 8);
+ ixgbe_shift_out_eeprom_bits(hw, word, 16);
+
+ if (page_size == 0)
+ break;
+
+ /* do not wrap around page */
+ if (((offset + i) & (page_size - 1)) ==
+ (page_size - 1))
+ break;
+ } while (++i < words);
+
+ ixgbe_standby_eeprom(hw);
+ usleep_range(10000, 20000);
}
+ /* Done with writing - release the EEPROM */
+ ixgbe_release_eeprom(hw);
- return status;
+ return 0;
}
/**
**/
s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
{
- s32 status;
-
hw->eeprom.ops.init_params(hw);
- if (offset >= hw->eeprom.word_size) {
- status = IXGBE_ERR_EEPROM;
- goto out;
- }
+ if (offset >= hw->eeprom.word_size)
+ return IXGBE_ERR_EEPROM;
- status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
-
-out:
- return status;
+ return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
}
/**
s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
u16 words, u16 *data)
{
- s32 status = 0;
+ s32 status;
u16 i, count;
hw->eeprom.ops.init_params(hw);
- if (words == 0) {
- status = IXGBE_ERR_INVALID_ARGUMENT;
- goto out;
- }
+ if (words == 0)
+ return IXGBE_ERR_INVALID_ARGUMENT;
- if (offset + words > hw->eeprom.word_size) {
- status = IXGBE_ERR_EEPROM;
- goto out;
- }
+ if (offset + words > hw->eeprom.word_size)
+ return IXGBE_ERR_EEPROM;
/*
* We cannot hold synchronization semaphores for too long
status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
count, &data[i]);
- if (status != 0)
- break;
+ if (status)
+ return status;
}
-out:
- return status;
+ return 0;
}
/**
/* Prepare the EEPROM for reading */
status = ixgbe_acquire_eeprom(hw);
+ if (status)
+ return status;
- if (status == 0) {
- if (ixgbe_ready_eeprom(hw) != 0) {
- ixgbe_release_eeprom(hw);
- status = IXGBE_ERR_EEPROM;
- }
+ if (ixgbe_ready_eeprom(hw) != 0) {
+ ixgbe_release_eeprom(hw);
+ return IXGBE_ERR_EEPROM;
}
- if (status == 0) {
- for (i = 0; i < words; i++) {
- ixgbe_standby_eeprom(hw);
- /*
- * Some SPI eeproms use the 8th address bit embedded
- * in the opcode
- */
- if ((hw->eeprom.address_bits == 8) &&
- ((offset + i) >= 128))
- read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
-
- /* Send the READ command (opcode + addr) */
- ixgbe_shift_out_eeprom_bits(hw, read_opcode,
- IXGBE_EEPROM_OPCODE_BITS);
- ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
- hw->eeprom.address_bits);
-
- /* Read the data. */
- word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
- data[i] = (word_in >> 8) | (word_in << 8);
- }
+ for (i = 0; i < words; i++) {
+ ixgbe_standby_eeprom(hw);
+ /* Some SPI eeproms use the 8th address bit embedded
+ * in the opcode
+ */
+ if ((hw->eeprom.address_bits == 8) &&
+ ((offset + i) >= 128))
+ read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
- /* End this read operation */
- ixgbe_release_eeprom(hw);
+ /* Send the READ command (opcode + addr) */
+ ixgbe_shift_out_eeprom_bits(hw, read_opcode,
+ IXGBE_EEPROM_OPCODE_BITS);
+ ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
+ hw->eeprom.address_bits);
+
+ /* Read the data. */
+ word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
+ data[i] = (word_in >> 8) | (word_in << 8);
}
- return status;
+ /* End this read operation */
+ ixgbe_release_eeprom(hw);
+
+ return 0;
}
/**
s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
u16 *data)
{
- s32 status;
-
hw->eeprom.ops.init_params(hw);
- if (offset >= hw->eeprom.word_size) {
- status = IXGBE_ERR_EEPROM;
- goto out;
- }
-
- status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
+ if (offset >= hw->eeprom.word_size)
+ return IXGBE_ERR_EEPROM;
-out:
- return status;
+ return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
}
/**
u16 words, u16 *data)
{
u32 eerd;
- s32 status = 0;
+ s32 status;
u32 i;
hw->eeprom.ops.init_params(hw);
- if (words == 0) {
- status = IXGBE_ERR_INVALID_ARGUMENT;
- goto out;
- }
+ if (words == 0)
+ return IXGBE_ERR_INVALID_ARGUMENT;
- if (offset >= hw->eeprom.word_size) {
- status = IXGBE_ERR_EEPROM;
- goto out;
- }
+ if (offset >= hw->eeprom.word_size)
+ return IXGBE_ERR_EEPROM;
for (i = 0; i < words; i++) {
eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
IXGBE_EEPROM_RW_REG_DATA);
} else {
hw_dbg(hw, "Eeprom read timed out\n");
- goto out;
+ return status;
}
}
-out:
- return status;
+
+ return 0;
}
/**
u16 offset)
{
u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
- s32 status = 0;
+ s32 status;
u16 i;
for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
IXGBE_EEPROM_PAGE_SIZE_MAX, data);
hw->eeprom.word_page_size = 0;
- if (status != 0)
- goto out;
+ if (status)
+ return status;
status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
- if (status != 0)
- goto out;
+ if (status)
+ return status;
/*
* When writing in burst more than the actual page size
hw_dbg(hw, "Detected EEPROM page size = %d words.\n",
hw->eeprom.word_page_size);
-out:
- return status;
+ return 0;
}
/**
u16 words, u16 *data)
{
u32 eewr;
- s32 status = 0;
+ s32 status;
u16 i;
hw->eeprom.ops.init_params(hw);
- if (words == 0) {
- status = IXGBE_ERR_INVALID_ARGUMENT;
- goto out;
- }
+ if (words == 0)
+ return IXGBE_ERR_INVALID_ARGUMENT;
- if (offset >= hw->eeprom.word_size) {
- status = IXGBE_ERR_EEPROM;
- goto out;
- }
+ if (offset >= hw->eeprom.word_size)
+ return IXGBE_ERR_EEPROM;
for (i = 0; i < words; i++) {
eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
IXGBE_EEPROM_RW_REG_START;
status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
- if (status != 0) {
+ if (status) {
hw_dbg(hw, "Eeprom write EEWR timed out\n");
- goto out;
+ return status;
}
IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
- if (status != 0) {
+ if (status) {
hw_dbg(hw, "Eeprom write EEWR timed out\n");
- goto out;
+ return status;
}
}
-out:
- return status;
+ return 0;
}
/**
{
u32 i;
u32 reg;
- s32 status = IXGBE_ERR_EEPROM;
for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
if (ee_reg == IXGBE_NVM_POLL_READ)
reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
if (reg & IXGBE_EEPROM_RW_REG_DONE) {
- status = 0;
- break;
+ return 0;
}
udelay(5);
}
- return status;
+ return IXGBE_ERR_EEPROM;
}
/**
**/
static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
{
- s32 status = 0;
u32 eec;
u32 i;
if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
- status = IXGBE_ERR_SWFW_SYNC;
+ return IXGBE_ERR_SWFW_SYNC;
- if (status == 0) {
- eec = IXGBE_READ_REG(hw, IXGBE_EEC);
-
- /* Request EEPROM Access */
- eec |= IXGBE_EEC_REQ;
- IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+ eec = IXGBE_READ_REG(hw, IXGBE_EEC);
- for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
- eec = IXGBE_READ_REG(hw, IXGBE_EEC);
- if (eec & IXGBE_EEC_GNT)
- break;
- udelay(5);
- }
+ /* Request EEPROM Access */
+ eec |= IXGBE_EEC_REQ;
+ IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
- /* Release if grant not acquired */
- if (!(eec & IXGBE_EEC_GNT)) {
- eec &= ~IXGBE_EEC_REQ;
- IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
- hw_dbg(hw, "Could not acquire EEPROM grant\n");
+ for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
+ eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+ if (eec & IXGBE_EEC_GNT)
+ break;
+ udelay(5);
+ }
- hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
- status = IXGBE_ERR_EEPROM;
- }
+ /* Release if grant not acquired */
+ if (!(eec & IXGBE_EEC_GNT)) {
+ eec &= ~IXGBE_EEC_REQ;
+ IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+ hw_dbg(hw, "Could not acquire EEPROM grant\n");
- /* Setup EEPROM for Read/Write */
- if (status == 0) {
- /* Clear CS and SK */
- eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
- IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
- IXGBE_WRITE_FLUSH(hw);
- udelay(1);
- }
+ hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
+ return IXGBE_ERR_EEPROM;
}
- return status;
+
+ /* Setup EEPROM for Read/Write */
+ /* Clear CS and SK */
+ eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
+ IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+ IXGBE_WRITE_FLUSH(hw);
+ udelay(1);
+ return 0;
}
/**
**/
static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
{
- s32 status = IXGBE_ERR_EEPROM;
u32 timeout = 2000;
u32 i;
u32 swsm;
* set and we have the semaphore
*/
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
- if (!(swsm & IXGBE_SWSM_SMBI)) {
- status = 0;
+ if (!(swsm & IXGBE_SWSM_SMBI))
break;
- }
usleep_range(50, 100);
}
if (i == timeout) {
hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n");
- /*
- * this release is particularly important because our attempts
+ /* this release is particularly important because our attempts
* above to get the semaphore may have succeeded, and if there
* was a timeout, we should unconditionally clear the semaphore
* bits to free the driver to make progress
ixgbe_release_eeprom_semaphore(hw);
usleep_range(50, 100);
- /*
- * one last try
+ /* one last try
* If the SMBI bit is 0 when we read it, then the bit will be
* set and we have the semaphore
*/
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
- if (!(swsm & IXGBE_SWSM_SMBI))
- status = 0;
+ if (swsm & IXGBE_SWSM_SMBI) {
+ hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");
+ return IXGBE_ERR_EEPROM;
+ }
}
/* Now get the semaphore between SW/FW through the SWESMBI bit */
- if (status == 0) {
- for (i = 0; i < timeout; i++) {
- swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+ for (i = 0; i < timeout; i++) {
+ swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
- /* Set the SW EEPROM semaphore bit to request access */
- swsm |= IXGBE_SWSM_SWESMBI;
- IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
+ /* Set the SW EEPROM semaphore bit to request access */
+ swsm |= IXGBE_SWSM_SWESMBI;
+ IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
- /*
- * If we set the bit successfully then we got the
- * semaphore.
- */
- swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
- if (swsm & IXGBE_SWSM_SWESMBI)
- break;
+ /* If we set the bit successfully then we got the
+ * semaphore.
+ */
+ swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+ if (swsm & IXGBE_SWSM_SWESMBI)
+ break;
- usleep_range(50, 100);
- }
+ usleep_range(50, 100);
+ }
- /*
- * Release semaphores and return error if SW EEPROM semaphore
- * was not granted because we don't have access to the EEPROM
- */
- if (i >= timeout) {
- hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n");
- ixgbe_release_eeprom_semaphore(hw);
- status = IXGBE_ERR_EEPROM;
- }
- } else {
- hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");
+ /* Release semaphores and return error if SW EEPROM semaphore
+ * was not granted because we don't have access to the EEPROM
+ */
+ if (i >= timeout) {
+ hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n");
+ ixgbe_release_eeprom_semaphore(hw);
+ return IXGBE_ERR_EEPROM;
}
- return status;
+ return 0;
}
/**
**/
static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
{
- s32 status = 0;
u16 i;
u8 spi_stat_reg;
*/
if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
hw_dbg(hw, "SPI EEPROM Status error\n");
- status = IXGBE_ERR_EEPROM;
+ return IXGBE_ERR_EEPROM;
}
- return status;
+ return 0;
}
/**
**/
s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
{
- s32 ret_val = 0;
u32 mflcn_reg, fccfg_reg;
u32 reg;
u32 fcrtl, fcrth;
int i;
/* Validate the water mark configuration. */
- if (!hw->fc.pause_time) {
- ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
- goto out;
- }
+ if (!hw->fc.pause_time)
+ return IXGBE_ERR_INVALID_LINK_SETTINGS;
/* Low water mark of zero causes XOFF floods */
for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
if (!hw->fc.low_water[i] ||
hw->fc.low_water[i] >= hw->fc.high_water[i]) {
hw_dbg(hw, "Invalid water mark configuration\n");
- ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
- goto out;
+ return IXGBE_ERR_INVALID_LINK_SETTINGS;
}
}
}
break;
default:
hw_dbg(hw, "Flow control param set incorrectly\n");
- ret_val = IXGBE_ERR_CONFIG;
- goto out;
+ return IXGBE_ERR_CONFIG;
}
/* Set 802.3x based flow control settings. */
IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
-out:
- return ret_val;
+ return 0;
}
/**
static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
{
u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
- s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
+ s32 ret_val;
/*
* On multispeed fiber at 1g, bail out if
linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
(!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
- goto out;
+ return IXGBE_ERR_FC_NOT_NEGOTIATED;
pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
IXGBE_PCS1GANA_SYM_PAUSE,
IXGBE_PCS1GANA_ASM_PAUSE);
-out:
return ret_val;
}
static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
{
u32 links2, anlp1_reg, autoc_reg, links;
- s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
+ s32 ret_val;
/*
* On backplane, bail out if
*/
links = IXGBE_READ_REG(hw, IXGBE_LINKS);
if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
- goto out;
+ return IXGBE_ERR_FC_NOT_NEGOTIATED;
if (hw->mac.type == ixgbe_mac_82599EB) {
links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
- goto out;
+ return IXGBE_ERR_FC_NOT_NEGOTIATED;
}
/*
* Read the 10g AN autoc and LP ability registers and resolve
anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
-out:
return ret_val;
}
**/
static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
{
- s32 status = 0;
u32 i, poll;
u16 value;
/* Exit if master requests are blocked */
if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
ixgbe_removed(hw->hw_addr))
- goto out;
+ return 0;
/* Poll for master request bit to clear */
for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
udelay(100);
if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
- goto out;
+ return 0;
}
/*
udelay(100);
value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
if (ixgbe_removed(hw->hw_addr))
- goto out;
+ return 0;
if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
- goto out;
+ return 0;
}
hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
- status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
-
-out:
- return status;
+ return IXGBE_ERR_MASTER_REQUESTS_PENDING;
}
/**
bool link_up = false;
u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
- s32 ret_val = 0;
bool locked = false;
+ s32 ret_val;
/*
* Link must be up to auto-blink the LEDs;
if (!link_up) {
ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
if (ret_val)
- goto out;
+ return ret_val;
autoc_reg |= IXGBE_AUTOC_AN_RESTART;
autoc_reg |= IXGBE_AUTOC_FLU;
ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
if (ret_val)
- goto out;
+ return ret_val;
IXGBE_WRITE_FLUSH(hw);
IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
IXGBE_WRITE_FLUSH(hw);
-out:
- return ret_val;
+ return 0;
}
/**
{
u32 autoc_reg = 0;
u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
- s32 ret_val = 0;
bool locked = false;
+ s32 ret_val;
ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
if (ret_val)
- goto out;
+ return ret_val;
autoc_reg &= ~IXGBE_AUTOC_FLU;
autoc_reg |= IXGBE_AUTOC_AN_RESTART;
ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
if (ret_val)
- goto out;
+ return ret_val;
led_reg &= ~IXGBE_LED_MODE_MASK(index);
led_reg &= ~IXGBE_LED_BLINK(index);
IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
IXGBE_WRITE_FLUSH(hw);
-out:
- return ret_val;
+ return 0;
}
/**
**/
u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
{
- u16 msix_count = 1;
+ u16 msix_count;
u16 max_msix_count;
u16 pcie_offset;
max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
break;
default:
- return msix_count;
+ return 1;
}
msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset);
mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
if (ixgbe_removed(hw->hw_addr))
- goto done;
+ return 0;
if (!mpsar_lo && !mpsar_hi)
- goto done;
+ return 0;
if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
if (mpsar_lo) {
/* was that the last pool using this rar? */
if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
hw->mac.ops.clear_rar(hw, rar);
-done:
return 0;
}
if ((alt_san_mac_blk_offset == 0) ||
(alt_san_mac_blk_offset == 0xFFFF))
- goto wwn_prefix_out;
+ return 0;
/* check capability in alternative san mac address block */
offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
if (hw->eeprom.ops.read(hw, offset, &caps))
goto wwn_prefix_err;
if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
- goto wwn_prefix_out;
+ return 0;
/* get the corresponding prefix for WWNN/WWPN */
offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
goto wwn_prefix_err;
-wwn_prefix_out:
return 0;
wwn_prefix_err:
u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
u8 buf_len, dword_len;
- s32 ret_val = 0;
-
if (length == 0 || length & 0x3 ||
length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
hw_dbg(hw, "Buffer length failure.\n");
- ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
- goto out;
+ return IXGBE_ERR_HOST_INTERFACE_COMMAND;
}
/* Check that the host interface is enabled. */
hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
if ((hicr & IXGBE_HICR_EN) == 0) {
hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
- ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
- goto out;
+ return IXGBE_ERR_HOST_INTERFACE_COMMAND;
}
/* Calculate length in DWORDs */
if (i == IXGBE_HI_COMMAND_TIMEOUT ||
(!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
hw_dbg(hw, "Command has failed with no status valid.\n");
- ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
- goto out;
+ return IXGBE_ERR_HOST_INTERFACE_COMMAND;
}
/* Calculate length in DWORDs */
/* If there is any thing in data position pull it in */
buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
if (buf_len == 0)
- goto out;
+ return 0;
if (length < (buf_len + hdr_size)) {
hw_dbg(hw, "Buffer not large enough for reply message.\n");
- ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
- goto out;
+ return IXGBE_ERR_HOST_INTERFACE_COMMAND;
}
/* Calculate length in DWORDs, add 3 for odd lengths */
le32_to_cpus(&buffer[bi]);
}
-out:
- return ret_val;
+ return 0;
}
/**
{
struct ixgbe_hic_drv_info fw_cmd;
int i;
- s32 ret_val = 0;
+ s32 ret_val;
- if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) != 0) {
- ret_val = IXGBE_ERR_SWFW_SYNC;
- goto out;
- }
+ if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM))
+ return IXGBE_ERR_SWFW_SYNC;
fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
}
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
-out:
return ret_val;
}
static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
u16 *ets_offset)
{
- s32 status = 0;
+ s32 status;
status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
if (status)
- goto out;
+ return status;
- if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) {
- status = IXGBE_NOT_IMPLEMENTED;
- goto out;
- }
+ if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF))
+ return IXGBE_NOT_IMPLEMENTED;
status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
if (status)
- goto out;
+ return status;
- if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) {
- status = IXGBE_NOT_IMPLEMENTED;
- goto out;
- }
+ if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED)
+ return IXGBE_NOT_IMPLEMENTED;
-out:
- return status;
+ return 0;
}
/**
**/
s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
{
- s32 status = 0;
+ s32 status;
u16 ets_offset;
u16 ets_cfg;
u16 ets_sensor;
struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
/* Only support thermal sensors attached to physical port 0 */
- if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
- status = IXGBE_NOT_IMPLEMENTED;
- goto out;
- }
+ if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
+ return IXGBE_NOT_IMPLEMENTED;
status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
if (status)
- goto out;
+ return status;
num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
if (num_sensors > IXGBE_MAX_SENSORS)
status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
&ets_sensor);
if (status)
- goto out;
+ return status;
sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
IXGBE_ETS_DATA_INDEX_SHIFT);
IXGBE_I2C_THERMAL_SENSOR_ADDR,
&data->sensor[i].temp);
if (status)
- goto out;
+ return status;
}
}
-out:
- return status;
+
+ return 0;
}
/**
**/
s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
{
- s32 status = 0;
+ s32 status;
u16 ets_offset;
u16 ets_cfg;
u16 ets_sensor;
memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
/* Only support thermal sensors attached to physical port 0 */
- if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
- status = IXGBE_NOT_IMPLEMENTED;
- goto out;
- }
+ if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
+ return IXGBE_NOT_IMPLEMENTED;
status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
if (status)
- goto out;
+ return status;
low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
IXGBE_ETS_LTHRES_DELTA_SHIFT);
data->sensor[i].caution_thresh = therm_limit;
data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
}
-out:
- return status;
+
+ return 0;
}
/*******************************************************************************
Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2013 Intel Corporation.
+ Copyright(c) 1999 - 2014 Intel Corporation.
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
int min_credit;
int min_multiplier;
int min_percent = 100;
- s32 ret_val = 0;
/* Initialization values default for Tx settings */
u32 credit_refill = 0;
u32 credit_max = 0;
u8 bw_percent = 0;
u8 i;
- if (dcb_config == NULL) {
- ret_val = DCB_ERR_CONFIG;
- goto out;
- }
+ if (!dcb_config)
+ return DCB_ERR_CONFIG;
min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) /
DCB_CREDIT_QUANTUM;
p->data_credits_max = (u16)credit_max;
}
-out:
- return ret_val;
+ return 0;
}
void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en)
/* If tc is 0 then DCB is likely not enabled or supported */
if (!tc)
- goto out;
+ return 0;
/*
* Test from maximum TC to 1 and report the first match we find. If
if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap)
break;
}
-out:
+
return tc;
}
s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
struct ixgbe_dcb_config *dcb_config)
{
- s32 ret = 0;
u8 pfc_en;
u8 ptype[MAX_TRAFFIC_CLASS];
u8 bwgid[MAX_TRAFFIC_CLASS];
switch (hw->mac.type) {
case ixgbe_mac_82598EB:
- ret = ixgbe_dcb_hw_config_82598(hw, pfc_en, refill, max,
- bwgid, ptype);
- break;
+ return ixgbe_dcb_hw_config_82598(hw, pfc_en, refill, max,
+ bwgid, ptype);
case ixgbe_mac_82599EB:
case ixgbe_mac_X540:
- ret = ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max,
- bwgid, ptype, prio_tc);
- break;
+ return ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max,
+ bwgid, ptype, prio_tc);
default:
break;
}
- return ret;
+ return 0;
}
/* Helper routines to abstract HW specifics from DCB netlink ops */
s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
{
- int ret = -EINVAL;
-
switch (hw->mac.type) {
case ixgbe_mac_82598EB:
- ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
- break;
+ return ixgbe_dcb_config_pfc_82598(hw, pfc_en);
case ixgbe_mac_82599EB:
case ixgbe_mac_X540:
- ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc);
- break;
+ return ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc);
default:
break;
}
- return ret;
+ return -EINVAL;
}
s32 ixgbe_dcb_hw_ets(struct ixgbe_hw *hw, struct ieee_ets *ets, int max_frame)
/*******************************************************************************
Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2013 Intel Corporation.
+ Copyright(c) 1999 - 2014 Intel Corporation.
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
static u8 ixgbe_dcbnl_set_state(struct net_device *netdev, u8 state)
{
struct ixgbe_adapter *adapter = netdev_priv(netdev);
- int err = 0;
/* Fail command if not in CEE mode */
if (!(adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE))
/* verify there is something to do, if not then exit */
if (!state == !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
- goto out;
+ return 0;
- err = ixgbe_setup_tc(netdev,
- state ? adapter->dcb_cfg.num_tcs.pg_tcs : 0);
-out:
- return !!err;
+ return !!ixgbe_setup_tc(netdev,
+ state ? adapter->dcb_cfg.num_tcs.pg_tcs : 0);
}
static void ixgbe_dcbnl_get_perm_hw_addr(struct net_device *netdev,
/* Fail command if not in CEE mode */
if (!(adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE))
- return ret;
+ return DCB_NO_HW_CHG;
adapter->dcb_set_bitmap |= ixgbe_copy_dcb_cfg(adapter,
MAX_TRAFFIC_CLASS);
if (!adapter->dcb_set_bitmap)
- return ret;
+ return DCB_NO_HW_CHG;
if (adapter->dcb_set_bitmap & (BIT_PG_TX|BIT_PG_RX)) {
u16 refill[MAX_TRAFFIC_CLASS], max[MAX_TRAFFIC_CLASS];
{
struct ixgbe_adapter *adapter = netdev_priv(dev);
int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
- int i, err = 0;
+ int i, err;
__u8 max_tc = 0;
__u8 map_chg = 0;
if (max_tc > adapter->dcb_cfg.num_tcs.pg_tcs)
return -EINVAL;
- if (max_tc != netdev_get_num_tc(dev))
+ if (max_tc != netdev_get_num_tc(dev)) {
err = ixgbe_setup_tc(dev, max_tc);
- else if (map_chg)
+ if (err)
+ return err;
+ } else if (map_chg) {
ixgbe_dcbnl_devreset(dev);
+ }
- if (err)
- goto err_out;
-
- err = ixgbe_dcb_hw_ets(&adapter->hw, ets, max_frame);
-err_out:
- return err;
+ return ixgbe_dcb_hw_ets(&adapter->hw, ets, max_frame);
}
static int ixgbe_dcbnl_ieee_getpfc(struct net_device *dev,
struct dcb_app *app)
{
struct ixgbe_adapter *adapter = netdev_priv(dev);
- int err = -EINVAL;
+ int err;
if (!(adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE))
- return err;
+ return -EINVAL;
err = dcb_ieee_setapp(dev, app);
if (err)
u8 app_mask = dcb_ieee_getapp_mask(dev, app);
if (app_mask & (1 << adapter->fcoe.up))
- return err;
+ return 0;
adapter->fcoe.up = app->priority;
ixgbe_dcbnl_devreset(dev);
u8 app_mask = dcb_ieee_getapp_mask(dev, app);
if (app_mask & (1 << adapter->fcoe.up))
- return err;
+ return 0;
adapter->fcoe.up = app_mask ?
ffs(app_mask) - 1 : IXGBE_FCOE_DEFTC;
/*******************************************************************************
Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2013 Intel Corporation.
+ Copyright(c) 1999 - 2014 Intel Corporation.
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
*/
int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid)
{
- int len = 0;
+ int len;
struct ixgbe_fcoe *fcoe;
struct ixgbe_adapter *adapter;
struct ixgbe_fcoe_ddp *ddp;
u32 fcbuff;
if (!netdev)
- goto out_ddp_put;
+ return 0;
if (xid >= IXGBE_FCOE_DDP_MAX)
- goto out_ddp_put;
+ return 0;
adapter = netdev_priv(netdev);
fcoe = &adapter->fcoe;
ddp = &fcoe->ddp[xid];
if (!ddp->udl)
- goto out_ddp_put;
+ return 0;
len = ddp->len;
/* if there an error, force to invalidate ddp context */
ixgbe_fcoe_clear_ddp(ddp);
-out_ddp_put:
return len;
}
xid = be16_to_cpu(fh->fh_rx_id);
if (xid >= IXGBE_FCOE_DDP_MAX)
- goto ddp_out;
+ return -EINVAL;
fcoe = &adapter->fcoe;
ddp = &fcoe->ddp[xid];
if (!ddp->udl)
- goto ddp_out;
+ return -EINVAL;
ddp_err = ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_FCEOFE |
IXGBE_RXDADV_ERR_FCERR);
if (ddp_err)
- goto ddp_out;
+ return -EINVAL;
switch (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_FCSTAT)) {
/* return 0 to bypass going to ULD for DDPed data */
crc = (struct fcoe_crc_eof *)skb_put(skb, sizeof(*crc));
crc->fcoe_eof = FC_EOF_T;
}
-ddp_out:
+
return rc;
}
*/
int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type)
{
- int rc = -EINVAL;
u16 prefix = 0xffff;
struct ixgbe_adapter *adapter = netdev_priv(netdev);
struct ixgbe_mac_info *mac = &adapter->hw.mac;
((u64) mac->san_addr[3] << 16) |
((u64) mac->san_addr[4] << 8) |
((u64) mac->san_addr[5]);
- rc = 0;
+ return 0;
}
- return rc;
+ return -EINVAL;
}
/**
/* Print TX Ring Summary */
if (!netdev || !netif_running(netdev))
- goto exit;
+ return;
dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
pr_info(" %s %s %s %s\n",
/* Print RX Rings */
if (!netif_msg_rx_status(adapter))
- goto exit;
+ return;
dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
}
}
-
-exit:
- return;
}
static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
u32 tx_done = ixgbe_get_tx_completed(tx_ring);
u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
- bool ret = false;
clear_check_for_tx_hang(tx_ring);
* run the check_tx_hang logic with a transmit completion
* pending but without time to complete it yet.
*/
- if ((tx_done_old == tx_done) && tx_pending) {
+ if (tx_done_old == tx_done && tx_pending)
/* make sure it is true for two checks in a row */
- ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
- &tx_ring->state);
- } else {
- /* update completed stats and continue */
- tx_ring->tx_stats.tx_done_old = tx_done;
- /* reset the countdown */
- clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
- }
+ return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
+ &tx_ring->state);
+ /* update completed stats and continue */
+ tx_ring->tx_stats.tx_done_old = tx_done;
+ /* reset the countdown */
+ clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
- return ret;
+ return false;
}
/**
ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
if (ret)
- goto link_cfg_out;
+ return ret;
speed = hw->phy.autoneg_advertised;
if ((!speed) && (hw->mac.ops.get_link_capabilities))
ret = hw->mac.ops.get_link_capabilities(hw, &speed,
&autoneg);
if (ret)
- goto link_cfg_out;
+ return ret;
if (hw->mac.ops.setup_link)
ret = hw->mac.ops.setup_link(hw, speed, link_up);
-link_cfg_out:
+
return ret;
}
s32 ixgbe_read_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)
{
struct ixgbe_mbx_info *mbx = &hw->mbx;
- s32 ret_val = IXGBE_ERR_MBX;
/* limit read to size of mailbox */
if (size > mbx->size)
size = mbx->size;
- if (mbx->ops.read)
- ret_val = mbx->ops.read(hw, msg, size, mbx_id);
+ if (!mbx->ops.read)
+ return IXGBE_ERR_MBX;
- return ret_val;
+ return mbx->ops.read(hw, msg, size, mbx_id);
}
/**
s32 ixgbe_check_for_msg(struct ixgbe_hw *hw, u16 mbx_id)
{
struct ixgbe_mbx_info *mbx = &hw->mbx;
- s32 ret_val = IXGBE_ERR_MBX;
- if (mbx->ops.check_for_msg)
- ret_val = mbx->ops.check_for_msg(hw, mbx_id);
+ if (!mbx->ops.check_for_msg)
+ return IXGBE_ERR_MBX;
- return ret_val;
+ return mbx->ops.check_for_msg(hw, mbx_id);
}
/**
s32 ixgbe_check_for_ack(struct ixgbe_hw *hw, u16 mbx_id)
{
struct ixgbe_mbx_info *mbx = &hw->mbx;
- s32 ret_val = IXGBE_ERR_MBX;
- if (mbx->ops.check_for_ack)
- ret_val = mbx->ops.check_for_ack(hw, mbx_id);
+ if (!mbx->ops.check_for_ack)
+ return IXGBE_ERR_MBX;
- return ret_val;
+ return mbx->ops.check_for_ack(hw, mbx_id);
}
/**
s32 ixgbe_check_for_rst(struct ixgbe_hw *hw, u16 mbx_id)
{
struct ixgbe_mbx_info *mbx = &hw->mbx;
- s32 ret_val = IXGBE_ERR_MBX;
- if (mbx->ops.check_for_rst)
- ret_val = mbx->ops.check_for_rst(hw, mbx_id);
+ if (!mbx->ops.check_for_rst)
+ return IXGBE_ERR_MBX;
- return ret_val;
+ return mbx->ops.check_for_rst(hw, mbx_id);
}
/**
int countdown = mbx->timeout;
if (!countdown || !mbx->ops.check_for_msg)
- goto out;
+ return IXGBE_ERR_MBX;
- while (countdown && mbx->ops.check_for_msg(hw, mbx_id)) {
+ while (mbx->ops.check_for_msg(hw, mbx_id)) {
countdown--;
if (!countdown)
- break;
+ return IXGBE_ERR_MBX;
udelay(mbx->usec_delay);
}
-out:
- return countdown ? 0 : IXGBE_ERR_MBX;
+ return 0;
}
/**
int countdown = mbx->timeout;
if (!countdown || !mbx->ops.check_for_ack)
- goto out;
+ return IXGBE_ERR_MBX;
- while (countdown && mbx->ops.check_for_ack(hw, mbx_id)) {
+ while (mbx->ops.check_for_ack(hw, mbx_id)) {
countdown--;
if (!countdown)
- break;
+ return IXGBE_ERR_MBX;
udelay(mbx->usec_delay);
}
-out:
- return countdown ? 0 : IXGBE_ERR_MBX;
+ return 0;
}
/**
u16 mbx_id)
{
struct ixgbe_mbx_info *mbx = &hw->mbx;
- s32 ret_val = IXGBE_ERR_MBX;
+ s32 ret_val;
if (!mbx->ops.read)
- goto out;
+ return IXGBE_ERR_MBX;
ret_val = ixgbe_poll_for_msg(hw, mbx_id);
+ if (ret_val)
+ return ret_val;
- /* if ack received read message, otherwise we timed out */
- if (!ret_val)
- ret_val = mbx->ops.read(hw, msg, size, mbx_id);
-out:
- return ret_val;
+ /* if ack received read message */
+ return mbx->ops.read(hw, msg, size, mbx_id);
}
/**
u16 mbx_id)
{
struct ixgbe_mbx_info *mbx = &hw->mbx;
- s32 ret_val = IXGBE_ERR_MBX;
+ s32 ret_val;
/* exit if either we can't write or there isn't a defined timeout */
if (!mbx->ops.write || !mbx->timeout)
- goto out;
+ return IXGBE_ERR_MBX;
/* send msg */
ret_val = mbx->ops.write(hw, msg, size, mbx_id);
+ if (ret_val)
+ return ret_val;
/* if msg sent wait until we receive an ack */
- if (!ret_val)
- ret_val = ixgbe_poll_for_ack(hw, mbx_id);
-out:
- return ret_val;
+ return ixgbe_poll_for_ack(hw, mbx_id);
}
static s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index)
{
u32 mbvficr = IXGBE_READ_REG(hw, IXGBE_MBVFICR(index));
- s32 ret_val = IXGBE_ERR_MBX;
if (mbvficr & mask) {
- ret_val = 0;
IXGBE_WRITE_REG(hw, IXGBE_MBVFICR(index), mask);
+ return 0;
}
- return ret_val;
+ return IXGBE_ERR_MBX;
}
/**
**/
static s32 ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, u16 vf_number)
{
- s32 ret_val = IXGBE_ERR_MBX;
s32 index = IXGBE_MBVFICR_INDEX(vf_number);
u32 vf_bit = vf_number % 16;
if (!ixgbe_check_for_bit_pf(hw, IXGBE_MBVFICR_VFREQ_VF1 << vf_bit,
index)) {
- ret_val = 0;
hw->mbx.stats.reqs++;
+ return 0;
}
- return ret_val;
+ return IXGBE_ERR_MBX;
}
/**
**/
static s32 ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, u16 vf_number)
{
- s32 ret_val = IXGBE_ERR_MBX;
s32 index = IXGBE_MBVFICR_INDEX(vf_number);
u32 vf_bit = vf_number % 16;
if (!ixgbe_check_for_bit_pf(hw, IXGBE_MBVFICR_VFACK_VF1 << vf_bit,
index)) {
- ret_val = 0;
hw->mbx.stats.acks++;
+ return 0;
}
- return ret_val;
+ return IXGBE_ERR_MBX;
}
/**
u32 reg_offset = (vf_number < 32) ? 0 : 1;
u32 vf_shift = vf_number % 32;
u32 vflre = 0;
- s32 ret_val = IXGBE_ERR_MBX;
switch (hw->mac.type) {
case ixgbe_mac_82599EB:
}
if (vflre & (1 << vf_shift)) {
- ret_val = 0;
IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift));
hw->mbx.stats.rsts++;
+ return 0;
}
- return ret_val;
+ return IXGBE_ERR_MBX;
}
/**
**/
static s32 ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, u16 vf_number)
{
- s32 ret_val = IXGBE_ERR_MBX;
u32 p2v_mailbox;
/* Take ownership of the buffer */
/* reserve mailbox for vf use */
p2v_mailbox = IXGBE_READ_REG(hw, IXGBE_PFMAILBOX(vf_number));
if (p2v_mailbox & IXGBE_PFMAILBOX_PFU)
- ret_val = 0;
+ return 0;
- return ret_val;
+ return IXGBE_ERR_MBX;
}
/**
/* lock the mailbox to prevent pf/vf race condition */
ret_val = ixgbe_obtain_mbx_lock_pf(hw, vf_number);
if (ret_val)
- goto out_no_write;
+ return ret_val;
/* flush msg and acks as we are overwriting the message buffer */
ixgbe_check_for_msg_pf(hw, vf_number);
/* update stats */
hw->mbx.stats.msgs_tx++;
-out_no_write:
- return ret_val;
-
+ return 0;
}
/**
/* lock the mailbox to prevent pf/vf race condition */
ret_val = ixgbe_obtain_mbx_lock_pf(hw, vf_number);
if (ret_val)
- goto out_no_read;
+ return ret_val;
/* copy the message to the mailbox memory buffer */
for (i = 0; i < size; i++)
/* update stats */
hw->mbx.stats.msgs_rx++;
-out_no_read:
- return ret_val;
+ return 0;
}
#ifdef CONFIG_PCI_IOV
**/
s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
{
- s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
u32 phy_addr;
u16 ext_ability = 0;
ixgbe_phy_generic;
}
- status = 0;
- break;
+ return 0;
}
}
/* clear value if nothing found */
- if (status != 0)
- hw->phy.mdio.prtad = 0;
- } else {
- status = 0;
+ hw->phy.mdio.prtad = 0;
+ return IXGBE_ERR_PHY_ADDR_INVALID;
}
-
- return status;
+ return 0;
}
/**
status = ixgbe_identify_phy_generic(hw);
if (status != 0 || hw->phy.type == ixgbe_phy_none)
- goto out;
+ return status;
/* Don't reset PHY if it's shut down due to overtemp. */
if (!hw->phy.reset_if_overtemp &&
(IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
- goto out;
+ return 0;
/* Blocked by MNG FW so bail */
if (ixgbe_check_reset_blocked(hw))
- goto out;
+ return 0;
/*
* Perform soft PHY reset to the PHY_XS.
}
if (ctrl & MDIO_CTRL1_RESET) {
- status = IXGBE_ERR_RESET_FAILED;
hw_dbg(hw, "PHY reset polling failed to complete.\n");
+ return IXGBE_ERR_RESET_FAILED;
}
-out:
- return status;
+ return 0;
}
/**
phy_data);
hw->mac.ops.release_swfw_sync(hw, gssr);
} else {
- status = IXGBE_ERR_SWFW_SYNC;
+ return IXGBE_ERR_SWFW_SYNC;
}
return status;
phy_data);
hw->mac.ops.release_swfw_sync(hw, gssr);
} else {
- status = IXGBE_ERR_SWFW_SYNC;
+ return IXGBE_ERR_SWFW_SYNC;
}
return status;
/* Blocked by MNG FW so don't reset PHY */
if (ixgbe_check_reset_blocked(hw))
- return status;
+ return 0;
/* Restart PHY autonegotiation and wait for completion */
hw->phy.ops.read_reg(hw, MDIO_CTRL1,
}
if (time_out == max_time_out) {
- status = IXGBE_ERR_LINK_SETUP;
hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out\n");
+ return IXGBE_ERR_LINK_SETUP;
}
return status;
ixgbe_link_speed *speed,
bool *autoneg)
{
- s32 status = IXGBE_ERR_LINK_SETUP;
+ s32 status;
u16 speed_ability;
*speed = 0;
s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
bool *link_up)
{
- s32 status = 0;
+ s32 status;
u32 time_out;
u32 max_time_out = 10;
u16 phy_link = 0;
**/
s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
{
- s32 status = 0;
+ s32 status;
u32 time_out;
u32 max_time_out = 10;
u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
/* Blocked by MNG FW so don't reset PHY */
if (ixgbe_check_reset_blocked(hw))
- return status;
+ return 0;
/* Restart PHY autonegotiation and wait for completion */
hw->phy.ops.read_reg(hw, MDIO_CTRL1,
}
if (time_out == max_time_out) {
- status = IXGBE_ERR_LINK_SETUP;
hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out\n");
+ return IXGBE_ERR_LINK_SETUP;
}
return status;
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
u16 *firmware_version)
{
- s32 status = 0;
+ s32 status;
status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
MDIO_MMD_VEND1,
s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
u16 *firmware_version)
{
- s32 status = 0;
+ s32 status;
status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
MDIO_MMD_VEND1,
bool end_data = false;
u16 list_offset, data_offset;
u16 phy_data = 0;
- s32 ret_val = 0;
+ s32 ret_val;
u32 i;
/* Blocked by MNG FW so bail */
if (ixgbe_check_reset_blocked(hw))
- goto out;
+ return 0;
hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
if ((phy_data & MDIO_CTRL1_RESET) != 0) {
hw_dbg(hw, "PHY reset did not complete.\n");
- ret_val = IXGBE_ERR_PHY;
- goto out;
+ return IXGBE_ERR_PHY;
}
/* Get init offsets */
ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
&data_offset);
- if (ret_val != 0)
- goto out;
+ if (ret_val)
+ return ret_val;
ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
data_offset++;
hw_dbg(hw, "SOL\n");
} else {
hw_dbg(hw, "Bad control value\n");
- ret_val = IXGBE_ERR_PHY;
- goto out;
+ return IXGBE_ERR_PHY;
}
break;
default:
hw_dbg(hw, "Bad control type\n");
- ret_val = IXGBE_ERR_PHY;
- goto out;
+ return IXGBE_ERR_PHY;
}
}
-out:
return ret_val;
err_eeprom:
**/
s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
{
- s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
-
switch (hw->mac.ops.get_media_type(hw)) {
case ixgbe_media_type_fiber:
- status = ixgbe_identify_sfp_module_generic(hw);
- break;
+ return ixgbe_identify_sfp_module_generic(hw);
case ixgbe_media_type_fiber_qsfp:
- status = ixgbe_identify_qsfp_module_generic(hw);
- break;
+ return ixgbe_identify_qsfp_module_generic(hw);
default:
hw->phy.sfp_type = ixgbe_sfp_type_not_present;
- status = IXGBE_ERR_SFP_NOT_PRESENT;
- break;
+ return IXGBE_ERR_SFP_NOT_PRESENT;
}
- return status;
+ return IXGBE_ERR_SFP_NOT_PRESENT;
}
/**
* ixgbe_identify_sfp_module_generic - Identifies SFP modules
* @hw: pointer to hardware structure
-*
+ *
* Searches for and identifies the SFP module and assigns appropriate PHY type.
**/
s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
{
struct ixgbe_adapter *adapter = hw->back;
- s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
+ s32 status;
u32 vendor_oui = 0;
enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
u8 identifier = 0;
if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
hw->phy.sfp_type = ixgbe_sfp_type_not_present;
- status = IXGBE_ERR_SFP_NOT_PRESENT;
- goto out;
+ return IXGBE_ERR_SFP_NOT_PRESENT;
}
status = hw->phy.ops.read_i2c_eeprom(hw,
IXGBE_SFF_IDENTIFIER,
&identifier);
- if (status != 0)
+ if (status)
goto err_read_i2c_eeprom;
/* LAN ID is needed for sfp_type determination */
if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
hw->phy.type = ixgbe_phy_sfp_unsupported;
- status = IXGBE_ERR_SFP_NOT_SUPPORTED;
- } else {
- status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_1GBE_COMP_CODES,
- &comp_codes_1g);
+ return IXGBE_ERR_SFP_NOT_SUPPORTED;
+ }
+ status = hw->phy.ops.read_i2c_eeprom(hw,
+ IXGBE_SFF_1GBE_COMP_CODES,
+ &comp_codes_1g);
- if (status != 0)
- goto err_read_i2c_eeprom;
+ if (status)
+ goto err_read_i2c_eeprom;
- status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_10GBE_COMP_CODES,
- &comp_codes_10g);
+ status = hw->phy.ops.read_i2c_eeprom(hw,
+ IXGBE_SFF_10GBE_COMP_CODES,
+ &comp_codes_10g);
- if (status != 0)
- goto err_read_i2c_eeprom;
- status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_CABLE_TECHNOLOGY,
- &cable_tech);
+ if (status)
+ goto err_read_i2c_eeprom;
+ status = hw->phy.ops.read_i2c_eeprom(hw,
+ IXGBE_SFF_CABLE_TECHNOLOGY,
+ &cable_tech);
- if (status != 0)
- goto err_read_i2c_eeprom;
+ if (status)
+ goto err_read_i2c_eeprom;
- /* ID Module
- * =========
- * 0 SFP_DA_CU
- * 1 SFP_SR
- * 2 SFP_LR
- * 3 SFP_DA_CORE0 - 82599-specific
- * 4 SFP_DA_CORE1 - 82599-specific
- * 5 SFP_SR/LR_CORE0 - 82599-specific
- * 6 SFP_SR/LR_CORE1 - 82599-specific
- * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
- * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
- * 9 SFP_1g_cu_CORE0 - 82599-specific
- * 10 SFP_1g_cu_CORE1 - 82599-specific
- * 11 SFP_1g_sx_CORE0 - 82599-specific
- * 12 SFP_1g_sx_CORE1 - 82599-specific
- */
- if (hw->mac.type == ixgbe_mac_82598EB) {
- if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
- hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
- else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
- hw->phy.sfp_type = ixgbe_sfp_type_sr;
- else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
- hw->phy.sfp_type = ixgbe_sfp_type_lr;
+ /* ID Module
+ * =========
+ * 0 SFP_DA_CU
+ * 1 SFP_SR
+ * 2 SFP_LR
+ * 3 SFP_DA_CORE0 - 82599-specific
+ * 4 SFP_DA_CORE1 - 82599-specific
+ * 5 SFP_SR/LR_CORE0 - 82599-specific
+ * 6 SFP_SR/LR_CORE1 - 82599-specific
+ * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
+ * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
+ * 9 SFP_1g_cu_CORE0 - 82599-specific
+ * 10 SFP_1g_cu_CORE1 - 82599-specific
+ * 11 SFP_1g_sx_CORE0 - 82599-specific
+ * 12 SFP_1g_sx_CORE1 - 82599-specific
+ */
+ if (hw->mac.type == ixgbe_mac_82598EB) {
+ if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
+ hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
+ else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
+ hw->phy.sfp_type = ixgbe_sfp_type_sr;
+ else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
+ hw->phy.sfp_type = ixgbe_sfp_type_lr;
+ else
+ hw->phy.sfp_type = ixgbe_sfp_type_unknown;
+ } else if (hw->mac.type == ixgbe_mac_82599EB) {
+ if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
+ if (hw->bus.lan_id == 0)
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_da_cu_core0;
else
- hw->phy.sfp_type = ixgbe_sfp_type_unknown;
- } else if (hw->mac.type == ixgbe_mac_82599EB) {
- if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type =
- ixgbe_sfp_type_da_cu_core0;
- else
- hw->phy.sfp_type =
- ixgbe_sfp_type_da_cu_core1;
- } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
- hw->phy.ops.read_i2c_eeprom(
- hw, IXGBE_SFF_CABLE_SPEC_COMP,
- &cable_spec);
- if (cable_spec &
- IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type =
- ixgbe_sfp_type_da_act_lmt_core0;
- else
- hw->phy.sfp_type =
- ixgbe_sfp_type_da_act_lmt_core1;
- } else {
- hw->phy.sfp_type =
- ixgbe_sfp_type_unknown;
- }
- } else if (comp_codes_10g &
- (IXGBE_SFF_10GBASESR_CAPABLE |
- IXGBE_SFF_10GBASELR_CAPABLE)) {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type =
- ixgbe_sfp_type_srlr_core0;
- else
- hw->phy.sfp_type =
- ixgbe_sfp_type_srlr_core1;
- } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type =
- ixgbe_sfp_type_1g_cu_core0;
- else
- hw->phy.sfp_type =
- ixgbe_sfp_type_1g_cu_core1;
- } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type =
- ixgbe_sfp_type_1g_sx_core0;
- else
- hw->phy.sfp_type =
- ixgbe_sfp_type_1g_sx_core1;
- } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_da_cu_core1;
+ } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
+ hw->phy.ops.read_i2c_eeprom(
+ hw, IXGBE_SFF_CABLE_SPEC_COMP,
+ &cable_spec);
+ if (cable_spec &
+ IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
if (hw->bus.lan_id == 0)
hw->phy.sfp_type =
- ixgbe_sfp_type_1g_lx_core0;
+ ixgbe_sfp_type_da_act_lmt_core0;
else
hw->phy.sfp_type =
- ixgbe_sfp_type_1g_lx_core1;
+ ixgbe_sfp_type_da_act_lmt_core1;
} else {
- hw->phy.sfp_type = ixgbe_sfp_type_unknown;
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_unknown;
}
+ } else if (comp_codes_10g &
+ (IXGBE_SFF_10GBASESR_CAPABLE |
+ IXGBE_SFF_10GBASELR_CAPABLE)) {
+ if (hw->bus.lan_id == 0)
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_srlr_core0;
+ else
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_srlr_core1;
+ } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
+ if (hw->bus.lan_id == 0)
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_1g_cu_core0;
+ else
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_1g_cu_core1;
+ } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
+ if (hw->bus.lan_id == 0)
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_1g_sx_core0;
+ else
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_1g_sx_core1;
+ } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
+ if (hw->bus.lan_id == 0)
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_1g_lx_core0;
+ else
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_1g_lx_core1;
+ } else {
+ hw->phy.sfp_type = ixgbe_sfp_type_unknown;
}
+ }
- if (hw->phy.sfp_type != stored_sfp_type)
- hw->phy.sfp_setup_needed = true;
-
- /* Determine if the SFP+ PHY is dual speed or not. */
- hw->phy.multispeed_fiber = false;
- if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
- (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
- ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
- (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
- hw->phy.multispeed_fiber = true;
-
- /* Determine PHY vendor */
- if (hw->phy.type != ixgbe_phy_nl) {
- hw->phy.id = identifier;
- status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_VENDOR_OUI_BYTE0,
- &oui_bytes[0]);
-
- if (status != 0)
- goto err_read_i2c_eeprom;
-
- status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_VENDOR_OUI_BYTE1,
- &oui_bytes[1]);
-
- if (status != 0)
- goto err_read_i2c_eeprom;
-
- status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_VENDOR_OUI_BYTE2,
- &oui_bytes[2]);
-
- if (status != 0)
- goto err_read_i2c_eeprom;
-
- vendor_oui =
- ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
- (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
- (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
-
- switch (vendor_oui) {
- case IXGBE_SFF_VENDOR_OUI_TYCO:
- if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
- hw->phy.type =
- ixgbe_phy_sfp_passive_tyco;
- break;
- case IXGBE_SFF_VENDOR_OUI_FTL:
- if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
- hw->phy.type = ixgbe_phy_sfp_ftl_active;
- else
- hw->phy.type = ixgbe_phy_sfp_ftl;
- break;
- case IXGBE_SFF_VENDOR_OUI_AVAGO:
- hw->phy.type = ixgbe_phy_sfp_avago;
- break;
- case IXGBE_SFF_VENDOR_OUI_INTEL:
- hw->phy.type = ixgbe_phy_sfp_intel;
- break;
- default:
- if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
- hw->phy.type =
- ixgbe_phy_sfp_passive_unknown;
- else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
- hw->phy.type =
- ixgbe_phy_sfp_active_unknown;
- else
- hw->phy.type = ixgbe_phy_sfp_unknown;
- break;
- }
- }
+ if (hw->phy.sfp_type != stored_sfp_type)
+ hw->phy.sfp_setup_needed = true;
- /* Allow any DA cable vendor */
- if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
- IXGBE_SFF_DA_ACTIVE_CABLE)) {
- status = 0;
- goto out;
- }
+ /* Determine if the SFP+ PHY is dual speed or not. */
+ hw->phy.multispeed_fiber = false;
+ if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
+ (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
+ ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
+ (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
+ hw->phy.multispeed_fiber = true;
- /* Verify supported 1G SFP modules */
- if (comp_codes_10g == 0 &&
- !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
- hw->phy.type = ixgbe_phy_sfp_unsupported;
- status = IXGBE_ERR_SFP_NOT_SUPPORTED;
- goto out;
- }
+ /* Determine PHY vendor */
+ if (hw->phy.type != ixgbe_phy_nl) {
+ hw->phy.id = identifier;
+ status = hw->phy.ops.read_i2c_eeprom(hw,
+ IXGBE_SFF_VENDOR_OUI_BYTE0,
+ &oui_bytes[0]);
- /* Anything else 82598-based is supported */
- if (hw->mac.type == ixgbe_mac_82598EB) {
- status = 0;
- goto out;
- }
+ if (status != 0)
+ goto err_read_i2c_eeprom;
- hw->mac.ops.get_device_caps(hw, &enforce_sfp);
- if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
- !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
- /* Make sure we're a supported PHY type */
- if (hw->phy.type == ixgbe_phy_sfp_intel) {
- status = 0;
- } else {
- if (hw->allow_unsupported_sfp) {
- e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
- status = 0;
- } else {
- hw_dbg(hw,
- "SFP+ module not supported\n");
- hw->phy.type =
- ixgbe_phy_sfp_unsupported;
- status = IXGBE_ERR_SFP_NOT_SUPPORTED;
- }
- }
- } else {
- status = 0;
+ status = hw->phy.ops.read_i2c_eeprom(hw,
+ IXGBE_SFF_VENDOR_OUI_BYTE1,
+ &oui_bytes[1]);
+
+ if (status != 0)
+ goto err_read_i2c_eeprom;
+
+ status = hw->phy.ops.read_i2c_eeprom(hw,
+ IXGBE_SFF_VENDOR_OUI_BYTE2,
+ &oui_bytes[2]);
+
+ if (status != 0)
+ goto err_read_i2c_eeprom;
+
+ vendor_oui =
+ ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
+ (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
+ (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
+
+ switch (vendor_oui) {
+ case IXGBE_SFF_VENDOR_OUI_TYCO:
+ if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
+ hw->phy.type =
+ ixgbe_phy_sfp_passive_tyco;
+ break;
+ case IXGBE_SFF_VENDOR_OUI_FTL:
+ if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
+ hw->phy.type = ixgbe_phy_sfp_ftl_active;
+ else
+ hw->phy.type = ixgbe_phy_sfp_ftl;
+ break;
+ case IXGBE_SFF_VENDOR_OUI_AVAGO:
+ hw->phy.type = ixgbe_phy_sfp_avago;
+ break;
+ case IXGBE_SFF_VENDOR_OUI_INTEL:
+ hw->phy.type = ixgbe_phy_sfp_intel;
+ break;
+ default:
+ if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
+ hw->phy.type =
+ ixgbe_phy_sfp_passive_unknown;
+ else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
+ hw->phy.type =
+ ixgbe_phy_sfp_active_unknown;
+ else
+ hw->phy.type = ixgbe_phy_sfp_unknown;
+ break;
}
}
-out:
- return status;
+ /* Allow any DA cable vendor */
+ if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
+ IXGBE_SFF_DA_ACTIVE_CABLE))
+ return 0;
+
+ /* Verify supported 1G SFP modules */
+ if (comp_codes_10g == 0 &&
+ !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
+ hw->phy.type = ixgbe_phy_sfp_unsupported;
+ return IXGBE_ERR_SFP_NOT_SUPPORTED;
+ }
+
+ /* Anything else 82598-based is supported */
+ if (hw->mac.type == ixgbe_mac_82598EB)
+ return 0;
+
+ hw->mac.ops.get_device_caps(hw, &enforce_sfp);
+ if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
+ !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
+ /* Make sure we're a supported PHY type */
+ if (hw->phy.type == ixgbe_phy_sfp_intel)
+ return 0;
+ if (hw->allow_unsupported_sfp) {
+ e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
+ return 0;
+ }
+ hw_dbg(hw, "SFP+ module not supported\n");
+ hw->phy.type = ixgbe_phy_sfp_unsupported;
+ return IXGBE_ERR_SFP_NOT_SUPPORTED;
+ }
+ return 0;
err_read_i2c_eeprom:
hw->phy.sfp_type = ixgbe_sfp_type_not_present;
static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
{
struct ixgbe_adapter *adapter = hw->back;
- s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
+ s32 status;
u32 vendor_oui = 0;
enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
u8 identifier = 0;
if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
hw->phy.sfp_type = ixgbe_sfp_type_not_present;
- status = IXGBE_ERR_SFP_NOT_PRESENT;
- goto out;
+ return IXGBE_ERR_SFP_NOT_PRESENT;
}
status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
hw->phy.type = ixgbe_phy_sfp_unsupported;
- status = IXGBE_ERR_SFP_NOT_SUPPORTED;
- goto out;
+ return IXGBE_ERR_SFP_NOT_SUPPORTED;
}
hw->phy.id = identifier;
} else {
/* unsupported module type */
hw->phy.type = ixgbe_phy_sfp_unsupported;
- status = IXGBE_ERR_SFP_NOT_SUPPORTED;
- goto out;
+ return IXGBE_ERR_SFP_NOT_SUPPORTED;
}
}
hw->mac.ops.get_device_caps(hw, &enforce_sfp);
if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
/* Make sure we're a supported PHY type */
- if (hw->phy.type == ixgbe_phy_qsfp_intel) {
- status = 0;
- } else {
- if (hw->allow_unsupported_sfp == true) {
- e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
- status = 0;
- } else {
- hw_dbg(hw,
- "QSFP module not supported\n");
- hw->phy.type =
- ixgbe_phy_sfp_unsupported;
- status = IXGBE_ERR_SFP_NOT_SUPPORTED;
- }
+ if (hw->phy.type == ixgbe_phy_qsfp_intel)
+ return 0;
+ if (hw->allow_unsupported_sfp) {
+ e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
+ return 0;
}
- } else {
- status = 0;
+ hw_dbg(hw, "QSFP module not supported\n");
+ hw->phy.type = ixgbe_phy_sfp_unsupported;
+ return IXGBE_ERR_SFP_NOT_SUPPORTED;
}
+ return 0;
}
-
-out:
- return status;
+ return 0;
err_read_i2c_eeprom:
hw->phy.sfp_type = ixgbe_sfp_type_not_present;
s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data)
{
- s32 status = 0;
+ s32 status;
u32 max_retry = 10;
u32 retry = 0;
u16 swfw_mask = 0;
swfw_mask = IXGBE_GSSR_PHY0_SM;
do {
- if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
- status = IXGBE_ERR_SWFW_SYNC;
- goto read_byte_out;
- }
+ if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
+ return IXGBE_ERR_SWFW_SYNC;
ixgbe_i2c_start(hw);
hw->mac.ops.release_swfw_sync(hw, swfw_mask);
-read_byte_out:
return status;
}
s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data)
{
- s32 status = 0;
+ s32 status;
u32 max_retry = 1;
u32 retry = 0;
u16 swfw_mask = 0;
else
swfw_mask = IXGBE_GSSR_PHY0_SM;
- if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
- status = IXGBE_ERR_SWFW_SYNC;
- goto write_byte_out;
- }
+ if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
+ return IXGBE_ERR_SWFW_SYNC;
do {
ixgbe_i2c_start(hw);
hw->mac.ops.release_swfw_sync(hw, swfw_mask);
-write_byte_out:
return status;
}
**/
static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
{
- s32 status = 0;
+ s32 status;
s32 i;
u32 i2cctl;
bool bit = false;
*/
udelay(IXGBE_I2C_T_LOW);
} else {
- status = IXGBE_ERR_I2C;
hw_dbg(hw, "I2C data was not set to %X\n", data);
+ return IXGBE_ERR_I2C;
}
- return status;
+ return 0;
}
/**
* ixgbe_raise_i2c_clk - Raises the I2C SCL clock
**/
static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
{
- s32 status = 0;
-
if (data)
*i2cctl |= IXGBE_I2C_DATA_OUT;
else
/* Verify data was set correctly */
*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
if (data != ixgbe_get_i2c_data(i2cctl)) {
- status = IXGBE_ERR_I2C;
hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
+ return IXGBE_ERR_I2C;
}
- return status;
+ return 0;
}
/**
**/
static bool ixgbe_get_i2c_data(u32 *i2cctl)
{
- bool data;
-
if (*i2cctl & IXGBE_I2C_DATA_IN)
- data = true;
- else
- data = false;
-
- return data;
+ return true;
+ return false;
}
/**
**/
s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
{
- s32 status = 0;
u16 phy_data = 0;
if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
- goto out;
+ return 0;
/* Check that the LASI temp alarm status was triggered */
hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
MDIO_MMD_PMAPMD, &phy_data);
if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
- goto out;
+ return 0;
- status = IXGBE_ERR_OVERTEMP;
-out:
- return status;
+ return IXGBE_ERR_OVERTEMP;
}
/*******************************************************************************
Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2013 Intel Corporation.
+ Copyright(c) 1999 - 2014 Intel Corporation.
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
if (pre_existing_vfs && pre_existing_vfs != num_vfs)
err = ixgbe_disable_sriov(adapter);
else if (pre_existing_vfs && pre_existing_vfs == num_vfs)
- goto out;
+ return num_vfs;
if (err)
- goto err_out;
+ return err;
/* While the SR-IOV capability structure reports total VFs to be
* 64 we limit the actual number that can be allocated to 63 so
* PF. The PCI bus driver already checks for other values out of
* range.
*/
- if (num_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
- err = -EPERM;
- goto err_out;
- }
+ if (num_vfs > IXGBE_MAX_VFS_DRV_LIMIT)
+ return -EPERM;
adapter->num_vfs = num_vfs;
err = __ixgbe_enable_sriov(adapter);
if (err)
- goto err_out;
+ return err;
for (i = 0; i < adapter->num_vfs; i++)
ixgbe_vf_configuration(dev, (i | 0x10000000));
err = pci_enable_sriov(dev, num_vfs);
if (err) {
e_dev_warn("Failed to enable PCI sriov: %d\n", err);
- goto err_out;
+ return err;
}
ixgbe_sriov_reinit(adapter);
-out:
return num_vfs;
-
-err_out:
- return err;
-#endif
+#else
return 0;
+#endif
}
static int ixgbe_pci_sriov_disable(struct pci_dev *dev)
if (!add && adapter->netdev->flags & IFF_PROMISC) {
reg_ndx = ixgbe_find_vlvf_entry(hw, vid);
if (reg_ndx < 0)
- goto out;
+ return err;
vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_ndx));
/* See if any other pools are set for this VLAN filter
* entry other than the PF.
ixgbe_set_vf_vlan(adapter, add, vid, VMDQ_P(0));
}
-out:
-
return err;
}
/* this is a message we already processed, do nothing */
if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
- return retval;
+ return 0;
/* flush the ack before we write any messages back */
IXGBE_WRITE_FLUSH(hw);
if (!adapter->vfinfo[vf].clear_to_send) {
msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
ixgbe_write_mbx(hw, msgbuf, 1, vf);
- return retval;
+ return 0;
}
switch ((msgbuf[0] & 0xFFFF)) {
/* Call adapter stop to disable tx/rx and clear interrupts */
status = hw->mac.ops.stop_adapter(hw);
- if (status != 0)
- goto reset_hw_out;
+ if (status)
+ return status;
/* flush pending Tx transactions */
ixgbe_clear_tx_pending(hw);
hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
&hw->mac.wwpn_prefix);
-reset_hw_out:
return status;
}
**/
static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
{
- s32 ret_val = 0;
+ s32 ret_val;
ret_val = ixgbe_start_hw_generic(hw);
- if (ret_val != 0)
- goto out;
+ if (ret_val)
+ return ret_val;
- ret_val = ixgbe_start_hw_gen2(hw);
-out:
- return ret_val;
+ return ixgbe_start_hw_gen2(hw);
}
/**
static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
{
u32 flup;
- s32 status = IXGBE_ERR_EEPROM;
+ s32 status;
status = ixgbe_poll_flash_update_done_X540(hw);
if (status == IXGBE_ERR_EEPROM) {
hw_dbg(hw, "Flash update time out\n");
- goto out;
+ return status;
}
flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
else
hw_dbg(hw, "Flash update time out\n");
}
-out:
+
return status;
}
{
u32 i;
u32 reg;
- s32 status = IXGBE_ERR_EEPROM;
for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
reg = IXGBE_READ_REG(hw, IXGBE_EEC);
- if (reg & IXGBE_EEC_FLUDONE) {
- status = 0;
- break;
- }
+ if (reg & IXGBE_EEC_FLUDONE)
+ return 0;
udelay(5);
}
- return status;
+ return IXGBE_ERR_EEPROM;
}
/**
projects / GitHub / MotorolaMobilityLLC / kernel-slsi.git / commitdiff