hdmitx: optimize hpll suspend

PD#165090: hdmitx: optimize hpll suspend

The BIT definition of RESET / ENABLE in G12A is different from
earlier chips.
HPLL suspend workflow:
1. set RESET as 1
2. delay 50us
3. set ENABLE as 0
Resume workflow is inverse, but no need anymore, it will be set
in set_disp_mode_auto().

Change-Id: Iefc7f7f026562f566c8a40325c74a53f46465b02
Signed-off-by: Zongdong Jiao <zongdong.jiao@amlogic.com>

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
index 29e1cddb8d51cc360b342d7ae892159c0d10605b..bd9ffba22d5ef447330d6899bcd26409794111ed 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
@@ -2483,6 +2483,7 @@ static int hdmitx_cntl(struct hdmitx_dev *hdev, unsigned int cmd,
                        /* G12A reset/enable bit position is different */
                        switch (hdev->chip_type) {
                        case MESON_CPU_ID_G12A:
+                       case MESON_CPU_ID_G12B:
                                hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 1, 29, 1);
                                udelay(50);
                                hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0, 28, 1);