drm/i915/dp: Don't turn CPT DP ports on too early

The docs say the port has to come on in training pattern 1; at this
point, though, ->DP is in normal mode.  The intent here is to wait
until the port is in fact sending data, but that doesn't happen since
we've broken the sequence the hardware expects, and the vblank wait will
time out and kvetch in the log.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8aecb072466b6cd34e16e8238ad634e5f5b2ec3f..dcc7ae6d414198a4a20b66eab61053a195d79b6e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1334,10 +1334,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
        u32 reg;
        uint32_t DP = intel_dp->DP;
 
-       /* Enable output, wait for it to become active */
-       I915_WRITE(intel_dp->output_reg, intel_dp->DP);
-       POSTING_READ(intel_dp->output_reg);
-       intel_wait_for_vblank(dev, intel_crtc->pipe);
+       /*
+        * On CPT we have to enable the port in training pattern 1, which
+        * will happen below in intel_dp_set_link_train.  Otherwise, enable
+        * the port and wait for it to become active.
+        */
+       if (!HAS_PCH_CPT(dev)) {
+               I915_WRITE(intel_dp->output_reg, intel_dp->DP);
+               POSTING_READ(intel_dp->output_reg);
+               intel_wait_for_vblank(dev, intel_crtc->pipe);
+       }
 
        /* Write the link configuration data */
        intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,