ARM: GIC: move gic_chip_data structure declaration to header
authorChanghwan Youn <chaos.youn@samsung.com>
Sat, 16 Jul 2011 01:49:47 +0000 (10:49 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Wed, 20 Jul 2011 14:28:22 +0000 (23:28 +0900)
Since Samsung EXYNOS4210 cannot support register banking in GIC,
so needs to update CPU interface base address.
The 'gic_chip_data' is used for it, this patch moves gic_chip_data
structure declaraton to arch/arm/include/asm/hardware/gic.h to use
it.

Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
arch/arm/common/gic.c
arch/arm/include/asm/hardware/gic.h

index 4ddd0a6ac7ff3d9db4f55b165c172ec144e90a51..23564edbd849f202a8ad06ee4e6fc1abe3bb57c4 100644 (file)
@@ -38,12 +38,6 @@ static DEFINE_SPINLOCK(irq_controller_lock);
 /* Address of GIC 0 CPU interface */
 void __iomem *gic_cpu_base_addr __read_mostly;
 
-struct gic_chip_data {
-       unsigned int irq_offset;
-       void __iomem *dist_base;
-       void __iomem *cpu_base;
-};
-
 /*
  * Supported arch specific GIC irq extension.
  * Default make them NULL.
index 0691f9dcc5006b262f71c6bbd832463b370aa886..435d3f86c708778c9ad8211451a1a1c2b75372fe 100644 (file)
@@ -41,6 +41,12 @@ void gic_secondary_init(unsigned int);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
 void gic_enable_ppi(unsigned int);
+
+struct gic_chip_data {
+       unsigned int irq_offset;
+       void __iomem *dist_base;
+       void __iomem *cpu_base;
+};
 #endif
 
 #endif