KVM: arm64: Log an error if trapping a read-from-write-only GICv3 access
authorMarc Zyngier <marc.zyngier@arm.com>
Fri, 9 Jun 2017 11:49:55 +0000 (12:49 +0100)
committerMarc Zyngier <marc.zyngier@arm.com>
Thu, 15 Jun 2017 08:45:06 +0000 (09:45 +0100)
A read-from-write-only GICv3 access should UNDEF at EL1. But since
we're in complete paranoia-land with broken CPUs, let's assume the
worse and gracefully handle the case.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
arch/arm64/kvm/sys_regs.c
virt/kvm/arm/hyp/vgic-v3-sr.c

index 0fe27024a2e1a749b2ba08fc3971c10f5ad5adc0..8d51c075966d91ad873790c9f9a8456289efba2b 100644 (file)
@@ -56,7 +56,8 @@
  */
 
 static bool read_from_write_only(struct kvm_vcpu *vcpu,
-                                const struct sys_reg_params *params)
+                                struct sys_reg_params *params,
+                                const struct sys_reg_desc *r)
 {
        WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
        print_sys_reg_instr(params);
@@ -93,7 +94,7 @@ static bool access_dcsw(struct kvm_vcpu *vcpu,
                        const struct sys_reg_desc *r)
 {
        if (!p->is_write)
-               return read_from_write_only(vcpu, p);
+               return read_from_write_only(vcpu, p, r);
 
        kvm_set_way_flush(vcpu);
        return true;
@@ -135,7 +136,7 @@ static bool access_gic_sgi(struct kvm_vcpu *vcpu,
                           const struct sys_reg_desc *r)
 {
        if (!p->is_write)
-               return read_from_write_only(vcpu, p);
+               return read_from_write_only(vcpu, p, r);
 
        vgic_v3_dispatch_sgi(vcpu, p->regval);
 
@@ -773,7 +774,7 @@ static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
                return trap_raz_wi(vcpu, p, r);
 
        if (!p->is_write)
-               return read_from_write_only(vcpu, p);
+               return read_from_write_only(vcpu, p, r);
 
        if (pmu_write_swinc_el0_disabled(vcpu))
                return false;
@@ -953,7 +954,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 
        { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
 
+       { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
+       { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
        { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
+       { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
        { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
 
        { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
index 15b557697086cbd6c56323741156de0a5c49b771..b26ce58b012a4d23259cf29758f36175479eaad1 100644 (file)
@@ -980,6 +980,8 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
                break;
        case SYS_ICC_EOIR0_EL1:
        case SYS_ICC_EOIR1_EL1:
+               if (unlikely(is_read))
+                       return 0;
                fn = __vgic_v3_write_eoir;
                break;
        case SYS_ICC_GRPEN1_EL1:
@@ -1039,6 +1041,8 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
                        fn = __vgic_v3_write_bpr0;
                break;
        case SYS_ICC_DIR_EL1:
+               if (unlikely(is_read))
+                       return 0;
                fn = __vgic_v3_write_dir;
                break;
        case SYS_ICC_RPR_EL1: