ARM: prima2: move to generic reset controller driver framework
authorBarry Song <Baohua.Song@csr.com>
Fri, 10 Jan 2014 03:15:42 +0000 (03:15 +0000)
committerBarry Song <Baohua.Song@csr.com>
Wed, 5 Mar 2014 02:33:47 +0000 (10:33 +0800)
this moves to generic IP module reset framework, and make other drivers
use common device_reset() API.

Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Bin Shi <Bin.Shi@csr.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Documentation/devicetree/bindings/reset/sirf,rstc.txt [new file with mode: 0644]
arch/arm/boot/dts/atlas6.dtsi
arch/arm/boot/dts/marco.dtsi
arch/arm/boot/dts/prima2.dtsi
arch/arm/mach-prima2/Kconfig
arch/arm/mach-prima2/rstc.c

diff --git a/Documentation/devicetree/bindings/reset/sirf,rstc.txt b/Documentation/devicetree/bindings/reset/sirf,rstc.txt
new file mode 100644 (file)
index 0000000..0505de7
--- /dev/null
@@ -0,0 +1,42 @@
+CSR SiRFSoC Reset Controller
+======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc"
+- reg: should be register base and length as documented in the
+  datasheet
+- #reset-cells: 1, see below
+
+example:
+
+rstc: reset-controller@88010000 {
+       compatible = "sirf,prima2-rstc";
+       reg = <0x88010000 0x1000>;
+       #reset-cells = <1>;
+};
+
+Specifying reset lines connected to IP modules
+==============================================
+
+The reset controller(rstc) manages various reset sources. This module provides
+reset signals for most blocks in system. Those device nodes should specify the
+reset line on the rstc in their resets property, containing a phandle to the
+rstc device node and a RESET_INDEX specifying which module to reset, as described
+in reset.txt.
+
+For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers.
+For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose
+rest_bit is in SW_RST1, its RESET_INDEX is 32~63.
+
+example:
+
+vpp@90020000 {
+       compatible = "sirf,prima2-vpp";
+       reg = <0x90020000 0x10000>;
+       interrupts = <31>;
+       clocks = <&clks 35>;
+       resets = <&rstc 6>;
+};
index f8674bcc4489f0ce09d5409711baddfbb7efae76..f7f9cafb42f5f4257cae2c12ad1baf41bfe230d0 100644 (file)
                                #clock-cells = <1>;
                        };
 
-                       reset-controller@88010000 {
+                       rstc: reset-controller@88010000 {
                                compatible = "sirf,prima2-rstc";
                                reg = <0x88010000 0x1000>;
+                               #reset-cells = <1>;
                        };
 
                        rsc-controller@88020000 {
index 1579c3491ccd5fe5ee0cce9792d519d739843fe4..0c9647d28765469cb1b0ba87bc6c6d85c9565acf 100644 (file)
                        #size-cells = <1>;
                        ranges = <0xc2000000 0xc2000000 0x1000000>;
 
-                       reset-controller@c2000000 {
+                       rstc: reset-controller@c2000000 {
                                compatible = "sirf,marco-rstc";
                                reg = <0xc2000000 0x10000>;
+                               #reset-cells = <1>;
                        };
                };
 
index 0e219932d7cce360ea8011893424ec52979a1bfb..0ca0d7fd7a6e577d9e9b2f01a3bb0170dffea4c0 100644 (file)
                                #clock-cells = <1>;
                        };
 
-                       reset-controller@88010000 {
+                       rstc: reset-controller@88010000 {
                                compatible = "sirf,prima2-rstc";
                                reg = <0x88010000 0x1000>;
+                               #reset-cells = <1>;
                        };
 
                        rsc-controller@88020000 {
index 6988b117fc174a70e049df575417dea3093daa1b..f37a1de1a114ad43994d68cda18838a55bbf331c 100644 (file)
@@ -1,5 +1,6 @@
 config ARCH_SIRF
        bool "CSR SiRF" if ARCH_MULTI_V7
+       select ARCH_HAS_RESET_CONTROLLER
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
index ccb53391147ad008c40b0caf39a6f724bed4f173..a5997674333273533a98b4c644c1d2c5ed198d64 100644 (file)
 #include <linux/device.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/platform_device.h>
 #include <linux/reboot.h>
+#include <linux/reset-controller.h>
+
+#define SIRFSOC_RSTBIT_NUM     64
 
 void __iomem *sirfsoc_rstc_base;
 static DEFINE_MUTEX(rstc_lock);
 
-static struct of_device_id rstc_ids[]  = {
-       { .compatible = "sirf,prima2-rstc" },
-       { .compatible = "sirf,marco-rstc" },
-       {},
-};
-
-static int __init sirfsoc_of_rstc_init(void)
-{
-       struct device_node *np;
-
-       np = of_find_matching_node(NULL, rstc_ids);
-       if (!np) {
-               pr_err("unable to find compatible sirf rstc node in dtb\n");
-               return -ENOENT;
-       }
-
-       sirfsoc_rstc_base = of_iomap(np, 0);
-       if (!sirfsoc_rstc_base)
-               panic("unable to map rstc cpu registers\n");
-
-       of_node_put(np);
-
-       return 0;
-}
-early_initcall(sirfsoc_of_rstc_init);
-
-int sirfsoc_reset_device(struct device *dev)
+static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
+                                       unsigned long sw_reset_idx)
 {
-       u32 reset_bit;
+       u32 reset_bit = sw_reset_idx;
 
-       if (of_property_read_u32(dev->of_node, "reset-bit", &reset_bit))
+       if (reset_bit >= SIRFSOC_RSTBIT_NUM)
                return -EINVAL;
 
        mutex_lock(&rstc_lock);
 
-       if (of_device_is_compatible(dev->of_node, "sirf,prima2-rstc")) {
+       if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) {
                /*
                 * Writing 1 to this bit resets corresponding block. Writing 0 to this
                 * bit de-asserts reset signal of the corresponding block.
                 * datasheet doesn't require explicit delay between the set and clear
                 * of reset bit. it could be shorter if tests pass.
                 */
-               writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
+               writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | (1 << reset_bit),
                        sirfsoc_rstc_base + (reset_bit / 32) * 4);
                msleep(10);
-               writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
+               writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~(1 << reset_bit),
                        sirfsoc_rstc_base + (reset_bit / 32) * 4);
        } else {
                /*
@@ -73,9 +52,9 @@ int sirfsoc_reset_device(struct device *dev)
                 * datasheet doesn't require explicit delay between the set and clear
                 * of reset bit. it could be shorter if tests pass.
                 */
-               writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
+               writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
                msleep(10);
-               writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
+               writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
        }
 
        mutex_unlock(&rstc_lock);
@@ -83,6 +62,52 @@ int sirfsoc_reset_device(struct device *dev)
        return 0;
 }
 
+static struct reset_control_ops sirfsoc_rstc_ops = {
+       .reset = sirfsoc_reset_module,
+};
+
+static struct reset_controller_dev sirfsoc_reset_controller = {
+       .ops = &sirfsoc_rstc_ops,
+       .nr_resets = SIRFSOC_RSTBIT_NUM,
+};
+
+static int sirfsoc_rstc_probe(struct platform_device *pdev)
+{
+       struct device_node *np = pdev->dev.of_node;
+       sirfsoc_rstc_base = of_iomap(np, 0);
+       if (!sirfsoc_rstc_base) {
+               dev_err(&pdev->dev, "unable to map rstc cpu registers\n");
+               return -ENOMEM;
+       }
+
+       sirfsoc_reset_controller.of_node = np;
+
+       reset_controller_register(&sirfsoc_reset_controller);
+
+       return 0;
+}
+
+static const struct of_device_id rstc_ids[]  = {
+       { .compatible = "sirf,prima2-rstc" },
+       { .compatible = "sirf,marco-rstc" },
+       {},
+};
+
+static struct platform_driver sirfsoc_rstc_driver = {
+       .probe          = sirfsoc_rstc_probe,
+       .driver         = {
+               .name   = "sirfsoc_rstc",
+               .owner  = THIS_MODULE,
+               .of_match_table = rstc_ids,
+       },
+};
+
+static int __init sirfsoc_rstc_init(void)
+{
+       return platform_driver_register(&sirfsoc_rstc_driver);
+}
+subsys_initcall(sirfsoc_rstc_init);
+
 #define SIRFSOC_SYS_RST_BIT  BIT(31)
 
 void sirfsoc_restart(enum reboot_mode mode, const char *cmd)