watchdog: at91sam9/wdt: move register header to drivers

move register header to drivers

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>

diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h
deleted file mode 100644 (file)
index fecc2e9..0000000
--- a/arch/arm/mach-at91/include/mach/at91_wdt.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_wdt.h
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Watchdog Timer (WDT) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_WDT_H
-#define AT91_WDT_H
-
-#define AT91_WDT_CR            (AT91_WDT + 0x00)       /* Watchdog Control Register */
-#define                AT91_WDT_WDRSTT         (1    << 0)             /* Restart */
-#define                AT91_WDT_KEY            (0xa5 << 24)            /* KEY Password */
-
-#define AT91_WDT_MR            (AT91_WDT + 0x04)       /* Watchdog Mode Register */
-#define                AT91_WDT_WDV            (0xfff << 0)            /* Counter Value */
-#define                AT91_WDT_WDFIEN         (1     << 12)           /* Fault Interrupt Enable */
-#define                AT91_WDT_WDRSTEN        (1     << 13)           /* Reset Processor */
-#define                AT91_WDT_WDRPROC        (1     << 14)           /* Timer Restart */
-#define                AT91_WDT_WDDIS          (1     << 15)           /* Watchdog Disable */
-#define                AT91_WDT_WDD            (0xfff << 16)           /* Delta Value */
-#define                AT91_WDT_WDDBGHLT       (1     << 28)           /* Debug Halt */
-#define                AT91_WDT_WDIDLEHLT      (1     << 29)           /* Idle Halt */
-
-#define AT91_WDT_SR            (AT91_WDT + 0x08)       /* Watchdog Status Register */
-#define                AT91_WDT_WDUNF          (1 << 0)                /* Watchdog Underflow */
-#define                AT91_WDT_WDERR          (1 << 1)                /* Watchdog Error */
-
-#endif

diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index 5cfbcc55d88a8fd77d95f5cace58a69a9a68a6be..87445b2d72a7375f36290ab7c74a404e0dbeaa21 100644 (file)
--- a/drivers/watchdog/at91sam9_wdt.c
+++ b/drivers/watchdog/at91sam9_wdt.c
@@ -31,7 +31,7 @@
 #include <linux/bitops.h>
 #include <linux/uaccess.h>
 
-#include <mach/at91_wdt.h>
+#include "at91sam9_wdt.h"
 
 #define DRV_NAME "AT91SAM9 Watchdog"
 

diff --git a/drivers/watchdog/at91sam9_wdt.h b/drivers/watchdog/at91sam9_wdt.h
new file mode 100644 (file)
index 0000000..757f9ca
--- /dev/null
+++ b/drivers/watchdog/at91sam9_wdt.h
@@ -0,0 +1,37 @@
+/*
+ * drivers/watchdog/at91sam9_wdt.h
+ *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Watchdog Timer (WDT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_WDT_H
+#define AT91_WDT_H
+
+#define AT91_WDT_CR            (AT91_WDT + 0x00)       /* Watchdog Control Register */
+#define                AT91_WDT_WDRSTT         (1    << 0)             /* Restart */
+#define                AT91_WDT_KEY            (0xa5 << 24)            /* KEY Password */
+
+#define AT91_WDT_MR            (AT91_WDT + 0x04)       /* Watchdog Mode Register */
+#define                AT91_WDT_WDV            (0xfff << 0)            /* Counter Value */
+#define                AT91_WDT_WDFIEN         (1     << 12)           /* Fault Interrupt Enable */
+#define                AT91_WDT_WDRSTEN        (1     << 13)           /* Reset Processor */
+#define                AT91_WDT_WDRPROC        (1     << 14)           /* Timer Restart */
+#define                AT91_WDT_WDDIS          (1     << 15)           /* Watchdog Disable */
+#define                AT91_WDT_WDD            (0xfff << 16)           /* Delta Value */
+#define                AT91_WDT_WDDBGHLT       (1     << 28)           /* Debug Halt */
+#define                AT91_WDT_WDIDLEHLT      (1     << 29)           /* Idle Halt */
+
+#define AT91_WDT_SR            (AT91_WDT + 0x08)       /* Watchdog Status Register */
+#define                AT91_WDT_WDUNF          (1 << 0)                /* Watchdog Underflow */
+#define                AT91_WDT_WDERR          (1 << 1)                /* Watchdog Error */
+
+#endif