arm: dts: qcom: apq8064: Add display DT nodes

APQ8064 contains a MDP4 based display controller. It contains a HDMI, LVDS
and 2 DSI outputs.

Add display DT nodes for MDP4, HDMI TX and HDMI PHY. MDP4 based display
blocks have a flat device hierarchy.

Nodes for other outputs will be added later.

Cc: devicetree@vger.kernel.org
Tested-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 1dbe697b2e90c9cd59da89e999b852fb24bb750b..5b3aaaa7a588a8b9340e914101fdee792c94cdcf 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1095,6 +1095,97 @@
                        reset-names = "axi", "ahb", "por", "pci", "phy";
                        status = "disabled";
                };
+
+               hdmi: hdmi-tx@4a00000 {
+                       compatible = "qcom,hdmi-tx-8960";
+                       reg = <0x04a00000 0x2f0>;
+                       reg-names = "core_physical";
+                       interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&mmcc HDMI_APP_CLK>,
+                                <&mmcc HDMI_M_AHB_CLK>,
+                                <&mmcc HDMI_S_AHB_CLK>;
+                       clock-names = "core_clk",
+                                     "master_iface_clk",
+                                     "slave_iface_clk";
+
+                       phys = <&hdmi_phy>;
+                       phy-names = "hdmi-phy";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       hdmi_in: endpoint {
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       hdmi_out: endpoint {
+                                       };
+                               };
+                       };
+               };
+
+               hdmi_phy: hdmi-phy@4a00400 {
+                       compatible = "qcom,hdmi-phy-8960";
+                       reg = <0x4a00400 0x60>,
+                             <0x4a00500 0x100>;
+                       reg-names = "hdmi_phy",
+                                   "hdmi_pll";
+
+                       clocks = <&mmcc HDMI_S_AHB_CLK>;
+                       clock-names = "slave_iface_clk";
+               };
+
+               mdp: mdp@5100000 {
+                       compatible = "qcom,mdp4";
+                       reg = <0x05100000 0xf0000>;
+                       interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&mmcc MDP_CLK>,
+                                <&mmcc MDP_AHB_CLK>,
+                                <&mmcc MDP_AXI_CLK>,
+                                <&mmcc MDP_LUT_CLK>,
+                                <&mmcc HDMI_TV_CLK>,
+                                <&mmcc MDP_TV_CLK>;
+                       clock-names = "core_clk",
+                                     "iface_clk",
+                                     "bus_clk",
+                                     "lut_clk",
+                                     "hdmi_clk",
+                                     "tv_clk";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       mdp_lvds_out: endpoint {
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       mdp_dsi1_out: endpoint {
+                                       };
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+                                       mdp_dsi2_out: endpoint {
+                                       };
+                               };
+
+                               port@3 {
+                                       reg = <3>;
+                                       mdp_dtv_out: endpoint {
+                                       };
+                               };
+                       };
+               };
        };
 };
 #include "qcom-apq8064-pins.dtsi"