qcom: ipq4019: add i2c node to ipq4019 SoC and DK01 device tree

This will allow boards to enable the I2C bus

CC: Sricharan R <srichara@qti.qualcomm.com>
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 99e64f4881bc3c5b4e558aee91e7ec33fd78c2a0..1937edfdcd7588a7573ffec003e31e228356d51d 100644 (file)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -25,6 +25,7 @@
 
        aliases {
                spi0 = &spi_0;
+               i2c0 = &i2c_0;
        };
 
        cpus {
@@ -126,6 +127,18 @@
                        status = "disabled";
                };
 
+               i2c_0: i2c@78b7000 {
+                       compatible = "qcom,i2c-qup-v2.2.1";
+                       reg = <0x78b7000 0x6000>;
+                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+                                <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+                       clock-names = "iface", "core";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                 acc0: clock-controller@b088000 {
                         compatible = "qcom,kpss-acc-v1";
                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;