ARM: dts: imx6: adopt DT to new GPC binding

Adopt the i.MX6Q/DL DT to the new and more flexible GPC binding.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e9a5d0b8c7b05917f27345c39dab9179f9642052..dd33849335b217f1f9ab79e392ba7df526b8e5ac 100644 (file)
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -125,7 +125,7 @@
                        clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
                                 <&clks IMX6QDL_CLK_GPU2D_CORE>;
                        clock-names = "bus", "core";
-                       power-domains = <&gpc 1>;
+                       power-domains = <&pd_pu>;
                };
 
                ipu2: ipu@02800000 {

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index e426faa9c24379bc3b19c3f859c464649c8c220d..2c2af6737b0e83d1c3801776a575fe33d091690e 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -156,7 +156,7 @@
                                 <&clks IMX6QDL_CLK_GPU3D_CORE>,
                                 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
                        clock-names = "bus", "core", "shader";
-                       power-domains = <&gpc 1>;
+                       power-domains = <&pd_pu>;
                };
 
                gpu_2d: gpu@00134000 {
@@ -166,7 +166,7 @@
                        clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
                                 <&clks IMX6QDL_CLK_GPU2D_CORE>;
                        clock-names = "bus", "core";
-                       power-domains = <&gpc 1>;
+                       power-domains = <&pd_pu>;
                };
 
                timer@00a00600 {
@@ -434,7 +434,7 @@
                                clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
                                         <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
                                clock-names = "per", "ahb";
-                               power-domains = <&gpc 1>;
+                               power-domains = <&pd_pu>;
                                resets = <&src 1>;
                                iram = <&ocram>;
                        };
@@ -797,14 +797,29 @@
                                interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
                                             <0 90 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-parent = <&intc>;
-                               pu-supply = <&reg_pu>;
-                               clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
-                                        <&clks IMX6QDL_CLK_GPU3D_SHADER>,
-                                        <&clks IMX6QDL_CLK_GPU2D_CORE>,
-                                        <&clks IMX6QDL_CLK_GPU2D_AXI>,
-                                        <&clks IMX6QDL_CLK_OPENVG_AXI>,
-                                        <&clks IMX6QDL_CLK_VPU_AXI>;
-                               #power-domain-cells = <1>;
+                               clocks = <&clks IMX6QDL_CLK_IPG>;
+                               clock-names = "ipg";
+
+                               pgc {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       power-domain@0 {
+                                               reg = <0>;
+                                               #power-domain-cells = <0>;
+                                       };
+                                       pd_pu: power-domain@1 {
+                                               reg = <1>;
+                                               #power-domain-cells = <0>;
+                                               power-supply = <&reg_pu>;
+                                               clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+                                                        <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+                                                        <&clks IMX6QDL_CLK_GPU2D_CORE>,
+                                                        <&clks IMX6QDL_CLK_GPU2D_AXI>,
+                                                        <&clks IMX6QDL_CLK_OPENVG_AXI>,
+                                                        <&clks IMX6QDL_CLK_VPU_AXI>;
+                                       };
+                               };
                        };
 
                        gpr: iomuxc-gpr@020e0000 {