drm/i915: extract common link_m_n helpers
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 29 Nov 2012 14:59:36 +0000 (15:59 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 6 Dec 2012 13:37:01 +0000 (14:37 +0100)
Both the dp and fdi code use the exact same computations (ignore minor
differences in conversion between bits and bytes).

This makes it even more apparent that we have a _massive_ mess between
cpu transcoder/fdi link/pch transcoder and pch link settings. And also
that we have hilarious amounts of confusion between edp and dp
(despite that they're identical at a link level).

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_dp.c

index a00ee3da632fea81329fe6c5298f665282d1b2ee..e9ac3603fbdb226fc8628496b403e96abc79dd4a 100644 (file)
@@ -107,6 +107,19 @@ struct intel_pch_pll {
 };
 #define I915_NUM_PLLS 2
 
+/* Used by dp and fdi links */
+struct intel_link_m_n {
+       uint32_t        tu;
+       uint32_t        gmch_m;
+       uint32_t        gmch_n;
+       uint32_t        link_m;
+       uint32_t        link_n;
+};
+
+void intel_link_compute_m_n(int bpp, int nlanes,
+                           int pixel_clock, int link_clock,
+                           struct intel_link_m_n *m_n);
+
 struct intel_ddi_plls {
        int spll_refcount;
        int wrpll1_refcount;
index 953796c84fbdd16d344cbcea488eab8dac515e20..34832bc0493160b2bf33ee50355b6992c2f9fe7e 100644 (file)
@@ -3951,16 +3951,8 @@ static int i830_get_display_clock_speed(struct drm_device *dev)
        return 133000;
 }
 
-struct fdi_m_n {
-       u32        tu;
-       u32        gmch_m;
-       u32        gmch_n;
-       u32        link_m;
-       u32        link_n;
-};
-
 static void
-fdi_reduce_ratio(u32 *num, u32 *den)
+intel_reduce_ratio(uint32_t *num, uint32_t *den)
 {
        while (*num > 0xffffff || *den > 0xffffff) {
                *num >>= 1;
@@ -3968,20 +3960,18 @@ fdi_reduce_ratio(u32 *num, u32 *den)
        }
 }
 
-static void
-ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
-                    int link_clock, struct fdi_m_n *m_n)
+void
+intel_link_compute_m_n(int bits_per_pixel, int nlanes,
+                      int pixel_clock, int link_clock,
+                      struct intel_link_m_n *m_n)
 {
-       m_n->tu = 64; /* default size */
-
-       /* BUG_ON(pixel_clock > INT_MAX / 36); */
+       m_n->tu = 64;
        m_n->gmch_m = bits_per_pixel * pixel_clock;
        m_n->gmch_n = link_clock * nlanes * 8;
-       fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
-
+       intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
        m_n->link_m = pixel_clock;
        m_n->link_n = link_clock;
-       fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
+       intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 }
 
 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
@@ -5095,7 +5085,7 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
        struct intel_encoder *intel_encoder, *edp_encoder = NULL;
-       struct fdi_m_n m_n = {0};
+       struct intel_link_m_n m_n = {0};
        int target_clock, pixel_multiplier, lane, link_bw;
        bool is_dp = false, is_cpu_edp = false;
 
@@ -5153,8 +5143,7 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
 
        if (pixel_multiplier > 1)
                link_bw *= pixel_multiplier;
-       ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
-                            &m_n);
+       intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
 
        I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
        I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
index 84652ca3b161a2a1da301e2a71ab485cf95c6504..b2130bc6c29707598ad1667bc5f4786d5ec1aa21 100644 (file)
@@ -790,39 +790,6 @@ intel_dp_mode_fixup(struct drm_encoder *encoder,
        return false;
 }
 
-struct intel_dp_m_n {
-       uint32_t        tu;
-       uint32_t        gmch_m;
-       uint32_t        gmch_n;
-       uint32_t        link_m;
-       uint32_t        link_n;
-};
-
-static void
-intel_reduce_ratio(uint32_t *num, uint32_t *den)
-{
-       while (*num > 0xffffff || *den > 0xffffff) {
-               *num >>= 1;
-               *den >>= 1;
-       }
-}
-
-static void
-intel_dp_compute_m_n(int bpp,
-                    int nlanes,
-                    int pixel_clock,
-                    int link_clock,
-                    struct intel_dp_m_n *m_n)
-{
-       m_n->tu = 64;
-       m_n->gmch_m = (pixel_clock * bpp) >> 3;
-       m_n->gmch_n = link_clock * nlanes;
-       intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
-       m_n->link_m = pixel_clock;
-       m_n->link_n = link_clock;
-       intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
-}
-
 void
 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
                 struct drm_display_mode *adjusted_mode)
@@ -833,7 +800,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int lane_count = 4;
-       struct intel_dp_m_n m_n;
+       struct intel_link_m_n m_n;
        int pipe = intel_crtc->pipe;
        enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 
@@ -856,8 +823,8 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
         * the number of bytes_per_pixel post-LUT, which we always
         * set up for 8-bits of R/G/B, or 3 bytes total.
         */
-       intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
-                            mode->clock, adjusted_mode->clock, &m_n);
+       intel_link_compute_m_n(intel_crtc->bpp, lane_count,
+                              mode->clock, adjusted_mode->clock, &m_n);
 
        if (IS_HASWELL(dev)) {
                I915_WRITE(PIPE_DATA_M1(cpu_transcoder),