drm/amdgpu: use new flag to handle different firmware loading method
authorHuang Rui <ray.huang@amd.com>
Tue, 1 Nov 2016 07:35:38 +0000 (15:35 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 30 Mar 2017 03:54:33 +0000 (23:54 -0400)
This patch introduces a new flag named "amdgpu_firmware_load_type" to
handle different firmware loading method. Since Vega10, there are
three ways to load firmware. It would be better to use a flag and a
fw_load_type kernel parameter to configure it.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
drivers/gpu/drm/amd/amdgpu/cik.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
drivers/gpu/drm/amd/amdgpu/vi.c

index a7108ba947947ed4c569a51461e4568f225f0b0f..c83d7bd5b71215a2f7864bd763b875ecaef02c7f 100644 (file)
@@ -81,7 +81,7 @@ extern int amdgpu_pcie_gen2;
 extern int amdgpu_msi;
 extern int amdgpu_lockup_timeout;
 extern int amdgpu_dpm;
-extern int amdgpu_smc_load_fw;
+extern int amdgpu_fw_load_type;
 extern int amdgpu_aspm;
 extern int amdgpu_runtime_pm;
 extern unsigned amdgpu_ip_block_mask;
@@ -1063,9 +1063,15 @@ struct amdgpu_sdma {
 /*
  * Firmware
  */
+enum amdgpu_firmware_load_type {
+       AMDGPU_FW_LOAD_DIRECT = 0,
+       AMDGPU_FW_LOAD_SMU,
+       AMDGPU_FW_LOAD_PSP,
+};
+
 struct amdgpu_firmware {
        struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
-       bool smu_load;
+       enum amdgpu_firmware_load_type load_type;
        struct amdgpu_bo *fw_buf;
        unsigned int fw_size;
 };
index 778d16f835ab856f9945d78ee84966218e549d25..7292f4e7bb1a0255c439fd741e4bc270c8c8a3d1 100644 (file)
@@ -80,7 +80,7 @@ int amdgpu_pcie_gen2 = -1;
 int amdgpu_msi = -1;
 int amdgpu_lockup_timeout = 0;
 int amdgpu_dpm = -1;
-int amdgpu_smc_load_fw = 1;
+int amdgpu_fw_load_type = -1;
 int amdgpu_aspm = -1;
 int amdgpu_runtime_pm = -1;
 unsigned amdgpu_ip_block_mask = 0xffffffff;
@@ -140,8 +140,8 @@ module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
 module_param_named(dpm, amdgpu_dpm, int, 0444);
 
-MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)");
-module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444);
+MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
+module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
 
 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
 module_param_named(aspm, amdgpu_aspm, int, 0444);
index d56d200a3646b412d22b64a96faa19e2c6c55d39..96a5113b948fcace6a98c1e41505c943bd46ee04 100644 (file)
@@ -163,7 +163,7 @@ static int amdgpu_pp_hw_init(void *handle)
        int ret = 0;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       if (adev->pp_enabled && adev->firmware.smu_load)
+       if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
                amdgpu_ucode_init_bo(adev);
 
        if (adev->powerplay.ip_funcs->hw_init)
@@ -190,7 +190,7 @@ static int amdgpu_pp_hw_fini(void *handle)
                ret = adev->powerplay.ip_funcs->hw_fini(
                                        adev->powerplay.pp_handle);
 
-       if (adev->pp_enabled && adev->firmware.smu_load)
+       if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
                amdgpu_ucode_fini_bo(adev);
 
        return ret;
index be16377128c32b55d5138d45fe452c98a35ef77a..73c3e664d99a5f202bec25a9b5d3132cc56b1dc1 100644 (file)
@@ -217,6 +217,49 @@ bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
        return true;
 }
 
+enum amdgpu_firmware_load_type
+amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
+{
+       switch (adev->asic_type) {
+#ifdef CONFIG_DRM_AMDGPU_SI
+       case CHIP_TAHITI:
+       case CHIP_PITCAIRN:
+       case CHIP_VERDE:
+       case CHIP_OLAND:
+               return AMDGPU_FW_LOAD_DIRECT;
+#endif
+#ifdef CONFIG_DRM_AMDGPU_CIK
+       case CHIP_BONAIRE:
+       case CHIP_KAVERI:
+       case CHIP_KABINI:
+       case CHIP_HAWAII:
+       case CHIP_MULLINS:
+               return AMDGPU_FW_LOAD_DIRECT;
+#endif
+       case CHIP_TOPAZ:
+       case CHIP_TONGA:
+       case CHIP_FIJI:
+       case CHIP_CARRIZO:
+       case CHIP_STONEY:
+       case CHIP_POLARIS10:
+       case CHIP_POLARIS11:
+       case CHIP_POLARIS12:
+               if (!load_type)
+                       return AMDGPU_FW_LOAD_DIRECT;
+               else
+                       return AMDGPU_FW_LOAD_SMU;
+       case CHIP_VEGA10:
+               if (!load_type)
+                       return AMDGPU_FW_LOAD_DIRECT;
+               else
+                       return AMDGPU_FW_LOAD_PSP;
+       default:
+               DRM_ERROR("Unknow firmware load type\n");
+       }
+
+       return AMDGPU_FW_LOAD_DIRECT;
+}
+
 static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode,
                                uint64_t mc_addr, void *kptr)
 {
@@ -273,7 +316,7 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
        uint64_t fw_mc_addr;
        void *fw_buf_ptr = NULL;
        uint64_t fw_offset = 0;
-       int i, err;
+       int i, err, max;
        struct amdgpu_firmware_info *ucode = NULL;
        const struct common_firmware_header *header = NULL;
 
@@ -306,7 +349,16 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
 
        amdgpu_bo_unreserve(*bo);
 
-       for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) {
+       /*
+        * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
+        * ucode info here
+        */
+       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
+               max = AMDGPU_UCODE_ID_MAXIMUM - 3;
+       else
+               max = AMDGPU_UCODE_ID_MAXIMUM;
+
+       for (i = 0; i < max; i++) {
                ucode = &adev->firmware.ucode[i];
                if (ucode->fw) {
                        header = (const struct common_firmware_header *)ucode->fw->data;
@@ -331,7 +383,8 @@ failed_pin:
 failed_reserve:
        amdgpu_bo_unref(bo);
 failed:
-       adev->firmware.smu_load = false;
+       if (err)
+               adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
 
        return err;
 }
@@ -340,8 +393,14 @@ int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
 {
        int i;
        struct amdgpu_firmware_info *ucode = NULL;
+       int max;
+
+       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
+               max = AMDGPU_UCODE_ID_MAXIMUM - 3;
+       else
+               max = AMDGPU_UCODE_ID_MAXIMUM;
 
-       for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) {
+       for (i = 0; i < max; i++) {
                ucode = &adev->firmware.ucode[i];
                if (ucode->fw) {
                        ucode->mc_addr = 0;
index 19a584cd452702dc2ba685ee7562d5534869ede1..2b212b04ce54a982da70889e46c4cd91ea95c4fe 100644 (file)
@@ -176,4 +176,7 @@ bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
 int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
 int amdgpu_ucode_fini_bo(struct amdgpu_device *adev);
 
+enum amdgpu_firmware_load_type
+amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
+
 #endif
index dbaedb4f2a6bb26620f04b452f1902e13f9eaf2e..9d33e56414194d4fc22d378c26140adae0d25c6a 100644 (file)
@@ -1785,6 +1785,8 @@ static int cik_common_early_init(void *handle)
                return -EINVAL;
        }
 
+       adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
+
        amdgpu_get_pcie_info(adev);
 
        return 0;
index 1e177cd9b46b79aa04a50563f1adba8b45b62cc5..423ed68c2e529b218e5be9884e3692ae82c31eec 100644 (file)
@@ -1040,7 +1040,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
                }
        }
 
-       if (adev->firmware.smu_load) {
+       if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
                info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
                info->fw = adev->gfx.pfp_fw;
@@ -4253,7 +4253,7 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
        gfx_v8_0_init_pg(adev);
 
        if (!adev->pp_enabled) {
-               if (!adev->firmware.smu_load) {
+               if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
                        /* legacy rlc firmware loading */
                        r = gfx_v8_0_rlc_load_microcode(adev);
                        if (r)
@@ -5269,7 +5269,7 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
                gfx_v8_0_enable_gui_idle_interrupt(adev, false);
 
        if (!adev->pp_enabled) {
-               if (!adev->firmware.smu_load) {
+               if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
                        /* legacy firmware loading */
                        r = gfx_v8_0_cp_gfx_load_microcode(adev);
                        if (r)
index 1a4b351f350b4fc1e2904fda3136257a183c1187..182de5dc20815f47de8d2756a0d38f832fda9824 100644 (file)
@@ -158,7 +158,7 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
                if (adev->sdma.instance[i].feature_version >= 20)
                        adev->sdma.instance[i].burst_nop = true;
 
-               if (adev->firmware.smu_load) {
+               if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
                        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
                        info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
                        info->fw = adev->sdma.instance[i].fw;
@@ -562,7 +562,7 @@ static int sdma_v2_4_start(struct amdgpu_device *adev)
        int r;
 
        if (!adev->pp_enabled) {
-               if (!adev->firmware.smu_load) {
+               if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
                        r = sdma_v2_4_load_microcode(adev);
                        if (r)
                                return r;
index 5f7812d1c90d9ef177a90ad56cf724bddd560da6..5be84df27cad8c2bad090b027da94248ac35d3db 100644 (file)
@@ -310,7 +310,7 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
                if (adev->sdma.instance[i].feature_version >= 20)
                        adev->sdma.instance[i].burst_nop = true;
 
-               if (adev->firmware.smu_load) {
+               if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
                        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
                        info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
                        info->fw = adev->sdma.instance[i].fw;
@@ -771,7 +771,7 @@ static int sdma_v3_0_start(struct amdgpu_device *adev)
        int r, i;
 
        if (!adev->pp_enabled) {
-               if (!adev->firmware.smu_load) {
+               if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
                        r = sdma_v3_0_load_microcode(adev);
                        if (r)
                                return r;
index 1ff36724fb2ab29ae2c55f7f2df46a5d2e7012d1..1fe654e8cb7fd805a9322ae7bcea9b0614b2894b 100644 (file)
@@ -1117,8 +1117,8 @@ static int vi_common_early_init(void *handle)
                return -EINVAL;
        }
 
-       if (amdgpu_smc_load_fw && smc_enabled)
-               adev->firmware.smu_load = true;
+       /* vi use smc load by default */
+       adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
 
        amdgpu_get_pcie_info(adev);