cxgb4: fix large delays in PTP synchronization

[ Upstream commit bd019427bf3623ee3c7d2845cf921bbf4c14846c ]

Fetching PTP sync information from mailbox is slow and can take
up to 10 milliseconds. Reduce this unnecessary delay by directly
reading the information from the corresponding registers.

Fixes: 9c33e4208bce ("cxgb4: Add PTP Hardware Clock (PHC) support")
Signed-off-by: Manoj Malviya <manojmalviya@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c
index 758f2b8363282ab1fc1bbed2d6b9d76e23e6ac8a..ff7e58a8c90fb59c14472ecaf85ecae5c9febd36 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c
@@ -311,32 +311,17 @@ static int cxgb4_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
  */
 static int cxgb4_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
 {
-       struct adapter *adapter = (struct adapter *)container_of(ptp,
-                                  struct adapter, ptp_clock_info);
-       struct fw_ptp_cmd c;
+       struct adapter *adapter = container_of(ptp, struct adapter,
+                                              ptp_clock_info);
        u64 ns;
-       int err;
-
-       memset(&c, 0, sizeof(c));
-       c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PTP_CMD) |
-                                    FW_CMD_REQUEST_F |
-                                    FW_CMD_READ_F |
-                                    FW_PTP_CMD_PORTID_V(0));
-       c.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(sizeof(c) / 16));
-       c.u.ts.sc = FW_PTP_SC_GET_TIME;
 
-       err = t4_wr_mbox(adapter, adapter->mbox, &c, sizeof(c), &c);
-       if (err < 0) {
-               dev_err(adapter->pdev_dev,
-                       "PTP: %s error %d\n", __func__, -err);
-               return err;
-       }
+       ns = t4_read_reg(adapter, T5_PORT_REG(0, MAC_PORT_PTP_SUM_LO_A));
+       ns |= (u64)t4_read_reg(adapter,
+                              T5_PORT_REG(0, MAC_PORT_PTP_SUM_HI_A)) << 32;
 
        /* convert to timespec*/
-       ns = be64_to_cpu(c.u.ts.tm);
        *ts = ns_to_timespec64(ns);
-
-       return err;
+       return 0;
 }
 
 /**

diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
index dac90837842bf1b20e93f8d0810dada4e5c34292..d3df6962cf433d8ad9a0ded83fea9677f2f72c0e 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
@@ -1810,6 +1810,9 @@
 
 #define MAC_PORT_CFG2_A 0x818
 
+#define MAC_PORT_PTP_SUM_LO_A 0x990
+#define MAC_PORT_PTP_SUM_HI_A 0x994
+
 #define MPS_CMN_CTL_A  0x9000
 
 #define COUNTPAUSEMCRX_S    5