drm/i915: Only preallocate the aliasing GTT to the extents of the global GTT
authorChris Wilson <chris@chris-wilson.co.uk>
Wed, 15 Feb 2017 08:43:55 +0000 (08:43 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Wed, 15 Feb 2017 10:07:33 +0000 (10:07 +0000)
As the aliasing GTT is only accessed via the global GTT, we will never
use more of it than we expose via the Global GTT and so we only need to
preallocate sufficient space within the ppgtt for the full GTT. Equally,
if the aliasing GTT is smaller than the global GTT, we have a serious
issue and must bail.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170215084357.19977-21-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/i915_gem_gtt.c

index ebd87c3373941242105622e7caa19715cee40bdb..7fbb1080431997fd52fd90c16c87c7cabd8c7331 100644 (file)
@@ -2384,9 +2384,19 @@ int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915)
        if (IS_ERR(ppgtt))
                return PTR_ERR(ppgtt);
 
+       if (WARN_ON(ppgtt->base.total < ggtt->base.total)) {
+               err = -ENODEV;
+               goto err_ppgtt;
+       }
+
        if (ppgtt->base.allocate_va_range) {
+               /* Note we only pre-allocate as far as the end of the global
+                * GTT. On 48b / 4-level page-tables, the difference is very,
+                * very significant! We have to preallocate as GVT/vgpu does
+                * not like the page directory disappearing.
+                */
                err = ppgtt->base.allocate_va_range(&ppgtt->base,
-                                                   0, ppgtt->base.total);
+                                                   0, ggtt->base.total);
                if (err)
                        goto err_ppgtt;
        }