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msm: 8x60: setup correct handlers for private interrupts
authorAbhijeet Dharmapurikar <adharmap@codeaurora.org>
Mon, 1 Feb 2010 20:30:28 +0000 (12:30 -0800)
committerDaniel Walker <dwalker@codeaurora.org>
Fri, 8 Oct 2010 22:12:45 +0000 (15:12 -0700)
Private Peripheral interrupts could be edge triggered or level triggered
depending on the platform. Initialize handlers for these in board file.

Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
arch/arm/mach-msm/board-msm8x60.c patch | blob | blame | history

diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index e7feb99b5cfe8df566913d3f8c099c5b0e8961ad..70087cad6731003c62b8602798cb65bd1b907740 100644 (file)
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -44,7 +44,7 @@ static void __init msm8x60_init_irq(void)
 {
        unsigned int i;
 
-       gic_dist_init(0, MSM_QGIC_DIST_BASE, 1);
+       gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
        gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
        gic_cpu_init(0, MSM_QGIC_CPU_BASE);